nativeInst_sparc.cpp revision 1472
/*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/
# include "incls/_precompiled.incl"
# include "incls/_nativeInst_sparc.cpp.incl"
bool NativeInstruction::is_dtrace_trap() {
return !is_nop();
}
// Generate a the new sequence
}
void NativeInstruction::verify() {
// make sure code pattern is actually an instruction address
fatal("not an instruction address");
}
}
void NativeInstruction::print() {
}
*(int*)addr = i;
}
// Don't need to invalidate 2 words here, because
// the flush instruction operates on doublewords.
}
// Don't need to invalidate 2 words here in the 64-bit case,
// because the flush instruction operates on doublewords.
// The Intel code has this assertion for NativeCall::set_destination,
// NativeMovConstReg::set_data, NativeMovRegMem::set_offset,
// NativeJump::set_jump_destination, and NativePushImm32::set_data
//assert (Patching_lock->owned_by_self(), "must hold lock to patch instruction")
}
int x = long_at(0);
return true;
return true;
}
}
return false;
}
int x = long_at(0);
return true;
}
return false;
}
void NativeCall::verify() {
// make sure code pattern is actually a call instruction
fatal("not a call");
}
}
void NativeCall::print() {
}
// MT-safe patching of a call instruction (and following word).
// First patches the second word, and then atomicly replaces
// the first word with the first new instruction word.
// Other processors might briefly see the old first word
// followed by the new second word. This is OK if the old
// second word is harmless, and the new second word may be
// harmlessly executed in the delay slot of the call.
int i0 = ((int*)code_buffer)[0];
"must not interfere with original call");
// The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order
// NOTE: It is possible that another thread T will execute
// only the second patched word.
// In other words, since the original instruction is this
// call patching_stub; nop (NativeCall)
// and the new sequence from the buffer is this:
// sethi %hi(K), %r; add %r, %lo(K), %r (NativeMovConstReg)
// what T will execute is this:
// call patching_stub; add %r, %lo(K), %r
// thereby putting garbage into %r before calling the patching stub.
// This is OK, because the patching stub ignores the value of %r.
// Make sure the first-patched instruction, which may co-exist
// briefly with the call, will do something harmless.
"must not interfere with original call");
}
// Similar to replace_mt_safe, but just changes the destination. The
// important thing is that free-running threads are able to execute this
// call instruction at all times. Thus, the displacement field must be
// instruction-word-aligned. This is always true on SPARC.
//
// Used in the runtime linkage of calls; see class CompiledIC.
// set_destination uses set_long_at which does the ICache::invalidate
}
// Code for unit testing implementation of NativeCall class
void NativeCall::test() {
#ifdef ASSERT
NativeCall *nc;
int offsets[] = {
0x0,
0xfffffff0,
0x7ffffff0,
0x80000000,
0x20,
0x4000,
};
VM_Version::allow_all();
}
VM_Version::revert();
#endif
}
// End code for unit testing implementation of NativeCall class
//-------------------------------------------------------------------
#ifdef _LP64
// Address materialized in the instruction stream, so nothing to do.
return;
#if 0 // What we'd do if we really did want to change the destination
if (destination() == dest) {
return;
}
// Generate the new sequence
#endif
}
void NativeFarCall::verify() {
// make sure code pattern is actually a jumpl_to instruction
}
}
void NativeFarCall::print() {
}
return false;
} else {
}
}
// MT-safe patching of a far call.
}
// Code for unit testing implementation of NativeFarCall class
void NativeFarCall::test() {
}
// End code for unit testing implementation of NativeFarCall class
#endif // _LP64
//-------------------------------------------------------------------
void NativeMovConstReg::verify() {
// make sure code pattern is actually a "set_oop" synthetic instruction
// see MacroAssembler::set_oop()
// verify the pattern "sethi %hi22(imm), reg ; add reg, %lo10(imm), reg"
#ifndef _LP64
fatal("not a set_oop");
}
#else
fatal("not a set_oop");
}
#endif
}
void NativeMovConstReg::print() {
}
#ifdef _LP64
}
#else
}
#endif
#ifdef _LP64
#else
#endif
// also store the value into an oop_Relocation cell, if any
} else {
}
}
}
}
}
// Code for unit testing implementation of NativeMovConstReg class
void NativeMovConstReg::test() {
#ifdef ASSERT
int offsets[] = {
0x0,
0x7fffffff,
0x80000000,
0xffffffff,
0x20,
4096,
4097,
};
VM_Version::allow_all();
}
VM_Version::revert();
#endif
}
// End code for unit testing implementation of NativeMovConstReg class
//-------------------------------------------------------------------
void NativeMovConstRegPatching::verify() {
// Verify the pattern "sethi %hi22(imm), reg; nop; add reg, %lo10(imm), reg"
// The casual reader should note that on Sparc a nop is a special case if sethi
// in which the destination register is %g0.
fatal("not a set_oop");
}
}
void NativeMovConstRegPatching::print() {
}
int NativeMovConstRegPatching::data() const {
#ifdef _LP64
#else
#endif
}
void NativeMovConstRegPatching::set_data(int x) {
#ifdef _LP64
#else
#endif
// also store the value into an oop_Relocation cell, if any
} else {
}
}
}
}
}
// Code for unit testing implementation of NativeMovConstRegPatching class
void NativeMovConstRegPatching::test() {
#ifdef ASSERT
int offsets[] = {
0x0,
0x7fffffff,
0x80000000,
0xffffffff,
0x20,
4096,
4097,
};
VM_Version::allow_all();
a->nop();
a->nop();
}
VM_Version::revert();
#endif // ASSERT
}
// End code for unit testing implementation of NativeMovConstRegPatching class
//-------------------------------------------------------------------
Untested("copy_instruction_to");
for (int i = 0; i < instruction_size; i += BytesPerInstWord) {
*(int*)(new_instruction_address + i) = *(int*)(address(this) + i);
}
}
void NativeMovRegMem::verify() {
// make sure code pattern is actually a "ld" or "st" of some sort.
0 != (op3 < op3_ldst_int_limit
{
0 != (op3 < op3_ldst_int_limit
fatal("not a ld* or st* op");
}
}
}
void NativeMovRegMem::print() {
if (is_immediate()) {
} else {
}
}
// Code for unit testing implementation of NativeMovRegMem class
void NativeMovRegMem::test() {
#ifdef ASSERT
int offsets[] = {
0x0,
0xffffffff,
0x7fffffff,
0x80000000,
4096,
4097,
0x20,
0x4000,
};
VM_Version::allow_all();
while (--idx) {
"check unit test");
}
}
VM_Version::revert();
#endif // ASSERT
}
// End code for unit testing implementation of NativeMovRegMem class
//--------------------------------------------------------------------------------
Untested("copy_instruction_to");
for (int i = 0; i < instruction_size; i += wordSize) {
*(long*)(new_instruction_address + i) = *(long*)(address(this) + i);
}
}
void NativeMovRegMemPatching::verify() {
// make sure code pattern is actually a "ld" or "st" of some sort.
0 != (op3 < op3_ldst_int_limit
0 != (op3 < op3_ldst_int_limit
fatal("not a ld* or st* op");
}
}
}
void NativeMovRegMemPatching::print() {
if (is_immediate()) {
} else {
}
}
// Code for unit testing implementation of NativeMovRegMemPatching class
void NativeMovRegMemPatching::test() {
#ifdef ASSERT
int offsets[] = {
0x0,
0xffffffff,
0x7fffffff,
0x80000000,
4096,
4097,
0x20,
0x4000,
};
VM_Version::allow_all();
while (--idx) {
"check unit test");
}
}
VM_Version::revert();
#endif // ASSERT
}
// End code for unit testing implementation of NativeMovRegMemPatching class
//--------------------------------------------------------------------------------
void NativeJump::verify() {
// verify the pattern "sethi %hi22(imm), treg ; jmpl treg, %lo10(imm), lreg"
#ifndef _LP64
fatal("not a jump_to instruction");
}
#else
// In LP64, the jump instruction location varies for non relocatable
// jumps, for example is could be sethi, xor, jmp instead of the
// 7 instructions for sethi. So let's check sethi only.
fatal("not a jump_to instruction");
}
#endif
}
void NativeJump::print() {
tty->print_cr(INTPTR_FORMAT ": jmpl reg, " INTPTR_FORMAT, instruction_address(), jump_destination());
}
// Code for unit testing implementation of NativeJump class
void NativeJump::test() {
#ifdef ASSERT
NativeJump* nj;
int offsets[] = {
0x0,
0xffffffff,
0x7fffffff,
0x80000000,
4096,
4097,
0x20,
0x4000,
};
VM_Version::allow_all();
}
VM_Version::revert();
#endif // ASSERT
}
// End code for unit testing implementation of NativeJump class
}
// MT safe inserting of a jump over an unknown instruction sequence (used by nmethod::makeZombie)
// The problem: jump_to <dest> is a 3-word instruction (including its delay slot).
// Atomic write can be only with 1 word.
// Here's one way to do it: Pre-allocate a three-word jump sequence somewhere
// in the header of the nmethod, within a short branch's span of the patch point.
// Set up the jump sequence using NativeJump::insert, and then use an annulled
// unconditional branch at the target site (an atomic 1-word update).
// Limitations: You can only patch nmethods, with any given nmethod patched at
// most once, and the patch must be in the nmethod's header.
// It's messy, but you can ask the CodeCache for the nmethod containing the
// target address.
// %%%%% For now, do something MT-stupid:
if (VM_Version::v9_instructions_work()) {
} else {
}
}
}
static int illegal_instruction_bits = 0;
int NativeInstruction::illegal_instruction() {
if (illegal_instruction_bits == 0) {
char buf[40];
}
return illegal_instruction_bits;
}
static int ic_miss_trap_bits = 0;
bool NativeInstruction::is_ic_miss_trap() {
if (ic_miss_trap_bits == 0) {
char buf[40];
}
return long_at(0) == ic_miss_trap_bits;
}
bool NativeInstruction::is_illegal() {
if (illegal_instruction_bits == 0) {
return false;
}
return long_at(0) == illegal_instruction_bits;
}
void NativeGeneralJump::verify() {
}
ni->set_long_at(0, x);
}
// MT-safe patching of a jmp instruction (and following word).
// First patches the second word, and then atomicly replaces
// the first word with the first new instruction word.
// Other processors might briefly see the old first word
// followed by the new second word. This is OK if the old
// second word is harmless, and the new second word may be
// harmlessly executed in the delay slot of the call.
int i0 = ((int*)code_buffer)[0];
"must not interfere with original call");
// The set_long_at calls do the ICacheInvalidate so we just need to do them in reverse order
// NOTE: It is possible that another thread T will execute
// only the second patched word.
// In other words, since the original instruction is this
// jmp patching_stub; nop (NativeGeneralJump)
// and the new sequence from the buffer is this:
// sethi %hi(K), %r; add %r, %lo(K), %r (NativeMovConstReg)
// what T will execute is this:
// jmp patching_stub; add %r, %lo(K), %r
// thereby putting garbage into %r before calling the patching stub.
// This is OK, because the patching stub ignores the value of %r.
// Make sure the first-patched instruction, which may co-exist
// briefly with the call, will do something harmless.
"must not interfere with original call");
}