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0N/A
1879N/A#ifndef CPU_SPARC_VM_GLOBALS_SPARC_HPP
1879N/A#define CPU_SPARC_VM_GLOBALS_SPARC_HPP
1879N/A
1879N/A#include "utilities/globalDefinitions.hpp"
1879N/A#include "utilities/macros.hpp"
1879N/A
0N/A// Sets the default values for platform dependent flags used by the runtime system.
0N/A// (see globals.hpp)
0N/A
0N/A// For sparc we do not do call backs when a thread is in the interpreter, because the
0N/A// interpreter dispatch needs at least two instructions - first to load the dispatch address
0N/A// in a register, and second to jmp. The swapping of the dispatch table may occur _after_
0N/A// the load of the dispatch address and hence the jmp would still go to the location
0N/A// according to the prior table. So, we let the thread continue and let it block by itself.
0N/Adefine_pd_global(bool, DontYieldALot, true); // yield no more than 100 times per second
0N/Adefine_pd_global(bool, ConvertSleepToYield, false); // do not convert sleep(0) to yield. Helps GUI
0N/Adefine_pd_global(bool, ShareVtableStubs, false); // improves performance markedly for mtrt and compress
0N/Adefine_pd_global(bool, CountInterpCalls, false); // not implemented in the interpreter
0N/Adefine_pd_global(bool, NeedsDeoptSuspend, true); // register window machines need this
0N/A
0N/Adefine_pd_global(bool, ImplicitNullChecks, true); // Generate code for implicit null checks
0N/Adefine_pd_global(bool, UncommonNullCast, true); // Uncommon-trap NULLs past to check cast
0N/A
1064N/Adefine_pd_global(intx, CodeEntryAlignment, 32);
1365N/A// The default setting 16/16 seems to work best.
1365N/A// (For _228_jack 16/16 is 2% better than 4/4, 16/4, 32/32, 32/16, or 16/32.)
1365N/Adefine_pd_global(intx, OptoLoopAlignment, 16); // = 4*wordSize
1064N/Adefine_pd_global(intx, InlineFrequencyCount, 50); // we can use more inlining on the SPARC
1064N/Adefine_pd_global(intx, InlineSmallCode, 1500);
2215N/A
0N/A#ifdef _LP64
0N/A// Stack slots are 2X larger in LP64 than in the 32 bit VM.
1064N/Adefine_pd_global(intx, ThreadStackSize, 1024);
1064N/Adefine_pd_global(intx, VMThreadStackSize, 1024);
3214N/Adefine_pd_global(intx, StackShadowPages, 10 DEBUG_ONLY(+1));
0N/A#else
1064N/Adefine_pd_global(intx, ThreadStackSize, 512);
1064N/Adefine_pd_global(intx, VMThreadStackSize, 512);
3214N/Adefine_pd_global(intx, StackShadowPages, 3 DEBUG_ONLY(+1));
0N/A#endif
0N/A
0N/Adefine_pd_global(intx, StackYellowPages, 2);
0N/Adefine_pd_global(intx, StackRedPages, 1);
0N/A
1064N/Adefine_pd_global(intx, PreInflateSpin, 40); // Determined by running design center
0N/A
0N/Adefine_pd_global(bool, RewriteBytecodes, true);
0N/Adefine_pd_global(bool, RewriteFrequentPairs, true);
1788N/A
1788N/Adefine_pd_global(bool, UseMembar, false);
1879N/A
2215N/A// GC Ergo Flags
2215N/Adefine_pd_global(intx, CMSYoungGenPerWorker, 16*M); // default max size of CMS young gen, per GC worker thread
3983N/A
3983N/A#define ARCH_FLAGS(develop, product, diagnostic, experimental, notproduct) \
3983N/A \
3983N/A product(intx, UseVIS, 99, \
3983N/A "Highest supported VIS instructions set on Sparc") \
3983N/A \
3983N/A product(bool, UseCBCond, false, \
3983N/A "Use compare and branch instruction on SPARC") \
3983N/A \
3983N/A product(bool, UseBlockZeroing, false, \
3983N/A "Use special cpu instructions for block zeroing") \
3983N/A \
3983N/A product(intx, BlockZeroingLowLimit, 2048, \
3983N/A "Minimum size in bytes when block zeroing will be used") \
3983N/A \
3983N/A product(bool, UseBlockCopy, false, \
3983N/A "Use special cpu instructions for block copy") \
3983N/A \
3983N/A product(intx, BlockCopyLowLimit, 2048, \
3983N/A "Minimum size in bytes when block copy will be used") \
3983N/A \
3983N/A develop(bool, UseV8InstrsOnly, false, \
3983N/A "Use SPARC-V8 Compliant instruction subset") \
3983N/A \
3983N/A product(bool, UseNiagaraInstrs, false, \
3983N/A "Use Niagara-efficient instruction subset") \
3983N/A \
3983N/A develop(bool, UseCASForSwap, false, \
3983N/A "Do not use swap instructions, but only CAS (in a loop) on SPARC")\
3983N/A \
3983N/A product(uintx, ArraycopySrcPrefetchDistance, 0, \
3983N/A "Distance to prefetch source array in arracopy") \
3983N/A \
3983N/A product(uintx, ArraycopyDstPrefetchDistance, 0, \
3983N/A "Distance to prefetch destination array in arracopy") \
3983N/A \
3983N/A develop(intx, V8AtomicOperationUnderLockSpinCount, 50, \
3983N/A "Number of times to spin wait on a v8 atomic operation lock") \
3983N/A
1879N/A#endif // CPU_SPARC_VM_GLOBALS_SPARC_HPP