0N/A/*
1707N/A * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
0N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
0N/A *
0N/A * This code is free software; you can redistribute it and/or modify it
0N/A * under the terms of the GNU General Public License version 2 only, as
0N/A * published by the Free Software Foundation.
0N/A *
0N/A * This code is distributed in the hope that it will be useful, but WITHOUT
0N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
0N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
0N/A * version 2 for more details (a copy is included in the LICENSE file that
0N/A * accompanied this code).
0N/A *
0N/A * You should have received a copy of the GNU General Public License version
0N/A * 2 along with this work; if not, write to the Free Software Foundation,
0N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
0N/A *
1472N/A * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
1472N/A * or visit www.oracle.com if you need additional information or have any
1472N/A * questions.
0N/A *
0N/A */
0N/A
1879N/A#ifndef CPU_SPARC_VM_FRAME_SPARC_HPP
1879N/A#define CPU_SPARC_VM_FRAME_SPARC_HPP
1879N/A
1879N/A#include "runtime/synchronizer.hpp"
1879N/A#include "utilities/top.hpp"
1879N/A
0N/A// A frame represents a physical stack frame (an activation). Frames can be
0N/A// C or Java frames, and the Java frames can be interpreted or compiled.
0N/A// In contrast, vframes represent source-level activations, so that one physical frame
0N/A// can correspond to multiple source level frames because of inlining.
0N/A// A frame is comprised of {pc, sp, younger_sp}
0N/A
0N/A
0N/A// Layout of asm interpreter frame:
0N/A//
0N/A// 0xfffffff
0N/A// ......
0N/A// [last extra incoming arg, (local # Nargs > 6 ? Nargs-1 : undef)]
0N/A// .. Note: incoming args are copied to local frame area upon entry
0N/A// [first extra incoming arg, (local # Nargs > 6 ? 6 : undef)]
0N/A// [6 words for C-arg storage (unused)] Are this and next one really needed?
0N/A// [C-aggregate-word (unused)] Yes, if want extra params to be in same place as C convention
0N/A// [16 words for register saving] <--- FP
0N/A// [interpreter_frame_vm_locals ] (see below)
0N/A
0N/A// Note: Llocals is always double-word aligned
0N/A// [first local i.e. local # 0] <-- Llocals
0N/A// ...
0N/A// [last local, i.e. local # Nlocals-1]
0N/A
0N/A// [monitors ]
0N/A// ....
0N/A// [monitors ] <-- Lmonitors (same as Llocals + 6*4 if none)
0N/A// (must be double-word aligned because
0N/A// monitor element size is constrained to
0N/A// doubleword)
0N/A//
0N/A// <-- Lesp (points 1 past TOS)
0N/A// [bottom word used for stack ]
0N/A// ...
0N/A// [top word used for stack] (first word of stack is double-word aligned)
0N/A
0N/A// [space for outgoing args (conservatively allocated as max_stack - 6 + interpreter_frame_extra_outgoing_argument_words)]
0N/A// [6 words for C-arg storage]
0N/A// [C-aggregate-word (unused)]
0N/A// [16 words for register saving] <--- SP
0N/A// ...
0N/A// 0x0000000
0N/A//
0N/A// The in registers and local registers are preserved in a block at SP.
0N/A//
0N/A// The first six in registers (I0..I5) hold the first six locals.
0N/A// The locals are used as follows:
0N/A// Lesp first free element of expression stack
0N/A// (which grows towards __higher__ addresses)
0N/A// Lbcp is set to address of bytecode to execute
0N/A// It is accessed in the frame under the name "bcx".
0N/A// It may at times (during GC) be an index instead.
0N/A// Lmethod the method being interpreted
0N/A// Llocals the base pointer for accessing the locals array
0N/A// (lower-numbered locals have lower addresses)
0N/A// Lmonitors the base pointer for accessing active monitors
0N/A// Lcache a saved pointer to the method's constant pool cache
0N/A//
0N/A//
0N/A// When calling out to another method,
0N/A// G5_method is set to method to call, G5_inline_cache_klass may be set,
0N/A// parameters are put in O registers, and also extra parameters
0N/A// must be cleverly copied from the top of stack to the outgoing param area in the frame,
0N/A// ------------------------------ C++ interpreter ----------------------------------------
0N/A// Layout of C++ interpreter frame:
0N/A//
0N/A
0N/A
0N/A
0N/A// All frames:
0N/A
0N/A public:
0N/A
0N/A enum {
0N/A // normal return address is 2 words past PC
0N/A pc_return_offset = 2 * BytesPerInstWord,
0N/A
0N/A // size of each block, in order of increasing address:
0N/A register_save_words = 16,
0N/A#ifdef _LP64
0N/A callee_aggregate_return_pointer_words = 0,
0N/A#else
0N/A callee_aggregate_return_pointer_words = 1,
0N/A#endif
0N/A callee_register_argument_save_area_words = 6,
0N/A // memory_parameter_words = <arbitrary>,
0N/A
0N/A // offset of each block, in order of increasing address:
0N/A // (note: callee_register_argument_save_area_words == Assembler::n_register_parameters)
0N/A register_save_words_sp_offset = 0,
0N/A callee_aggregate_return_pointer_sp_offset = register_save_words_sp_offset + register_save_words,
0N/A callee_register_argument_save_area_sp_offset = callee_aggregate_return_pointer_sp_offset + callee_aggregate_return_pointer_words,
0N/A memory_parameter_word_sp_offset = callee_register_argument_save_area_sp_offset + callee_register_argument_save_area_words,
0N/A varargs_offset = memory_parameter_word_sp_offset
0N/A };
0N/A
0N/A private:
0N/A intptr_t* _younger_sp; // optional SP of callee (used to locate O7)
0N/A int _sp_adjustment_by_callee; // adjustment in words to SP by callee for making locals contiguous
0N/A
0N/A // Note: On SPARC, unlike Intel, the saved PC for a stack frame
0N/A // is stored at a __variable__ distance from that frame's SP.
0N/A // (In fact, it may be in the register save area of the callee frame,
0N/A // but that fact need not bother us.) Thus, we must store the
0N/A // address of that saved PC explicitly. On the other hand, SPARC
0N/A // stores the FP for a frame at a fixed offset from the frame's SP,
0N/A // so there is no need for a separate "frame::_fp" field.
0N/A
0N/A public:
0N/A // Accessors
0N/A
0N/A intptr_t* younger_sp() const {
0N/A assert(_younger_sp != NULL, "frame must possess a younger_sp");
0N/A return _younger_sp;
0N/A }
0N/A
0N/A int callee_sp_adjustment() const { return _sp_adjustment_by_callee; }
0N/A void set_sp_adjustment_by_callee(int number_of_words) { _sp_adjustment_by_callee = number_of_words; }
0N/A
0N/A // Constructors
0N/A
0N/A // This constructor relies on the fact that the creator of a frame
0N/A // has flushed register windows which the frame will refer to, and
0N/A // that those register windows will not be reloaded until the frame is
0N/A // done reading and writing the stack. Moreover, if the "younger_sp"
0N/A // argument points into the register save area of the next younger
0N/A // frame (though it need not), the register window for that next
0N/A // younger frame must also stay flushed. (The caller is responsible
0N/A // for ensuring this.)
0N/A
0N/A frame(intptr_t* sp, intptr_t* younger_sp, bool younger_frame_adjusted_stack = false);
0N/A
0N/A // make a deficient frame which doesn't know where its PC is:
0N/A enum unpatchable_t { unpatchable };
0N/A frame(intptr_t* sp, unpatchable_t, address pc = NULL, CodeBlob* cb = NULL);
0N/A
0N/A // Walk from sp outward looking for old_sp, and return old_sp's predecessor
0N/A // (i.e. return the sp from the frame where old_sp is the fp).
0N/A // Register windows are assumed to be flushed for the stack in question.
0N/A
0N/A static intptr_t* next_younger_sp_or_null(intptr_t* old_sp, intptr_t* sp);
0N/A
0N/A // Return true if sp is a younger sp in the stack described by valid_sp.
0N/A static bool is_valid_stack_pointer(intptr_t* valid_sp, intptr_t* sp);
0N/A
0N/A public:
0N/A // accessors for the instance variables
0N/A intptr_t* fp() const { return (intptr_t*) ((intptr_t)(sp()[FP->sp_offset_in_saved_window()]) + STACK_BIAS ); }
0N/A
0N/A // All frames
0N/A
0N/A intptr_t* fp_addr_at(int index) const { return &fp()[index]; }
0N/A intptr_t* sp_addr_at(int index) const { return &sp()[index]; }
0N/A intptr_t fp_at( int index) const { return *fp_addr_at(index); }
0N/A intptr_t sp_at( int index) const { return *sp_addr_at(index); }
0N/A
0N/A private:
0N/A inline address* I7_addr() const;
0N/A inline address* O7_addr() const;
0N/A
0N/A inline address* I0_addr() const;
0N/A inline address* O0_addr() const;
0N/A intptr_t* younger_sp_addr_at(int index) const { return &younger_sp()[index]; }
0N/A
0N/A public:
0N/A // access to SPARC arguments and argument registers
0N/A
0N/A // Assumes reg is an in/local register
0N/A intptr_t* register_addr(Register reg) const {
0N/A return sp_addr_at(reg->sp_offset_in_saved_window());
0N/A }
0N/A
0N/A // Assumes reg is an out register
0N/A intptr_t* out_register_addr(Register reg) const {
0N/A return younger_sp_addr_at(reg->after_save()->sp_offset_in_saved_window());
0N/A }
0N/A intptr_t* memory_param_addr(int param_ix, bool is_in) const {
0N/A int offset = callee_register_argument_save_area_sp_offset + param_ix;
0N/A if (is_in)
0N/A return fp_addr_at(offset);
0N/A else
0N/A return sp_addr_at(offset);
0N/A }
0N/A intptr_t* param_addr(int param_ix, bool is_in) const {
0N/A if (param_ix >= callee_register_argument_save_area_words)
0N/A return memory_param_addr(param_ix, is_in);
0N/A else if (is_in)
0N/A return register_addr(Argument(param_ix, true).as_register());
0N/A else {
0N/A // the registers are stored in the next younger frame
0N/A // %%% is this really necessary?
0N/A ShouldNotReachHere();
0N/A return NULL;
0N/A }
0N/A }
0N/A
0N/A
0N/A // Interpreter frames
0N/A
0N/A public:
0N/A // Asm interpreter
0N/A#ifndef CC_INTERP
0N/A enum interpreter_frame_vm_locals {
0N/A // 2 words, also used to save float regs across calls to C
0N/A interpreter_frame_d_scratch_fp_offset = -2,
0N/A interpreter_frame_l_scratch_fp_offset = -4,
0N/A interpreter_frame_padding_offset = -5, // for native calls only
0N/A interpreter_frame_oop_temp_offset = -6, // for native calls only
0N/A interpreter_frame_vm_locals_fp_offset = -6, // should be same as above, and should be zero mod 8
0N/A
0N/A interpreter_frame_vm_local_words = -interpreter_frame_vm_locals_fp_offset,
0N/A
0N/A
0N/A // interpreter frame set-up needs to save 2 extra words in outgoing param area
0N/A // for class and jnienv arguments for native stubs (see nativeStubGen_sparc.cpp_
0N/A
0N/A interpreter_frame_extra_outgoing_argument_words = 2
0N/A };
0N/A#else
0N/A enum interpreter_frame_vm_locals {
0N/A // 2 words, also used to save float regs across calls to C
0N/A interpreter_state_ptr_offset = 0, // Is in L0 (Lstate) in save area
0N/A interpreter_frame_mirror_offset = 1, // Is in L1 (Lmirror) in save area (for native calls only)
0N/A
0N/A // interpreter frame set-up needs to save 2 extra words in outgoing param area
0N/A // for class and jnienv arguments for native stubs (see nativeStubGen_sparc.cpp_
0N/A
0N/A interpreter_frame_extra_outgoing_argument_words = 2
0N/A };
0N/A#endif /* CC_INTERP */
0N/A
0N/A enum compiler_frame_fixed_locals {
2733N/A compiler_frame_vm_locals_fp_offset = -2
0N/A };
0N/A
0N/A private:
1707N/A constantPoolCacheOop* interpreter_frame_cpoolcache_addr() const;
0N/A
0N/A#ifndef CC_INTERP
0N/A
0N/A // where Lmonitors is saved:
0N/A BasicObjectLock** interpreter_frame_monitors_addr() const {
0N/A return (BasicObjectLock**) sp_addr_at(Lmonitors->sp_offset_in_saved_window());
0N/A }
0N/A intptr_t** interpreter_frame_esp_addr() const {
0N/A return (intptr_t**)sp_addr_at(Lesp->sp_offset_in_saved_window());
0N/A }
0N/A
0N/A inline void interpreter_frame_set_tos_address(intptr_t* x);
0N/A
0N/A // monitors:
0N/A
0N/A // next two fns read and write Lmonitors value,
0N/A private:
0N/A BasicObjectLock* interpreter_frame_monitors() const { return *interpreter_frame_monitors_addr(); }
0N/A void interpreter_frame_set_monitors(BasicObjectLock* monitors) { *interpreter_frame_monitors_addr() = monitors; }
0N/A#else
0N/A public:
0N/A inline interpreterState get_interpreterState() const {
0N/A return ((interpreterState)sp_at(interpreter_state_ptr_offset));
0N/A }
0N/A
0N/A#endif /* CC_INTERP */
0N/A
0N/A public:
1879N/A
1879N/A#endif // CPU_SPARC_VM_FRAME_SPARC_HPP