c1_LIRAssembler_sparc.cpp revision 1060
0N/A/*
665N/A * Copyright 2000-2009 Sun Microsystems, Inc. All Rights Reserved.
0N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
0N/A *
0N/A * This code is free software; you can redistribute it and/or modify it
0N/A * under the terms of the GNU General Public License version 2 only, as
0N/A * published by the Free Software Foundation.
0N/A *
0N/A * This code is distributed in the hope that it will be useful, but WITHOUT
0N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
0N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
0N/A * version 2 for more details (a copy is included in the LICENSE file that
0N/A * accompanied this code).
0N/A *
0N/A * You should have received a copy of the GNU General Public License version
0N/A * 2 along with this work; if not, write to the Free Software Foundation,
0N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
0N/A *
0N/A * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
0N/A * CA 95054 USA or visit www.sun.com if you need additional information or
0N/A * have any questions.
0N/A *
0N/A */
0N/A
0N/A# include "incls/_precompiled.incl"
0N/A# include "incls/_c1_LIRAssembler_sparc.cpp.incl"
0N/A
0N/A#define __ _masm->
0N/A
0N/A
0N/A//------------------------------------------------------------
0N/A
0N/A
0N/Abool LIR_Assembler::is_small_constant(LIR_Opr opr) {
0N/A if (opr->is_constant()) {
0N/A LIR_Const* constant = opr->as_constant_ptr();
0N/A switch (constant->type()) {
0N/A case T_INT: {
0N/A jint value = constant->as_jint();
0N/A return Assembler::is_simm13(value);
0N/A }
0N/A
0N/A default:
0N/A return false;
0N/A }
0N/A }
0N/A return false;
0N/A}
0N/A
0N/A
0N/Abool LIR_Assembler::is_single_instruction(LIR_Op* op) {
0N/A switch (op->code()) {
0N/A case lir_null_check:
0N/A return true;
0N/A
0N/A
0N/A case lir_add:
0N/A case lir_ushr:
0N/A case lir_shr:
0N/A case lir_shl:
0N/A // integer shifts and adds are always one instruction
0N/A return op->result_opr()->is_single_cpu();
0N/A
0N/A
0N/A case lir_move: {
0N/A LIR_Op1* op1 = op->as_Op1();
0N/A LIR_Opr src = op1->in_opr();
0N/A LIR_Opr dst = op1->result_opr();
0N/A
0N/A if (src == dst) {
0N/A NEEDS_CLEANUP;
0N/A // this works around a problem where moves with the same src and dst
0N/A // end up in the delay slot and then the assembler swallows the mov
0N/A // since it has no effect and then it complains because the delay slot
0N/A // is empty. returning false stops the optimizer from putting this in
0N/A // the delay slot
0N/A return false;
0N/A }
0N/A
0N/A // don't put moves involving oops into the delay slot since the VerifyOops code
0N/A // will make it much larger than a single instruction.
0N/A if (VerifyOops) {
0N/A return false;
0N/A }
0N/A
0N/A if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none ||
0N/A ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) {
0N/A return false;
0N/A }
0N/A
0N/A if (dst->is_register()) {
0N/A if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) {
0N/A return !PatchALot;
0N/A } else if (src->is_single_stack()) {
0N/A return true;
0N/A }
0N/A }
0N/A
0N/A if (src->is_register()) {
0N/A if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) {
0N/A return !PatchALot;
0N/A } else if (dst->is_single_stack()) {
0N/A return true;
0N/A }
0N/A }
0N/A
0N/A if (dst->is_register() &&
0N/A ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) ||
0N/A (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) {
0N/A return true;
0N/A }
0N/A
0N/A return false;
0N/A }
0N/A
0N/A default:
0N/A return false;
0N/A }
0N/A ShouldNotReachHere();
0N/A}
0N/A
0N/A
0N/ALIR_Opr LIR_Assembler::receiverOpr() {
0N/A return FrameMap::O0_oop_opr;
0N/A}
0N/A
0N/A
0N/ALIR_Opr LIR_Assembler::incomingReceiverOpr() {
0N/A return FrameMap::I0_oop_opr;
0N/A}
0N/A
0N/A
0N/ALIR_Opr LIR_Assembler::osrBufferPointer() {
0N/A return FrameMap::I0_opr;
0N/A}
0N/A
0N/A
0N/Aint LIR_Assembler::initial_frame_size_in_bytes() {
0N/A return in_bytes(frame_map()->framesize_in_bytes());
0N/A}
0N/A
0N/A
0N/A// inline cache check: the inline cached class is in G5_inline_cache_reg(G5);
0N/A// we fetch the class of the receiver (O0) and compare it with the cached class.
0N/A// If they do not match we jump to slow case.
0N/Aint LIR_Assembler::check_icache() {
0N/A int offset = __ offset();
0N/A __ inline_cache_check(O0, G5_inline_cache_reg);
0N/A return offset;
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::osr_entry() {
0N/A // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
0N/A //
0N/A // 1. Create a new compiled activation.
0N/A // 2. Initialize local variables in the compiled activation. The expression stack must be empty
0N/A // at the osr_bci; it is not initialized.
0N/A // 3. Jump to the continuation address in compiled code to resume execution.
0N/A
0N/A // OSR entry point
0N/A offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
0N/A BlockBegin* osr_entry = compilation()->hir()->osr_entry();
0N/A ValueStack* entry_state = osr_entry->end()->state();
0N/A int number_of_locks = entry_state->locks_size();
0N/A
0N/A // Create a frame for the compiled activation.
0N/A __ build_frame(initial_frame_size_in_bytes());
0N/A
0N/A // OSR buffer is
0N/A //
0N/A // locals[nlocals-1..0]
0N/A // monitors[number_of_locks-1..0]
0N/A //
0N/A // locals is a direct copy of the interpreter frame so in the osr buffer
0N/A // so first slot in the local array is the last local from the interpreter
0N/A // and last slot is local[0] (receiver) from the interpreter
0N/A //
0N/A // Similarly with locks. The first lock slot in the osr buffer is the nth lock
0N/A // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
0N/A // in the interpreter frame (the method lock if a sync method)
0N/A
0N/A // Initialize monitors in the compiled activation.
0N/A // I0: pointer to osr buffer
0N/A //
0N/A // All other registers are dead at this point and the locals will be
0N/A // copied into place by code emitted in the IR.
0N/A
0N/A Register OSR_buf = osrBufferPointer()->as_register();
0N/A { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
0N/A int monitor_offset = BytesPerWord * method()->max_locals() +
1060N/A (2 * BytesPerWord) * (number_of_locks - 1);
1060N/A // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
1060N/A // the OSR buffer using 2 word entries: first the lock and then
1060N/A // the oop.
0N/A for (int i = 0; i < number_of_locks; i++) {
1060N/A int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
0N/A#ifdef ASSERT
0N/A // verify the interpreter's monitor has a non-null object
0N/A {
0N/A Label L;
1060N/A __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
0N/A __ cmp(G0, O7);
0N/A __ br(Assembler::notEqual, false, Assembler::pt, L);
0N/A __ delayed()->nop();
0N/A __ stop("locked object is NULL");
0N/A __ bind(L);
0N/A }
0N/A#endif // ASSERT
0N/A // Copy the lock field into the compiled activation.
1060N/A __ ld_ptr(OSR_buf, slot_offset + 0, O7);
0N/A __ st_ptr(O7, frame_map()->address_for_monitor_lock(i));
1060N/A __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7);
0N/A __ st_ptr(O7, frame_map()->address_for_monitor_object(i));
0N/A }
0N/A }
0N/A}
0N/A
0N/A
0N/A// Optimized Library calls
0N/A// This is the fast version of java.lang.String.compare; it has not
0N/A// OSR-entry and therefore, we generate a slow version for OSR's
0N/Avoid LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) {
0N/A Register str0 = left->as_register();
0N/A Register str1 = right->as_register();
0N/A
0N/A Label Ldone;
0N/A
0N/A Register result = dst->as_register();
0N/A {
0N/A // Get a pointer to the first character of string0 in tmp0 and get string0.count in str0
0N/A // Get a pointer to the first character of string1 in tmp1 and get string1.count in str1
0N/A // Also, get string0.count-string1.count in o7 and get the condition code set
0N/A // Note: some instructions have been hoisted for better instruction scheduling
0N/A
0N/A Register tmp0 = L0;
0N/A Register tmp1 = L1;
0N/A Register tmp2 = L2;
0N/A
0N/A int value_offset = java_lang_String:: value_offset_in_bytes(); // char array
0N/A int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position
0N/A int count_offset = java_lang_String:: count_offset_in_bytes();
0N/A
727N/A __ ld_ptr(str0, value_offset, tmp0);
727N/A __ ld(str0, offset_offset, tmp2);
0N/A __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0);
727N/A __ ld(str0, count_offset, str0);
0N/A __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
0N/A
0N/A // str1 may be null
0N/A add_debug_info_for_null_check_here(info);
0N/A
727N/A __ ld_ptr(str1, value_offset, tmp1);
0N/A __ add(tmp0, tmp2, tmp0);
0N/A
727N/A __ ld(str1, offset_offset, tmp2);
0N/A __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1);
727N/A __ ld(str1, count_offset, str1);
0N/A __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2);
0N/A __ subcc(str0, str1, O7);
0N/A __ add(tmp1, tmp2, tmp1);
0N/A }
0N/A
0N/A {
0N/A // Compute the minimum of the string lengths, scale it and store it in limit
0N/A Register count0 = I0;
0N/A Register count1 = I1;
0N/A Register limit = L3;
0N/A
0N/A Label Lskip;
0N/A __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter
0N/A __ br(Assembler::greater, true, Assembler::pt, Lskip);
0N/A __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter
0N/A __ bind(Lskip);
0N/A
0N/A // If either string is empty (or both of them) the result is the difference in lengths
0N/A __ cmp(limit, 0);
0N/A __ br(Assembler::equal, true, Assembler::pn, Ldone);
0N/A __ delayed()->mov(O7, result); // result is difference in lengths
0N/A }
0N/A
0N/A {
0N/A // Neither string is empty
0N/A Label Lloop;
0N/A
0N/A Register base0 = L0;
0N/A Register base1 = L1;
0N/A Register chr0 = I0;
0N/A Register chr1 = I1;
0N/A Register limit = L3;
0N/A
0N/A // Shift base0 and base1 to the end of the arrays, negate limit
0N/A __ add(base0, limit, base0);
0N/A __ add(base1, limit, base1);
0N/A __ neg(limit); // limit = -min{string0.count, strin1.count}
0N/A
0N/A __ lduh(base0, limit, chr0);
0N/A __ bind(Lloop);
0N/A __ lduh(base1, limit, chr1);
0N/A __ subcc(chr0, chr1, chr0);
0N/A __ br(Assembler::notZero, false, Assembler::pn, Ldone);
0N/A assert(chr0 == result, "result must be pre-placed");
0N/A __ delayed()->inccc(limit, sizeof(jchar));
0N/A __ br(Assembler::notZero, true, Assembler::pt, Lloop);
0N/A __ delayed()->lduh(base0, limit, chr0);
0N/A }
0N/A
0N/A // If strings are equal up to min length, return the length difference.
0N/A __ mov(O7, result);
0N/A
0N/A // Otherwise, return the difference between the first mismatched chars.
0N/A __ bind(Ldone);
0N/A}
0N/A
0N/A
0N/A// --------------------------------------------------------------------------------------------
0N/A
0N/Avoid LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) {
0N/A if (!GenerateSynchronizationCode) return;
0N/A
0N/A Register obj_reg = obj_opr->as_register();
0N/A Register lock_reg = lock_opr->as_register();
0N/A
0N/A Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
0N/A Register reg = mon_addr.base();
0N/A int offset = mon_addr.disp();
0N/A // compute pointer to BasicLock
0N/A if (mon_addr.is_simm13()) {
0N/A __ add(reg, offset, lock_reg);
0N/A }
0N/A else {
0N/A __ set(offset, lock_reg);
0N/A __ add(reg, lock_reg, lock_reg);
0N/A }
0N/A // unlock object
0N/A MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no);
0N/A // _slow_case_stubs->append(slow_case);
0N/A // temporary fix: must be created after exceptionhandler, therefore as call stub
0N/A _slow_case_stubs->append(slow_case);
0N/A if (UseFastLocking) {
0N/A // try inlined fast unlocking first, revert to slow locking if it fails
0N/A // note: lock_reg points to the displaced header since the displaced header offset is 0!
0N/A assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
0N/A __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry());
0N/A } else {
0N/A // always do slow unlocking
0N/A // note: the slow unlocking code could be inlined here, however if we use
0N/A // slow unlocking, speed doesn't matter anyway and this solution is
0N/A // simpler and requires less duplicated code - additionally, the
0N/A // slow unlocking code is the same in either case which simplifies
0N/A // debugging
0N/A __ br(Assembler::always, false, Assembler::pt, *slow_case->entry());
0N/A __ delayed()->nop();
0N/A }
0N/A // done
0N/A __ bind(*slow_case->continuation());
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::emit_exception_handler() {
0N/A // if the last instruction is a call (typically to do a throw which
0N/A // is coming at the end after block reordering) the return address
0N/A // must still point into the code area in order to avoid assertion
0N/A // failures when searching for the corresponding bci => add a nop
0N/A // (was bug 5/14/1999 - gri)
0N/A __ nop();
0N/A
0N/A // generate code for exception handler
0N/A ciMethod* method = compilation()->method();
0N/A
0N/A address handler_base = __ start_a_stub(exception_handler_size);
0N/A
0N/A if (handler_base == NULL) {
0N/A // not enough space left for the handler
0N/A bailout("exception handler overflow");
0N/A return;
0N/A }
0N/A#ifdef ASSERT
0N/A int offset = code_offset();
0N/A#endif // ASSERT
0N/A compilation()->offsets()->set_value(CodeOffsets::Exceptions, code_offset());
0N/A
0N/A
780N/A if (compilation()->has_exception_handlers() || compilation()->env()->jvmti_can_post_exceptions()) {
0N/A __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
0N/A __ delayed()->nop();
0N/A }
0N/A
0N/A __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
0N/A __ delayed()->nop();
0N/A debug_only(__ stop("should have gone to the caller");)
0N/A assert(code_offset() - offset <= exception_handler_size, "overflow");
0N/A
0N/A __ end_a_stub();
0N/A}
0N/A
0N/Avoid LIR_Assembler::emit_deopt_handler() {
0N/A // if the last instruction is a call (typically to do a throw which
0N/A // is coming at the end after block reordering) the return address
0N/A // must still point into the code area in order to avoid assertion
0N/A // failures when searching for the corresponding bci => add a nop
0N/A // (was bug 5/14/1999 - gri)
0N/A __ nop();
0N/A
0N/A // generate code for deopt handler
0N/A ciMethod* method = compilation()->method();
0N/A address handler_base = __ start_a_stub(deopt_handler_size);
0N/A if (handler_base == NULL) {
0N/A // not enough space left for the handler
0N/A bailout("deopt handler overflow");
0N/A return;
0N/A }
0N/A#ifdef ASSERT
0N/A int offset = code_offset();
0N/A#endif // ASSERT
0N/A compilation()->offsets()->set_value(CodeOffsets::Deopt, code_offset());
0N/A
727N/A AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
727N/A
727N/A __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp
0N/A __ delayed()->nop();
0N/A
0N/A assert(code_offset() - offset <= deopt_handler_size, "overflow");
0N/A
0N/A debug_only(__ stop("should have gone to the caller");)
0N/A
0N/A __ end_a_stub();
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::jobject2reg(jobject o, Register reg) {
0N/A if (o == NULL) {
0N/A __ set(NULL_WORD, reg);
0N/A } else {
0N/A int oop_index = __ oop_recorder()->find_index(o);
0N/A RelocationHolder rspec = oop_Relocation::spec(oop_index);
0N/A __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
0N/A // Allocate a new index in oop table to hold the oop once it's been patched
0N/A int oop_index = __ oop_recorder()->allocate_index((jobject)NULL);
0N/A PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, oop_index);
0N/A
727N/A AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index));
727N/A assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
0N/A // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the
0N/A // NULL will be dynamically patched later and the patched value may be large. We must
0N/A // therefore generate the sethi/add as a placeholders
727N/A __ patchable_set(addrlit, reg);
0N/A
0N/A patching_epilog(patch, lir_patch_normal, reg, info);
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::emit_op3(LIR_Op3* op) {
0N/A Register Rdividend = op->in_opr1()->as_register();
0N/A Register Rdivisor = noreg;
0N/A Register Rscratch = op->in_opr3()->as_register();
0N/A Register Rresult = op->result_opr()->as_register();
0N/A int divisor = -1;
0N/A
0N/A if (op->in_opr2()->is_register()) {
0N/A Rdivisor = op->in_opr2()->as_register();
0N/A } else {
0N/A divisor = op->in_opr2()->as_constant_ptr()->as_jint();
0N/A assert(Assembler::is_simm13(divisor), "can only handle simm13");
0N/A }
0N/A
0N/A assert(Rdividend != Rscratch, "");
0N/A assert(Rdivisor != Rscratch, "");
0N/A assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
0N/A
0N/A if (Rdivisor == noreg && is_power_of_2(divisor)) {
0N/A // convert division by a power of two into some shifts and logical operations
0N/A if (op->code() == lir_idiv) {
0N/A if (divisor == 2) {
0N/A __ srl(Rdividend, 31, Rscratch);
0N/A } else {
0N/A __ sra(Rdividend, 31, Rscratch);
0N/A __ and3(Rscratch, divisor - 1, Rscratch);
0N/A }
0N/A __ add(Rdividend, Rscratch, Rscratch);
0N/A __ sra(Rscratch, log2_intptr(divisor), Rresult);
0N/A return;
0N/A } else {
0N/A if (divisor == 2) {
0N/A __ srl(Rdividend, 31, Rscratch);
0N/A } else {
0N/A __ sra(Rdividend, 31, Rscratch);
0N/A __ and3(Rscratch, divisor - 1,Rscratch);
0N/A }
0N/A __ add(Rdividend, Rscratch, Rscratch);
0N/A __ andn(Rscratch, divisor - 1,Rscratch);
0N/A __ sub(Rdividend, Rscratch, Rresult);
0N/A return;
0N/A }
0N/A }
0N/A
0N/A __ sra(Rdividend, 31, Rscratch);
0N/A __ wry(Rscratch);
0N/A if (!VM_Version::v9_instructions_work()) {
0N/A // v9 doesn't require these nops
0N/A __ nop();
0N/A __ nop();
0N/A __ nop();
0N/A __ nop();
0N/A }
0N/A
0N/A add_debug_info_for_div0_here(op->info());
0N/A
0N/A if (Rdivisor != noreg) {
0N/A __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch));
0N/A } else {
0N/A assert(Assembler::is_simm13(divisor), "can only handle simm13");
0N/A __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch));
0N/A }
0N/A
0N/A Label skip;
0N/A __ br(Assembler::overflowSet, true, Assembler::pn, skip);
0N/A __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch));
0N/A __ bind(skip);
0N/A
0N/A if (op->code() == lir_irem) {
0N/A if (Rdivisor != noreg) {
0N/A __ smul(Rscratch, Rdivisor, Rscratch);
0N/A } else {
0N/A __ smul(Rscratch, divisor, Rscratch);
0N/A }
0N/A __ sub(Rdividend, Rscratch, Rresult);
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
0N/A#ifdef ASSERT
0N/A assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
0N/A if (op->block() != NULL) _branch_target_blocks.append(op->block());
0N/A if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
0N/A#endif
0N/A assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
0N/A
0N/A if (op->cond() == lir_cond_always) {
0N/A __ br(Assembler::always, false, Assembler::pt, *(op->label()));
0N/A } else if (op->code() == lir_cond_float_branch) {
0N/A assert(op->ublock() != NULL, "must have unordered successor");
0N/A bool is_unordered = (op->ublock() == op->block());
0N/A Assembler::Condition acond;
0N/A switch (op->cond()) {
0N/A case lir_cond_equal: acond = Assembler::f_equal; break;
0N/A case lir_cond_notEqual: acond = Assembler::f_notEqual; break;
0N/A case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break;
0N/A case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break;
0N/A case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break;
0N/A case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break;
0N/A default : ShouldNotReachHere();
0N/A };
0N/A
0N/A if (!VM_Version::v9_instructions_work()) {
0N/A __ nop();
0N/A }
0N/A __ fb( acond, false, Assembler::pn, *(op->label()));
0N/A } else {
0N/A assert (op->code() == lir_branch, "just checking");
0N/A
0N/A Assembler::Condition acond;
0N/A switch (op->cond()) {
0N/A case lir_cond_equal: acond = Assembler::equal; break;
0N/A case lir_cond_notEqual: acond = Assembler::notEqual; break;
0N/A case lir_cond_less: acond = Assembler::less; break;
0N/A case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
0N/A case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
0N/A case lir_cond_greater: acond = Assembler::greater; break;
0N/A case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
0N/A case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
0N/A default: ShouldNotReachHere();
0N/A };
0N/A
0N/A // sparc has different condition codes for testing 32-bit
0N/A // vs. 64-bit values. We could always test xcc is we could
0N/A // guarantee that 32-bit loads always sign extended but that isn't
0N/A // true and since sign extension isn't free, it would impose a
0N/A // slight cost.
0N/A#ifdef _LP64
0N/A if (op->type() == T_INT) {
0N/A __ br(acond, false, Assembler::pn, *(op->label()));
0N/A } else
0N/A#endif
0N/A __ brx(acond, false, Assembler::pn, *(op->label()));
0N/A }
0N/A // The peephole pass fills the delay slot
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
0N/A Bytecodes::Code code = op->bytecode();
0N/A LIR_Opr dst = op->result_opr();
0N/A
0N/A switch(code) {
0N/A case Bytecodes::_i2l: {
0N/A Register rlo = dst->as_register_lo();
0N/A Register rhi = dst->as_register_hi();
0N/A Register rval = op->in_opr()->as_register();
0N/A#ifdef _LP64
0N/A __ sra(rval, 0, rlo);
0N/A#else
0N/A __ mov(rval, rlo);
0N/A __ sra(rval, BitsPerInt-1, rhi);
0N/A#endif
0N/A break;
0N/A }
0N/A case Bytecodes::_i2d:
0N/A case Bytecodes::_i2f: {
0N/A bool is_double = (code == Bytecodes::_i2d);
0N/A FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
0N/A FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
0N/A FloatRegister rsrc = op->in_opr()->as_float_reg();
0N/A if (rsrc != rdst) {
0N/A __ fmov(FloatRegisterImpl::S, rsrc, rdst);
0N/A }
0N/A __ fitof(w, rdst, rdst);
0N/A break;
0N/A }
0N/A case Bytecodes::_f2i:{
0N/A FloatRegister rsrc = op->in_opr()->as_float_reg();
0N/A Address addr = frame_map()->address_for_slot(dst->single_stack_ix());
0N/A Label L;
0N/A // result must be 0 if value is NaN; test by comparing value to itself
0N/A __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc);
0N/A if (!VM_Version::v9_instructions_work()) {
0N/A __ nop();
0N/A }
0N/A __ fb(Assembler::f_unordered, true, Assembler::pn, L);
0N/A __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN
0N/A __ ftoi(FloatRegisterImpl::S, rsrc, rsrc);
0N/A // move integer result from float register to int register
0N/A __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp());
0N/A __ bind (L);
0N/A break;
0N/A }
0N/A case Bytecodes::_l2i: {
0N/A Register rlo = op->in_opr()->as_register_lo();
0N/A Register rhi = op->in_opr()->as_register_hi();
0N/A Register rdst = dst->as_register();
0N/A#ifdef _LP64
0N/A __ sra(rlo, 0, rdst);
0N/A#else
0N/A __ mov(rlo, rdst);
0N/A#endif
0N/A break;
0N/A }
0N/A case Bytecodes::_d2f:
0N/A case Bytecodes::_f2d: {
0N/A bool is_double = (code == Bytecodes::_f2d);
0N/A assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check");
0N/A LIR_Opr val = op->in_opr();
0N/A FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg();
0N/A FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg();
0N/A FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D;
0N/A FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S;
0N/A __ ftof(vw, dw, rval, rdst);
0N/A break;
0N/A }
0N/A case Bytecodes::_i2s:
0N/A case Bytecodes::_i2b: {
0N/A Register rval = op->in_opr()->as_register();
0N/A Register rdst = dst->as_register();
0N/A int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort);
0N/A __ sll (rval, shift, rdst);
0N/A __ sra (rdst, shift, rdst);
0N/A break;
0N/A }
0N/A case Bytecodes::_i2c: {
0N/A Register rval = op->in_opr()->as_register();
0N/A Register rdst = dst->as_register();
0N/A int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte;
0N/A __ sll (rval, shift, rdst);
0N/A __ srl (rdst, shift, rdst);
0N/A break;
0N/A }
0N/A
0N/A default: ShouldNotReachHere();
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::align_call(LIR_Code) {
0N/A // do nothing since all instructions are word aligned on sparc
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::call(address entry, relocInfo::relocType rtype, CodeEmitInfo* info) {
0N/A __ call(entry, rtype);
0N/A // the peephole pass fills the delay slot
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::ic_call(address entry, CodeEmitInfo* info) {
0N/A RelocationHolder rspec = virtual_call_Relocation::spec(pc());
0N/A __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg);
0N/A __ relocate(rspec);
0N/A __ call(entry, relocInfo::none);
0N/A // the peephole pass fills the delay slot
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::vtable_call(int vtable_offset, CodeEmitInfo* info) {
0N/A add_debug_info_for_null_check_here(info);
727N/A __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch);
0N/A if (__ is_simm13(vtable_offset) ) {
0N/A __ ld_ptr(G3_scratch, vtable_offset, G5_method);
0N/A } else {
0N/A // This will generate 2 instructions
0N/A __ set(vtable_offset, G5_method);
0N/A // ld_ptr, set_hi, set
0N/A __ ld_ptr(G3_scratch, G5_method, G5_method);
0N/A }
727N/A __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch);
0N/A __ callr(G3_scratch, G0);
0N/A // the peephole pass fills the delay slot
0N/A}
0N/A
0N/A
0N/A// load with 32-bit displacement
0N/Aint LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) {
0N/A int load_offset = code_offset();
0N/A if (Assembler::is_simm13(disp)) {
0N/A if (info != NULL) add_debug_info_for_null_check_here(info);
0N/A switch(ld_type) {
0N/A case T_BOOLEAN: // fall through
0N/A case T_BYTE : __ ldsb(s, disp, d); break;
0N/A case T_CHAR : __ lduh(s, disp, d); break;
0N/A case T_SHORT : __ ldsh(s, disp, d); break;
0N/A case T_INT : __ ld(s, disp, d); break;
0N/A case T_ADDRESS:// fall through
0N/A case T_ARRAY : // fall through
0N/A case T_OBJECT: __ ld_ptr(s, disp, d); break;
0N/A default : ShouldNotReachHere();
0N/A }
0N/A } else {
727N/A __ set(disp, O7);
0N/A if (info != NULL) add_debug_info_for_null_check_here(info);
0N/A load_offset = code_offset();
0N/A switch(ld_type) {
0N/A case T_BOOLEAN: // fall through
0N/A case T_BYTE : __ ldsb(s, O7, d); break;
0N/A case T_CHAR : __ lduh(s, O7, d); break;
0N/A case T_SHORT : __ ldsh(s, O7, d); break;
0N/A case T_INT : __ ld(s, O7, d); break;
0N/A case T_ADDRESS:// fall through
0N/A case T_ARRAY : // fall through
0N/A case T_OBJECT: __ ld_ptr(s, O7, d); break;
0N/A default : ShouldNotReachHere();
0N/A }
0N/A }
0N/A if (ld_type == T_ARRAY || ld_type == T_OBJECT) __ verify_oop(d);
0N/A return load_offset;
0N/A}
0N/A
0N/A
0N/A// store with 32-bit displacement
0N/Avoid LIR_Assembler::store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
0N/A if (Assembler::is_simm13(offset)) {
0N/A if (info != NULL) add_debug_info_for_null_check_here(info);
0N/A switch (type) {
0N/A case T_BOOLEAN: // fall through
0N/A case T_BYTE : __ stb(value, base, offset); break;
0N/A case T_CHAR : __ sth(value, base, offset); break;
0N/A case T_SHORT : __ sth(value, base, offset); break;
0N/A case T_INT : __ stw(value, base, offset); break;
0N/A case T_ADDRESS:// fall through
0N/A case T_ARRAY : // fall through
0N/A case T_OBJECT: __ st_ptr(value, base, offset); break;
0N/A default : ShouldNotReachHere();
0N/A }
0N/A } else {
727N/A __ set(offset, O7);
0N/A if (info != NULL) add_debug_info_for_null_check_here(info);
0N/A switch (type) {
0N/A case T_BOOLEAN: // fall through
0N/A case T_BYTE : __ stb(value, base, O7); break;
0N/A case T_CHAR : __ sth(value, base, O7); break;
0N/A case T_SHORT : __ sth(value, base, O7); break;
0N/A case T_INT : __ stw(value, base, O7); break;
0N/A case T_ADDRESS:// fall through
0N/A case T_ARRAY : //fall through
0N/A case T_OBJECT: __ st_ptr(value, base, O7); break;
0N/A default : ShouldNotReachHere();
0N/A }
0N/A }
0N/A // Note: Do the store before verification as the code might be patched!
0N/A if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(value);
0N/A}
0N/A
0N/A
0N/A// load float with 32-bit displacement
0N/Avoid LIR_Assembler::load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
0N/A FloatRegisterImpl::Width w;
0N/A switch(ld_type) {
0N/A case T_FLOAT : w = FloatRegisterImpl::S; break;
0N/A case T_DOUBLE: w = FloatRegisterImpl::D; break;
0N/A default : ShouldNotReachHere();
0N/A }
0N/A
0N/A if (Assembler::is_simm13(disp)) {
0N/A if (info != NULL) add_debug_info_for_null_check_here(info);
0N/A if (disp % BytesPerLong != 0 && w == FloatRegisterImpl::D) {
0N/A __ ldf(FloatRegisterImpl::S, s, disp + BytesPerWord, d->successor());
0N/A __ ldf(FloatRegisterImpl::S, s, disp , d);
0N/A } else {
0N/A __ ldf(w, s, disp, d);
0N/A }
0N/A } else {
727N/A __ set(disp, O7);
0N/A if (info != NULL) add_debug_info_for_null_check_here(info);
0N/A __ ldf(w, s, O7, d);
0N/A }
0N/A}
0N/A
0N/A
0N/A// store float with 32-bit displacement
0N/Avoid LIR_Assembler::store(FloatRegister value, Register base, int offset, BasicType type, CodeEmitInfo *info) {
0N/A FloatRegisterImpl::Width w;
0N/A switch(type) {
0N/A case T_FLOAT : w = FloatRegisterImpl::S; break;
0N/A case T_DOUBLE: w = FloatRegisterImpl::D; break;
0N/A default : ShouldNotReachHere();
0N/A }
0N/A
0N/A if (Assembler::is_simm13(offset)) {
0N/A if (info != NULL) add_debug_info_for_null_check_here(info);
0N/A if (w == FloatRegisterImpl::D && offset % BytesPerLong != 0) {
0N/A __ stf(FloatRegisterImpl::S, value->successor(), base, offset + BytesPerWord);
0N/A __ stf(FloatRegisterImpl::S, value , base, offset);
0N/A } else {
0N/A __ stf(w, value, base, offset);
0N/A }
0N/A } else {
727N/A __ set(offset, O7);
0N/A if (info != NULL) add_debug_info_for_null_check_here(info);
0N/A __ stf(w, value, O7, base);
0N/A }
0N/A}
0N/A
0N/A
0N/Aint LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned) {
0N/A int store_offset;
0N/A if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
0N/A assert(!unaligned, "can't handle this");
0N/A // for offsets larger than a simm13 we setup the offset in O7
727N/A __ set(offset, O7);
0N/A store_offset = store(from_reg, base, O7, type);
0N/A } else {
0N/A if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
0N/A store_offset = code_offset();
0N/A switch (type) {
0N/A case T_BOOLEAN: // fall through
0N/A case T_BYTE : __ stb(from_reg->as_register(), base, offset); break;
0N/A case T_CHAR : __ sth(from_reg->as_register(), base, offset); break;
0N/A case T_SHORT : __ sth(from_reg->as_register(), base, offset); break;
0N/A case T_INT : __ stw(from_reg->as_register(), base, offset); break;
0N/A case T_LONG :
0N/A#ifdef _LP64
0N/A if (unaligned || PatchALot) {
0N/A __ srax(from_reg->as_register_lo(), 32, O7);
0N/A __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
0N/A __ stw(O7, base, offset + hi_word_offset_in_bytes);
0N/A } else {
0N/A __ stx(from_reg->as_register_lo(), base, offset);
0N/A }
0N/A#else
0N/A assert(Assembler::is_simm13(offset + 4), "must be");
0N/A __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes);
0N/A __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes);
0N/A#endif
0N/A break;
0N/A case T_ADDRESS:// fall through
0N/A case T_ARRAY : // fall through
0N/A case T_OBJECT: __ st_ptr(from_reg->as_register(), base, offset); break;
0N/A case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break;
0N/A case T_DOUBLE:
0N/A {
0N/A FloatRegister reg = from_reg->as_double_reg();
0N/A // split unaligned stores
0N/A if (unaligned || PatchALot) {
0N/A assert(Assembler::is_simm13(offset + 4), "must be");
0N/A __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4);
0N/A __ stf(FloatRegisterImpl::S, reg, base, offset);
0N/A } else {
0N/A __ stf(FloatRegisterImpl::D, reg, base, offset);
0N/A }
0N/A break;
0N/A }
0N/A default : ShouldNotReachHere();
0N/A }
0N/A }
0N/A return store_offset;
0N/A}
0N/A
0N/A
0N/Aint LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type) {
0N/A if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register());
0N/A int store_offset = code_offset();
0N/A switch (type) {
0N/A case T_BOOLEAN: // fall through
0N/A case T_BYTE : __ stb(from_reg->as_register(), base, disp); break;
0N/A case T_CHAR : __ sth(from_reg->as_register(), base, disp); break;
0N/A case T_SHORT : __ sth(from_reg->as_register(), base, disp); break;
0N/A case T_INT : __ stw(from_reg->as_register(), base, disp); break;
0N/A case T_LONG :
0N/A#ifdef _LP64
0N/A __ stx(from_reg->as_register_lo(), base, disp);
0N/A#else
0N/A assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match");
0N/A __ std(from_reg->as_register_hi(), base, disp);
0N/A#endif
0N/A break;
0N/A case T_ADDRESS:// fall through
0N/A case T_ARRAY : // fall through
0N/A case T_OBJECT: __ st_ptr(from_reg->as_register(), base, disp); break;
0N/A case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break;
0N/A case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break;
0N/A default : ShouldNotReachHere();
0N/A }
0N/A return store_offset;
0N/A}
0N/A
0N/A
0N/Aint LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned) {
0N/A int load_offset;
0N/A if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) {
0N/A assert(base != O7, "destroying register");
0N/A assert(!unaligned, "can't handle this");
0N/A // for offsets larger than a simm13 we setup the offset in O7
727N/A __ set(offset, O7);
0N/A load_offset = load(base, O7, to_reg, type);
0N/A } else {
0N/A load_offset = code_offset();
0N/A switch(type) {
0N/A case T_BOOLEAN: // fall through
0N/A case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break;
0N/A case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break;
0N/A case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break;
0N/A case T_INT : __ ld(base, offset, to_reg->as_register()); break;
0N/A case T_LONG :
0N/A if (!unaligned) {
0N/A#ifdef _LP64
0N/A __ ldx(base, offset, to_reg->as_register_lo());
0N/A#else
0N/A assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
0N/A "must be sequential");
0N/A __ ldd(base, offset, to_reg->as_register_hi());
0N/A#endif
0N/A } else {
0N/A#ifdef _LP64
0N/A assert(base != to_reg->as_register_lo(), "can't handle this");
1060N/A assert(O7 != to_reg->as_register_lo(), "can't handle this");
0N/A __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo());
1060N/A __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last
0N/A __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo());
1060N/A __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo());
0N/A#else
0N/A if (base == to_reg->as_register_lo()) {
0N/A __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
0N/A __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
0N/A } else {
0N/A __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo());
0N/A __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi());
0N/A }
0N/A#endif
0N/A }
0N/A break;
0N/A case T_ADDRESS:// fall through
0N/A case T_ARRAY : // fall through
0N/A case T_OBJECT: __ ld_ptr(base, offset, to_reg->as_register()); break;
0N/A case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break;
0N/A case T_DOUBLE:
0N/A {
0N/A FloatRegister reg = to_reg->as_double_reg();
0N/A // split unaligned loads
0N/A if (unaligned || PatchALot) {
1060N/A __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor());
1060N/A __ ldf(FloatRegisterImpl::S, base, offset, reg);
0N/A } else {
0N/A __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg());
0N/A }
0N/A break;
0N/A }
0N/A default : ShouldNotReachHere();
0N/A }
0N/A if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
0N/A }
0N/A return load_offset;
0N/A}
0N/A
0N/A
0N/Aint LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type) {
0N/A int load_offset = code_offset();
0N/A switch(type) {
0N/A case T_BOOLEAN: // fall through
0N/A case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break;
0N/A case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break;
0N/A case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break;
0N/A case T_INT : __ ld(base, disp, to_reg->as_register()); break;
0N/A case T_ADDRESS:// fall through
0N/A case T_ARRAY : // fall through
0N/A case T_OBJECT: __ ld_ptr(base, disp, to_reg->as_register()); break;
0N/A case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break;
0N/A case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break;
0N/A case T_LONG :
0N/A#ifdef _LP64
0N/A __ ldx(base, disp, to_reg->as_register_lo());
0N/A#else
0N/A assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(),
0N/A "must be sequential");
0N/A __ ldd(base, disp, to_reg->as_register_hi());
0N/A#endif
0N/A break;
0N/A default : ShouldNotReachHere();
0N/A }
0N/A if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register());
0N/A return load_offset;
0N/A}
0N/A
0N/A
0N/A// load/store with an Address
0N/Avoid LIR_Assembler::load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo *info, int offset) {
0N/A load(a.base(), a.disp() + offset, d, ld_type, info);
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::store(Register value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
0N/A store(value, dest.base(), dest.disp() + offset, type, info);
0N/A}
0N/A
0N/A
0N/A// loadf/storef with an Address
0N/Avoid LIR_Assembler::load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info, int offset) {
0N/A load(a.base(), a.disp() + offset, d, ld_type, info);
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::store(FloatRegister value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) {
0N/A store(value, dest.base(), dest.disp() + offset, type, info);
0N/A}
0N/A
0N/A
0N/A// load/store with an Address
0N/Avoid LIR_Assembler::load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo *info) {
0N/A load(as_Address(a), d, ld_type, info);
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::store(Register value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
0N/A store(value, as_Address(dest), type, info);
0N/A}
0N/A
0N/A
0N/A// loadf/storef with an Address
0N/Avoid LIR_Assembler::load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) {
0N/A load(as_Address(a), d, ld_type, info);
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::store(FloatRegister value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) {
0N/A store(value, as_Address(dest), type, info);
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
0N/A LIR_Const* c = src->as_constant_ptr();
0N/A switch (c->type()) {
0N/A case T_INT:
0N/A case T_FLOAT: {
0N/A Register src_reg = O7;
0N/A int value = c->as_jint_bits();
0N/A if (value == 0) {
0N/A src_reg = G0;
0N/A } else {
0N/A __ set(value, O7);
0N/A }
0N/A Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
0N/A __ stw(src_reg, addr.base(), addr.disp());
0N/A break;
0N/A }
0N/A case T_OBJECT: {
0N/A Register src_reg = O7;
0N/A jobject2reg(c->as_jobject(), src_reg);
0N/A Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
0N/A __ st_ptr(src_reg, addr.base(), addr.disp());
0N/A break;
0N/A }
0N/A case T_LONG:
0N/A case T_DOUBLE: {
0N/A Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
0N/A
0N/A Register tmp = O7;
0N/A int value_lo = c->as_jint_lo_bits();
0N/A if (value_lo == 0) {
0N/A tmp = G0;
0N/A } else {
0N/A __ set(value_lo, O7);
0N/A }
0N/A __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes);
0N/A int value_hi = c->as_jint_hi_bits();
0N/A if (value_hi == 0) {
0N/A tmp = G0;
0N/A } else {
0N/A __ set(value_hi, O7);
0N/A }
0N/A __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes);
0N/A break;
0N/A }
0N/A default:
0N/A Unimplemented();
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) {
0N/A LIR_Const* c = src->as_constant_ptr();
0N/A LIR_Address* addr = dest->as_address_ptr();
0N/A Register base = addr->base()->as_pointer_register();
0N/A
0N/A if (info != NULL) {
0N/A add_debug_info_for_null_check_here(info);
0N/A }
0N/A switch (c->type()) {
0N/A case T_INT:
0N/A case T_FLOAT: {
0N/A LIR_Opr tmp = FrameMap::O7_opr;
0N/A int value = c->as_jint_bits();
0N/A if (value == 0) {
0N/A tmp = FrameMap::G0_opr;
0N/A } else if (Assembler::is_simm13(value)) {
0N/A __ set(value, O7);
0N/A }
0N/A if (addr->index()->is_valid()) {
0N/A assert(addr->disp() == 0, "must be zero");
0N/A store(tmp, base, addr->index()->as_pointer_register(), type);
0N/A } else {
0N/A assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
0N/A store(tmp, base, addr->disp(), type);
0N/A }
0N/A break;
0N/A }
0N/A case T_LONG:
0N/A case T_DOUBLE: {
0N/A assert(!addr->index()->is_valid(), "can't handle reg reg address here");
0N/A assert(Assembler::is_simm13(addr->disp()) &&
0N/A Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses");
0N/A
0N/A Register tmp = O7;
0N/A int value_lo = c->as_jint_lo_bits();
0N/A if (value_lo == 0) {
0N/A tmp = G0;
0N/A } else {
0N/A __ set(value_lo, O7);
0N/A }
0N/A store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT);
0N/A int value_hi = c->as_jint_hi_bits();
0N/A if (value_hi == 0) {
0N/A tmp = G0;
0N/A } else {
0N/A __ set(value_hi, O7);
0N/A }
0N/A store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT);
0N/A break;
0N/A }
0N/A case T_OBJECT: {
0N/A jobject obj = c->as_jobject();
0N/A LIR_Opr tmp;
0N/A if (obj == NULL) {
0N/A tmp = FrameMap::G0_opr;
0N/A } else {
0N/A tmp = FrameMap::O7_opr;
0N/A jobject2reg(c->as_jobject(), O7);
0N/A }
0N/A // handle either reg+reg or reg+disp address
0N/A if (addr->index()->is_valid()) {
0N/A assert(addr->disp() == 0, "must be zero");
0N/A store(tmp, base, addr->index()->as_pointer_register(), type);
0N/A } else {
0N/A assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses");
0N/A store(tmp, base, addr->disp(), type);
0N/A }
0N/A
0N/A break;
0N/A }
0N/A default:
0N/A Unimplemented();
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
0N/A LIR_Const* c = src->as_constant_ptr();
0N/A LIR_Opr to_reg = dest;
0N/A
0N/A switch (c->type()) {
0N/A case T_INT:
0N/A {
0N/A jint con = c->as_jint();
0N/A if (to_reg->is_single_cpu()) {
0N/A assert(patch_code == lir_patch_none, "no patching handled here");
0N/A __ set(con, to_reg->as_register());
0N/A } else {
0N/A ShouldNotReachHere();
0N/A assert(to_reg->is_single_fpu(), "wrong register kind");
0N/A
0N/A __ set(con, O7);
727N/A Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS);
0N/A __ st(O7, temp_slot);
0N/A __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg());
0N/A }
0N/A }
0N/A break;
0N/A
0N/A case T_LONG:
0N/A {
0N/A jlong con = c->as_jlong();
0N/A
0N/A if (to_reg->is_double_cpu()) {
0N/A#ifdef _LP64
0N/A __ set(con, to_reg->as_register_lo());
0N/A#else
0N/A __ set(low(con), to_reg->as_register_lo());
0N/A __ set(high(con), to_reg->as_register_hi());
0N/A#endif
0N/A#ifdef _LP64
0N/A } else if (to_reg->is_single_cpu()) {
0N/A __ set(con, to_reg->as_register());
0N/A#endif
0N/A } else {
0N/A ShouldNotReachHere();
0N/A assert(to_reg->is_double_fpu(), "wrong register kind");
727N/A Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS);
727N/A Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS);
0N/A __ set(low(con), O7);
0N/A __ st(O7, temp_slot_lo);
0N/A __ set(high(con), O7);
0N/A __ st(O7, temp_slot_hi);
0N/A __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg());
0N/A }
0N/A }
0N/A break;
0N/A
0N/A case T_OBJECT:
0N/A {
0N/A if (patch_code == lir_patch_none) {
0N/A jobject2reg(c->as_jobject(), to_reg->as_register());
0N/A } else {
0N/A jobject2reg_with_patching(to_reg->as_register(), info);
0N/A }
0N/A }
0N/A break;
0N/A
0N/A case T_FLOAT:
0N/A {
0N/A address const_addr = __ float_constant(c->as_jfloat());
0N/A if (const_addr == NULL) {
0N/A bailout("const section overflow");
0N/A break;
0N/A }
0N/A RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
727N/A AddressLiteral const_addrlit(const_addr, rspec);
0N/A if (to_reg->is_single_fpu()) {
727N/A __ patchable_sethi(const_addrlit, O7);
0N/A __ relocate(rspec);
727N/A __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg());
0N/A
0N/A } else {
0N/A assert(to_reg->is_single_cpu(), "Must be a cpu register.");
0N/A
727N/A __ set(const_addrlit, O7);
0N/A load(O7, 0, to_reg->as_register(), T_INT);
0N/A }
0N/A }
0N/A break;
0N/A
0N/A case T_DOUBLE:
0N/A {
0N/A address const_addr = __ double_constant(c->as_jdouble());
0N/A if (const_addr == NULL) {
0N/A bailout("const section overflow");
0N/A break;
0N/A }
0N/A RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
0N/A
0N/A if (to_reg->is_double_fpu()) {
727N/A AddressLiteral const_addrlit(const_addr, rspec);
727N/A __ patchable_sethi(const_addrlit, O7);
0N/A __ relocate(rspec);
727N/A __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg());
0N/A } else {
0N/A assert(to_reg->is_double_cpu(), "Must be a long register.");
0N/A#ifdef _LP64
0N/A __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo());
0N/A#else
0N/A __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo());
0N/A __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi());
0N/A#endif
0N/A }
0N/A
0N/A }
0N/A break;
0N/A
0N/A default:
0N/A ShouldNotReachHere();
0N/A }
0N/A}
0N/A
0N/AAddress LIR_Assembler::as_Address(LIR_Address* addr) {
0N/A Register reg = addr->base()->as_register();
727N/A return Address(reg, addr->disp());
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
0N/A switch (type) {
0N/A case T_INT:
0N/A case T_FLOAT: {
0N/A Register tmp = O7;
0N/A Address from = frame_map()->address_for_slot(src->single_stack_ix());
0N/A Address to = frame_map()->address_for_slot(dest->single_stack_ix());
0N/A __ lduw(from.base(), from.disp(), tmp);
0N/A __ stw(tmp, to.base(), to.disp());
0N/A break;
0N/A }
0N/A case T_OBJECT: {
0N/A Register tmp = O7;
0N/A Address from = frame_map()->address_for_slot(src->single_stack_ix());
0N/A Address to = frame_map()->address_for_slot(dest->single_stack_ix());
0N/A __ ld_ptr(from.base(), from.disp(), tmp);
0N/A __ st_ptr(tmp, to.base(), to.disp());
0N/A break;
0N/A }
0N/A case T_LONG:
0N/A case T_DOUBLE: {
0N/A Register tmp = O7;
0N/A Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
0N/A Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
0N/A __ lduw(from.base(), from.disp(), tmp);
0N/A __ stw(tmp, to.base(), to.disp());
0N/A __ lduw(from.base(), from.disp() + 4, tmp);
0N/A __ stw(tmp, to.base(), to.disp() + 4);
0N/A break;
0N/A }
0N/A
0N/A default:
0N/A ShouldNotReachHere();
0N/A }
0N/A}
0N/A
0N/A
0N/AAddress LIR_Assembler::as_Address_hi(LIR_Address* addr) {
0N/A Address base = as_Address(addr);
727N/A return Address(base.base(), base.disp() + hi_word_offset_in_bytes);
0N/A}
0N/A
0N/A
0N/AAddress LIR_Assembler::as_Address_lo(LIR_Address* addr) {
0N/A Address base = as_Address(addr);
727N/A return Address(base.base(), base.disp() + lo_word_offset_in_bytes);
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
0N/A LIR_PatchCode patch_code, CodeEmitInfo* info, bool unaligned) {
0N/A
0N/A LIR_Address* addr = src_opr->as_address_ptr();
0N/A LIR_Opr to_reg = dest;
0N/A
0N/A Register src = addr->base()->as_pointer_register();
0N/A Register disp_reg = noreg;
0N/A int disp_value = addr->disp();
0N/A bool needs_patching = (patch_code != lir_patch_none);
0N/A
0N/A if (addr->base()->type() == T_OBJECT) {
0N/A __ verify_oop(src);
0N/A }
0N/A
0N/A PatchingStub* patch = NULL;
0N/A if (needs_patching) {
0N/A patch = new PatchingStub(_masm, PatchingStub::access_field_id);
0N/A assert(!to_reg->is_double_cpu() ||
0N/A patch_code == lir_patch_none ||
0N/A patch_code == lir_patch_normal, "patching doesn't match register");
0N/A }
0N/A
0N/A if (addr->index()->is_illegal()) {
0N/A if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
0N/A if (needs_patching) {
727N/A __ patchable_set(0, O7);
0N/A } else {
0N/A __ set(disp_value, O7);
0N/A }
0N/A disp_reg = O7;
0N/A }
0N/A } else if (unaligned || PatchALot) {
0N/A __ add(src, addr->index()->as_register(), O7);
0N/A src = O7;
0N/A } else {
0N/A disp_reg = addr->index()->as_pointer_register();
0N/A assert(disp_value == 0, "can't handle 3 operand addresses");
0N/A }
0N/A
0N/A // remember the offset of the load. The patching_epilog must be done
0N/A // before the call to add_debug_info, otherwise the PcDescs don't get
0N/A // entered in increasing order.
0N/A int offset = code_offset();
0N/A
0N/A assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
0N/A if (disp_reg == noreg) {
0N/A offset = load(src, disp_value, to_reg, type, unaligned);
0N/A } else {
0N/A assert(!unaligned, "can't handle this");
0N/A offset = load(src, disp_reg, to_reg, type);
0N/A }
0N/A
0N/A if (patch != NULL) {
0N/A patching_epilog(patch, patch_code, src, info);
0N/A }
0N/A
0N/A if (info != NULL) add_debug_info_for_null_check(offset, info);
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::prefetchr(LIR_Opr src) {
0N/A LIR_Address* addr = src->as_address_ptr();
0N/A Address from_addr = as_Address(addr);
0N/A
0N/A if (VM_Version::has_v9()) {
0N/A __ prefetch(from_addr, Assembler::severalReads);
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::prefetchw(LIR_Opr src) {
0N/A LIR_Address* addr = src->as_address_ptr();
0N/A Address from_addr = as_Address(addr);
0N/A
0N/A if (VM_Version::has_v9()) {
0N/A __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads);
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
0N/A Address addr;
0N/A if (src->is_single_word()) {
0N/A addr = frame_map()->address_for_slot(src->single_stack_ix());
0N/A } else if (src->is_double_word()) {
0N/A addr = frame_map()->address_for_double_slot(src->double_stack_ix());
0N/A }
0N/A
0N/A bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
0N/A load(addr.base(), addr.disp(), dest, dest->type(), unaligned);
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
0N/A Address addr;
0N/A if (dest->is_single_word()) {
0N/A addr = frame_map()->address_for_slot(dest->single_stack_ix());
0N/A } else if (dest->is_double_word()) {
0N/A addr = frame_map()->address_for_slot(dest->double_stack_ix());
0N/A }
0N/A bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
0N/A store(from_reg, addr.base(), addr.disp(), from_reg->type(), unaligned);
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
0N/A if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
0N/A if (from_reg->is_double_fpu()) {
0N/A // double to double moves
0N/A assert(to_reg->is_double_fpu(), "should match");
0N/A __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg());
0N/A } else {
0N/A // float to float moves
0N/A assert(to_reg->is_single_fpu(), "should match");
0N/A __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg());
0N/A }
0N/A } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
0N/A if (from_reg->is_double_cpu()) {
0N/A#ifdef _LP64
0N/A __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register());
0N/A#else
0N/A assert(to_reg->is_double_cpu() &&
0N/A from_reg->as_register_hi() != to_reg->as_register_lo() &&
0N/A from_reg->as_register_lo() != to_reg->as_register_hi(),
0N/A "should both be long and not overlap");
0N/A // long to long moves
0N/A __ mov(from_reg->as_register_hi(), to_reg->as_register_hi());
0N/A __ mov(from_reg->as_register_lo(), to_reg->as_register_lo());
0N/A#endif
0N/A#ifdef _LP64
0N/A } else if (to_reg->is_double_cpu()) {
0N/A // int to int moves
0N/A __ mov(from_reg->as_register(), to_reg->as_register_lo());
0N/A#endif
0N/A } else {
0N/A // int to int moves
0N/A __ mov(from_reg->as_register(), to_reg->as_register());
0N/A }
0N/A } else {
0N/A ShouldNotReachHere();
0N/A }
0N/A if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
0N/A __ verify_oop(to_reg->as_register());
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
0N/A LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
0N/A bool unaligned) {
0N/A LIR_Address* addr = dest->as_address_ptr();
0N/A
0N/A Register src = addr->base()->as_pointer_register();
0N/A Register disp_reg = noreg;
0N/A int disp_value = addr->disp();
0N/A bool needs_patching = (patch_code != lir_patch_none);
0N/A
0N/A if (addr->base()->is_oop_register()) {
0N/A __ verify_oop(src);
0N/A }
0N/A
0N/A PatchingStub* patch = NULL;
0N/A if (needs_patching) {
0N/A patch = new PatchingStub(_masm, PatchingStub::access_field_id);
0N/A assert(!from_reg->is_double_cpu() ||
0N/A patch_code == lir_patch_none ||
0N/A patch_code == lir_patch_normal, "patching doesn't match register");
0N/A }
0N/A
0N/A if (addr->index()->is_illegal()) {
0N/A if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) {
0N/A if (needs_patching) {
727N/A __ patchable_set(0, O7);
0N/A } else {
0N/A __ set(disp_value, O7);
0N/A }
0N/A disp_reg = O7;
0N/A }
0N/A } else if (unaligned || PatchALot) {
0N/A __ add(src, addr->index()->as_register(), O7);
0N/A src = O7;
0N/A } else {
0N/A disp_reg = addr->index()->as_pointer_register();
0N/A assert(disp_value == 0, "can't handle 3 operand addresses");
0N/A }
0N/A
0N/A // remember the offset of the store. The patching_epilog must be done
0N/A // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
0N/A // entered in increasing order.
0N/A int offset;
0N/A
0N/A assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up");
0N/A if (disp_reg == noreg) {
0N/A offset = store(from_reg, src, disp_value, type, unaligned);
0N/A } else {
0N/A assert(!unaligned, "can't handle this");
0N/A offset = store(from_reg, src, disp_reg, type);
0N/A }
0N/A
0N/A if (patch != NULL) {
0N/A patching_epilog(patch, patch_code, src, info);
0N/A }
0N/A
0N/A if (info != NULL) add_debug_info_for_null_check(offset, info);
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::return_op(LIR_Opr result) {
0N/A // the poll may need a register so just pick one that isn't the return register
0N/A#ifdef TIERED
0N/A if (result->type_field() == LIR_OprDesc::long_type) {
0N/A // Must move the result to G1
0N/A // Must leave proper result in O0,O1 and G1 (TIERED only)
0N/A __ sllx(I0, 32, G1); // Shift bits into high G1
0N/A __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
0N/A __ or3 (I1, G1, G1); // OR 64 bits into G1
0N/A }
0N/A#endif // TIERED
0N/A __ set((intptr_t)os::get_polling_page(), L0);
0N/A __ relocate(relocInfo::poll_return_type);
0N/A __ ld_ptr(L0, 0, G0);
0N/A __ ret();
0N/A __ delayed()->restore();
0N/A}
0N/A
0N/A
0N/Aint LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
0N/A __ set((intptr_t)os::get_polling_page(), tmp->as_register());
0N/A if (info != NULL) {
0N/A add_debug_info_for_branch(info);
0N/A } else {
0N/A __ relocate(relocInfo::poll_type);
0N/A }
0N/A
0N/A int offset = __ offset();
0N/A __ ld_ptr(tmp->as_register(), 0, G0);
0N/A
0N/A return offset;
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::emit_static_call_stub() {
0N/A address call_pc = __ pc();
0N/A address stub = __ start_a_stub(call_stub_size);
0N/A if (stub == NULL) {
0N/A bailout("static call stub overflow");
0N/A return;
0N/A }
0N/A
0N/A int start = __ offset();
0N/A __ relocate(static_stub_Relocation::spec(call_pc));
0N/A
0N/A __ set_oop(NULL, G5);
0N/A // must be set to -1 at code generation time
727N/A AddressLiteral addrlit(-1);
727N/A __ jump_to(addrlit, G3);
0N/A __ delayed()->nop();
0N/A
0N/A assert(__ offset() - start <= call_stub_size, "stub too big");
0N/A __ end_a_stub();
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
0N/A if (opr1->is_single_fpu()) {
0N/A __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg());
0N/A } else if (opr1->is_double_fpu()) {
0N/A __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg());
0N/A } else if (opr1->is_single_cpu()) {
0N/A if (opr2->is_constant()) {
0N/A switch (opr2->as_constant_ptr()->type()) {
0N/A case T_INT:
0N/A { jint con = opr2->as_constant_ptr()->as_jint();
0N/A if (Assembler::is_simm13(con)) {
0N/A __ cmp(opr1->as_register(), con);
0N/A } else {
0N/A __ set(con, O7);
0N/A __ cmp(opr1->as_register(), O7);
0N/A }
0N/A }
0N/A break;
0N/A
0N/A case T_OBJECT:
0N/A // there are only equal/notequal comparisions on objects
0N/A { jobject con = opr2->as_constant_ptr()->as_jobject();
0N/A if (con == NULL) {
0N/A __ cmp(opr1->as_register(), 0);
0N/A } else {
0N/A jobject2reg(con, O7);
0N/A __ cmp(opr1->as_register(), O7);
0N/A }
0N/A }
0N/A break;
0N/A
0N/A default:
0N/A ShouldNotReachHere();
0N/A break;
0N/A }
0N/A } else {
0N/A if (opr2->is_address()) {
0N/A LIR_Address * addr = opr2->as_address_ptr();
0N/A BasicType type = addr->type();
0N/A if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
0N/A else __ ld(as_Address(addr), O7);
0N/A __ cmp(opr1->as_register(), O7);
0N/A } else {
0N/A __ cmp(opr1->as_register(), opr2->as_register());
0N/A }
0N/A }
0N/A } else if (opr1->is_double_cpu()) {
0N/A Register xlo = opr1->as_register_lo();
0N/A Register xhi = opr1->as_register_hi();
0N/A if (opr2->is_constant() && opr2->as_jlong() == 0) {
0N/A assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases");
0N/A#ifdef _LP64
0N/A __ orcc(xhi, G0, G0);
0N/A#else
0N/A __ orcc(xhi, xlo, G0);
0N/A#endif
0N/A } else if (opr2->is_register()) {
0N/A Register ylo = opr2->as_register_lo();
0N/A Register yhi = opr2->as_register_hi();
0N/A#ifdef _LP64
0N/A __ cmp(xlo, ylo);
0N/A#else
0N/A __ subcc(xlo, ylo, xlo);
0N/A __ subccc(xhi, yhi, xhi);
0N/A if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
0N/A __ orcc(xhi, xlo, G0);
0N/A }
0N/A#endif
0N/A } else {
0N/A ShouldNotReachHere();
0N/A }
0N/A } else if (opr1->is_address()) {
0N/A LIR_Address * addr = opr1->as_address_ptr();
0N/A BasicType type = addr->type();
0N/A assert (opr2->is_constant(), "Checking");
0N/A if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7);
0N/A else __ ld(as_Address(addr), O7);
0N/A __ cmp(O7, opr2->as_constant_ptr()->as_jint());
0N/A } else {
0N/A ShouldNotReachHere();
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
0N/A if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
0N/A bool is_unordered_less = (code == lir_ucmp_fd2i);
0N/A if (left->is_single_fpu()) {
0N/A __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
0N/A } else if (left->is_double_fpu()) {
0N/A __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
0N/A } else {
0N/A ShouldNotReachHere();
0N/A }
0N/A } else if (code == lir_cmp_l2i) {
0N/A __ lcmp(left->as_register_hi(), left->as_register_lo(),
0N/A right->as_register_hi(), right->as_register_lo(),
0N/A dst->as_register());
0N/A } else {
0N/A ShouldNotReachHere();
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) {
0N/A
0N/A Assembler::Condition acond;
0N/A switch (condition) {
0N/A case lir_cond_equal: acond = Assembler::equal; break;
0N/A case lir_cond_notEqual: acond = Assembler::notEqual; break;
0N/A case lir_cond_less: acond = Assembler::less; break;
0N/A case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
0N/A case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break;
0N/A case lir_cond_greater: acond = Assembler::greater; break;
0N/A case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break;
0N/A case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break;
0N/A default: ShouldNotReachHere();
0N/A };
0N/A
0N/A if (opr1->is_constant() && opr1->type() == T_INT) {
0N/A Register dest = result->as_register();
0N/A // load up first part of constant before branch
0N/A // and do the rest in the delay slot.
0N/A if (!Assembler::is_simm13(opr1->as_jint())) {
0N/A __ sethi(opr1->as_jint(), dest);
0N/A }
0N/A } else if (opr1->is_constant()) {
0N/A const2reg(opr1, result, lir_patch_none, NULL);
0N/A } else if (opr1->is_register()) {
0N/A reg2reg(opr1, result);
0N/A } else if (opr1->is_stack()) {
0N/A stack2reg(opr1, result, result->type());
0N/A } else {
0N/A ShouldNotReachHere();
0N/A }
0N/A Label skip;
0N/A __ br(acond, false, Assembler::pt, skip);
0N/A if (opr1->is_constant() && opr1->type() == T_INT) {
0N/A Register dest = result->as_register();
0N/A if (Assembler::is_simm13(opr1->as_jint())) {
0N/A __ delayed()->or3(G0, opr1->as_jint(), dest);
0N/A } else {
0N/A // the sethi has been done above, so just put in the low 10 bits
0N/A __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest);
0N/A }
0N/A } else {
0N/A // can't do anything useful in the delay slot
0N/A __ delayed()->nop();
0N/A }
0N/A if (opr2->is_constant()) {
0N/A const2reg(opr2, result, lir_patch_none, NULL);
0N/A } else if (opr2->is_register()) {
0N/A reg2reg(opr2, result);
0N/A } else if (opr2->is_stack()) {
0N/A stack2reg(opr2, result, result->type());
0N/A } else {
0N/A ShouldNotReachHere();
0N/A }
0N/A __ bind(skip);
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
0N/A assert(info == NULL, "unused on this code path");
0N/A assert(left->is_register(), "wrong items state");
0N/A assert(dest->is_register(), "wrong items state");
0N/A
0N/A if (right->is_register()) {
0N/A if (dest->is_float_kind()) {
0N/A
0N/A FloatRegister lreg, rreg, res;
0N/A FloatRegisterImpl::Width w;
0N/A if (right->is_single_fpu()) {
0N/A w = FloatRegisterImpl::S;
0N/A lreg = left->as_float_reg();
0N/A rreg = right->as_float_reg();
0N/A res = dest->as_float_reg();
0N/A } else {
0N/A w = FloatRegisterImpl::D;
0N/A lreg = left->as_double_reg();
0N/A rreg = right->as_double_reg();
0N/A res = dest->as_double_reg();
0N/A }
0N/A
0N/A switch (code) {
0N/A case lir_add: __ fadd(w, lreg, rreg, res); break;
0N/A case lir_sub: __ fsub(w, lreg, rreg, res); break;
0N/A case lir_mul: // fall through
0N/A case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break;
0N/A case lir_div: // fall through
0N/A case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break;
0N/A default: ShouldNotReachHere();
0N/A }
0N/A
0N/A } else if (dest->is_double_cpu()) {
0N/A#ifdef _LP64
0N/A Register dst_lo = dest->as_register_lo();
0N/A Register op1_lo = left->as_pointer_register();
0N/A Register op2_lo = right->as_pointer_register();
0N/A
0N/A switch (code) {
0N/A case lir_add:
0N/A __ add(op1_lo, op2_lo, dst_lo);
0N/A break;
0N/A
0N/A case lir_sub:
0N/A __ sub(op1_lo, op2_lo, dst_lo);
0N/A break;
0N/A
0N/A default: ShouldNotReachHere();
0N/A }
0N/A#else
0N/A Register op1_lo = left->as_register_lo();
0N/A Register op1_hi = left->as_register_hi();
0N/A Register op2_lo = right->as_register_lo();
0N/A Register op2_hi = right->as_register_hi();
0N/A Register dst_lo = dest->as_register_lo();
0N/A Register dst_hi = dest->as_register_hi();
0N/A
0N/A switch (code) {
0N/A case lir_add:
0N/A __ addcc(op1_lo, op2_lo, dst_lo);
0N/A __ addc (op1_hi, op2_hi, dst_hi);
0N/A break;
0N/A
0N/A case lir_sub:
0N/A __ subcc(op1_lo, op2_lo, dst_lo);
0N/A __ subc (op1_hi, op2_hi, dst_hi);
0N/A break;
0N/A
0N/A default: ShouldNotReachHere();
0N/A }
0N/A#endif
0N/A } else {
0N/A assert (right->is_single_cpu(), "Just Checking");
0N/A
0N/A Register lreg = left->as_register();
0N/A Register res = dest->as_register();
0N/A Register rreg = right->as_register();
0N/A switch (code) {
0N/A case lir_add: __ add (lreg, rreg, res); break;
0N/A case lir_sub: __ sub (lreg, rreg, res); break;
0N/A case lir_mul: __ mult (lreg, rreg, res); break;
0N/A default: ShouldNotReachHere();
0N/A }
0N/A }
0N/A } else {
0N/A assert (right->is_constant(), "must be constant");
0N/A
0N/A if (dest->is_single_cpu()) {
0N/A Register lreg = left->as_register();
0N/A Register res = dest->as_register();
0N/A int simm13 = right->as_constant_ptr()->as_jint();
0N/A
0N/A switch (code) {
0N/A case lir_add: __ add (lreg, simm13, res); break;
0N/A case lir_sub: __ sub (lreg, simm13, res); break;
0N/A case lir_mul: __ mult (lreg, simm13, res); break;
0N/A default: ShouldNotReachHere();
0N/A }
0N/A } else {
0N/A Register lreg = left->as_pointer_register();
0N/A Register res = dest->as_register_lo();
0N/A long con = right->as_constant_ptr()->as_jlong();
0N/A assert(Assembler::is_simm13(con), "must be simm13");
0N/A
0N/A switch (code) {
0N/A case lir_add: __ add (lreg, (int)con, res); break;
0N/A case lir_sub: __ sub (lreg, (int)con, res); break;
0N/A case lir_mul: __ mult (lreg, (int)con, res); break;
0N/A default: ShouldNotReachHere();
0N/A }
0N/A }
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::fpop() {
0N/A // do nothing
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
0N/A switch (code) {
0N/A case lir_sin:
0N/A case lir_tan:
0N/A case lir_cos: {
0N/A assert(thread->is_valid(), "preserve the thread object for performance reasons");
0N/A assert(dest->as_double_reg() == F0, "the result will be in f0/f1");
0N/A break;
0N/A }
0N/A case lir_sqrt: {
0N/A assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
0N/A FloatRegister src_reg = value->as_double_reg();
0N/A FloatRegister dst_reg = dest->as_double_reg();
0N/A __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg);
0N/A break;
0N/A }
0N/A case lir_abs: {
0N/A assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
0N/A FloatRegister src_reg = value->as_double_reg();
0N/A FloatRegister dst_reg = dest->as_double_reg();
0N/A __ fabs(FloatRegisterImpl::D, src_reg, dst_reg);
0N/A break;
0N/A }
0N/A default: {
0N/A ShouldNotReachHere();
0N/A break;
0N/A }
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
0N/A if (right->is_constant()) {
0N/A if (dest->is_single_cpu()) {
0N/A int simm13 = right->as_constant_ptr()->as_jint();
0N/A switch (code) {
0N/A case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break;
0N/A case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break;
0N/A case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break;
0N/A default: ShouldNotReachHere();
0N/A }
0N/A } else {
0N/A long c = right->as_constant_ptr()->as_jlong();
0N/A assert(c == (int)c && Assembler::is_simm13(c), "out of range");
0N/A int simm13 = (int)c;
0N/A switch (code) {
0N/A case lir_logic_and:
0N/A#ifndef _LP64
0N/A __ and3 (left->as_register_hi(), 0, dest->as_register_hi());
0N/A#endif
0N/A __ and3 (left->as_register_lo(), simm13, dest->as_register_lo());
0N/A break;
0N/A
0N/A case lir_logic_or:
0N/A#ifndef _LP64
0N/A __ or3 (left->as_register_hi(), 0, dest->as_register_hi());
0N/A#endif
0N/A __ or3 (left->as_register_lo(), simm13, dest->as_register_lo());
0N/A break;
0N/A
0N/A case lir_logic_xor:
0N/A#ifndef _LP64
0N/A __ xor3 (left->as_register_hi(), 0, dest->as_register_hi());
0N/A#endif
0N/A __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo());
0N/A break;
0N/A
0N/A default: ShouldNotReachHere();
0N/A }
0N/A }
0N/A } else {
0N/A assert(right->is_register(), "right should be in register");
0N/A
0N/A if (dest->is_single_cpu()) {
0N/A switch (code) {
0N/A case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break;
0N/A case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break;
0N/A case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break;
0N/A default: ShouldNotReachHere();
0N/A }
0N/A } else {
0N/A#ifdef _LP64
0N/A Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
0N/A left->as_register_lo();
0N/A Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
0N/A right->as_register_lo();
0N/A
0N/A switch (code) {
0N/A case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break;
0N/A case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break;
0N/A case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break;
0N/A default: ShouldNotReachHere();
0N/A }
0N/A#else
0N/A switch (code) {
0N/A case lir_logic_and:
0N/A __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
0N/A __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
0N/A break;
0N/A
0N/A case lir_logic_or:
0N/A __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
0N/A __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
0N/A break;
0N/A
0N/A case lir_logic_xor:
0N/A __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi());
0N/A __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo());
0N/A break;
0N/A
0N/A default: ShouldNotReachHere();
0N/A }
0N/A#endif
0N/A }
0N/A }
0N/A}
0N/A
0N/A
0N/Aint LIR_Assembler::shift_amount(BasicType t) {
29N/A int elem_size = type2aelembytes(t);
0N/A switch (elem_size) {
0N/A case 1 : return 0;
0N/A case 2 : return 1;
0N/A case 4 : return 2;
0N/A case 8 : return 3;
0N/A }
0N/A ShouldNotReachHere();
0N/A return -1;
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info, bool unwind) {
0N/A assert(exceptionOop->as_register() == Oexception, "should match");
0N/A assert(unwind || exceptionPC->as_register() == Oissuing_pc, "should match");
0N/A
0N/A info->add_register_oop(exceptionOop);
0N/A
0N/A if (unwind) {
0N/A __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type);
0N/A __ delayed()->nop();
0N/A } else {
0N/A // reuse the debug info from the safepoint poll for the throw op itself
0N/A address pc_for_athrow = __ pc();
0N/A int pc_for_athrow_offset = __ offset();
0N/A RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
727N/A __ set(pc_for_athrow, Oissuing_pc, rspec);
0N/A add_call_info(pc_for_athrow_offset, info); // for exception handler
0N/A
0N/A __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type);
0N/A __ delayed()->nop();
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
0N/A Register src = op->src()->as_register();
0N/A Register dst = op->dst()->as_register();
0N/A Register src_pos = op->src_pos()->as_register();
0N/A Register dst_pos = op->dst_pos()->as_register();
0N/A Register length = op->length()->as_register();
0N/A Register tmp = op->tmp()->as_register();
0N/A Register tmp2 = O7;
0N/A
0N/A int flags = op->flags();
0N/A ciArrayKlass* default_type = op->expected_type();
0N/A BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
0N/A if (basic_type == T_ARRAY) basic_type = T_OBJECT;
0N/A
0N/A // set up the arraycopy stub information
0N/A ArrayCopyStub* stub = op->stub();
0N/A
0N/A // always do stub if no type information is available. it's ok if
0N/A // the known type isn't loaded since the code sanity checks
0N/A // in debug mode and the type isn't required when we know the exact type
0N/A // also check that the type is an array type.
342N/A // We also, for now, always call the stub if the barrier set requires a
342N/A // write_ref_pre barrier (which the stub does, but none of the optimized
342N/A // cases currently does).
342N/A if (op->expected_type() == NULL ||
342N/A Universe::heap()->barrier_set()->has_write_ref_pre_barrier()) {
0N/A __ mov(src, O0);
0N/A __ mov(src_pos, O1);
0N/A __ mov(dst, O2);
0N/A __ mov(dst_pos, O3);
0N/A __ mov(length, O4);
0N/A __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy));
0N/A
0N/A __ br_zero(Assembler::less, false, Assembler::pn, O0, *stub->entry());
0N/A __ delayed()->nop();
0N/A __ bind(*stub->continuation());
0N/A return;
0N/A }
0N/A
0N/A assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
0N/A
0N/A // make sure src and dst are non-null and load array length
0N/A if (flags & LIR_OpArrayCopy::src_null_check) {
0N/A __ tst(src);
0N/A __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
0N/A __ delayed()->nop();
0N/A }
0N/A
0N/A if (flags & LIR_OpArrayCopy::dst_null_check) {
0N/A __ tst(dst);
0N/A __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
0N/A __ delayed()->nop();
0N/A }
0N/A
0N/A if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
0N/A // test src_pos register
0N/A __ tst(src_pos);
0N/A __ br(Assembler::less, false, Assembler::pn, *stub->entry());
0N/A __ delayed()->nop();
0N/A }
0N/A
0N/A if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
0N/A // test dst_pos register
0N/A __ tst(dst_pos);
0N/A __ br(Assembler::less, false, Assembler::pn, *stub->entry());
0N/A __ delayed()->nop();
0N/A }
0N/A
0N/A if (flags & LIR_OpArrayCopy::length_positive_check) {
0N/A // make sure length isn't negative
0N/A __ tst(length);
0N/A __ br(Assembler::less, false, Assembler::pn, *stub->entry());
0N/A __ delayed()->nop();
0N/A }
0N/A
0N/A if (flags & LIR_OpArrayCopy::src_range_check) {
0N/A __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2);
0N/A __ add(length, src_pos, tmp);
0N/A __ cmp(tmp2, tmp);
0N/A __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
0N/A __ delayed()->nop();
0N/A }
0N/A
0N/A if (flags & LIR_OpArrayCopy::dst_range_check) {
0N/A __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2);
0N/A __ add(length, dst_pos, tmp);
0N/A __ cmp(tmp2, tmp);
0N/A __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry());
0N/A __ delayed()->nop();
0N/A }
0N/A
0N/A if (flags & LIR_OpArrayCopy::type_check) {
0N/A __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp);
0N/A __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
0N/A __ cmp(tmp, tmp2);
0N/A __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
0N/A __ delayed()->nop();
0N/A }
0N/A
0N/A#ifdef ASSERT
0N/A if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
0N/A // Sanity check the known type with the incoming class. For the
0N/A // primitive case the types must match exactly with src.klass and
0N/A // dst.klass each exactly matching the default type. For the
0N/A // object array case, if no type check is needed then either the
0N/A // dst type is exactly the expected type and the src type is a
0N/A // subtype which we can't check or src is the same array as dst
0N/A // but not necessarily exactly of type default_type.
0N/A Label known_ok, halt;
989N/A jobject2reg(op->expected_type()->constant_encoding(), tmp);
0N/A __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2);
0N/A if (basic_type != T_OBJECT) {
0N/A __ cmp(tmp, tmp2);
0N/A __ br(Assembler::notEqual, false, Assembler::pn, halt);
0N/A __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2);
0N/A __ cmp(tmp, tmp2);
0N/A __ br(Assembler::equal, false, Assembler::pn, known_ok);
0N/A __ delayed()->nop();
0N/A } else {
0N/A __ cmp(tmp, tmp2);
0N/A __ br(Assembler::equal, false, Assembler::pn, known_ok);
0N/A __ delayed()->cmp(src, dst);
0N/A __ br(Assembler::equal, false, Assembler::pn, known_ok);
0N/A __ delayed()->nop();
0N/A }
0N/A __ bind(halt);
0N/A __ stop("incorrect type information in arraycopy");
0N/A __ bind(known_ok);
0N/A }
0N/A#endif
0N/A
0N/A int shift = shift_amount(basic_type);
0N/A
0N/A Register src_ptr = O0;
0N/A Register dst_ptr = O1;
0N/A Register len = O2;
0N/A
0N/A __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr);
1060N/A LP64_ONLY(__ sra(src_pos, 0, src_pos);) //higher 32bits must be null
0N/A if (shift == 0) {
0N/A __ add(src_ptr, src_pos, src_ptr);
0N/A } else {
0N/A __ sll(src_pos, shift, tmp);
0N/A __ add(src_ptr, tmp, src_ptr);
0N/A }
0N/A
0N/A __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr);
1060N/A LP64_ONLY(__ sra(dst_pos, 0, dst_pos);) //higher 32bits must be null
0N/A if (shift == 0) {
0N/A __ add(dst_ptr, dst_pos, dst_ptr);
0N/A } else {
0N/A __ sll(dst_pos, shift, tmp);
0N/A __ add(dst_ptr, tmp, dst_ptr);
0N/A }
0N/A
0N/A if (basic_type != T_OBJECT) {
0N/A if (shift == 0) {
0N/A __ mov(length, len);
0N/A } else {
0N/A __ sll(length, shift, len);
0N/A }
0N/A __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy));
0N/A } else {
0N/A // oop_arraycopy takes a length in number of elements, so don't scale it.
0N/A __ mov(length, len);
0N/A __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy));
0N/A }
0N/A
0N/A __ bind(*stub->continuation());
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
0N/A if (dest->is_single_cpu()) {
0N/A#ifdef _LP64
0N/A if (left->type() == T_OBJECT) {
0N/A switch (code) {
0N/A case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break;
0N/A case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break;
0N/A case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
0N/A default: ShouldNotReachHere();
0N/A }
0N/A } else
0N/A#endif
0N/A switch (code) {
0N/A case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break;
0N/A case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break;
0N/A case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break;
0N/A default: ShouldNotReachHere();
0N/A }
0N/A } else {
0N/A#ifdef _LP64
0N/A switch (code) {
0N/A case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
0N/A case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
0N/A case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break;
0N/A default: ShouldNotReachHere();
0N/A }
0N/A#else
0N/A switch (code) {
0N/A case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
0N/A case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
0N/A case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break;
0N/A default: ShouldNotReachHere();
0N/A }
0N/A#endif
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
0N/A#ifdef _LP64
0N/A if (left->type() == T_OBJECT) {
0N/A count = count & 63; // shouldn't shift by more than sizeof(intptr_t)
0N/A Register l = left->as_register();
0N/A Register d = dest->as_register_lo();
0N/A switch (code) {
0N/A case lir_shl: __ sllx (l, count, d); break;
0N/A case lir_shr: __ srax (l, count, d); break;
0N/A case lir_ushr: __ srlx (l, count, d); break;
0N/A default: ShouldNotReachHere();
0N/A }
0N/A return;
0N/A }
0N/A#endif
0N/A
0N/A if (dest->is_single_cpu()) {
0N/A count = count & 0x1F; // Java spec
0N/A switch (code) {
0N/A case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break;
0N/A case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break;
0N/A case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break;
0N/A default: ShouldNotReachHere();
0N/A }
0N/A } else if (dest->is_double_cpu()) {
0N/A count = count & 63; // Java spec
0N/A switch (code) {
0N/A case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
0N/A case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break;
0N/A case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break;
0N/A default: ShouldNotReachHere();
0N/A }
0N/A } else {
0N/A ShouldNotReachHere();
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
0N/A assert(op->tmp1()->as_register() == G1 &&
0N/A op->tmp2()->as_register() == G3 &&
0N/A op->tmp3()->as_register() == G4 &&
0N/A op->obj()->as_register() == O0 &&
0N/A op->klass()->as_register() == G5, "must be");
0N/A if (op->init_check()) {
0N/A __ ld(op->klass()->as_register(),
0N/A instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc),
0N/A op->tmp1()->as_register());
0N/A add_debug_info_for_null_check_here(op->stub()->info());
0N/A __ cmp(op->tmp1()->as_register(), instanceKlass::fully_initialized);
0N/A __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry());
0N/A __ delayed()->nop();
0N/A }
0N/A __ allocate_object(op->obj()->as_register(),
0N/A op->tmp1()->as_register(),
0N/A op->tmp2()->as_register(),
0N/A op->tmp3()->as_register(),
0N/A op->header_size(),
0N/A op->object_size(),
0N/A op->klass()->as_register(),
0N/A *op->stub()->entry());
0N/A __ bind(*op->stub()->continuation());
0N/A __ verify_oop(op->obj()->as_register());
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
0N/A assert(op->tmp1()->as_register() == G1 &&
0N/A op->tmp2()->as_register() == G3 &&
0N/A op->tmp3()->as_register() == G4 &&
0N/A op->tmp4()->as_register() == O1 &&
0N/A op->klass()->as_register() == G5, "must be");
0N/A if (UseSlowPath ||
0N/A (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
0N/A (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
0N/A __ br(Assembler::always, false, Assembler::pn, *op->stub()->entry());
0N/A __ delayed()->nop();
0N/A } else {
0N/A __ allocate_array(op->obj()->as_register(),
0N/A op->len()->as_register(),
0N/A op->tmp1()->as_register(),
0N/A op->tmp2()->as_register(),
0N/A op->tmp3()->as_register(),
0N/A arrayOopDesc::header_size(op->type()),
29N/A type2aelembytes(op->type()),
0N/A op->klass()->as_register(),
0N/A *op->stub()->entry());
0N/A }
0N/A __ bind(*op->stub()->continuation());
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
0N/A LIR_Code code = op->code();
0N/A if (code == lir_store_check) {
0N/A Register value = op->object()->as_register();
0N/A Register array = op->array()->as_register();
0N/A Register k_RInfo = op->tmp1()->as_register();
0N/A Register klass_RInfo = op->tmp2()->as_register();
0N/A Register Rtmp1 = op->tmp3()->as_register();
0N/A
0N/A __ verify_oop(value);
0N/A
0N/A CodeStub* stub = op->stub();
0N/A Label done;
0N/A __ cmp(value, 0);
0N/A __ br(Assembler::equal, false, Assembler::pn, done);
0N/A __ delayed()->nop();
0N/A load(array, oopDesc::klass_offset_in_bytes(), k_RInfo, T_OBJECT, op->info_for_exception());
0N/A load(value, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
0N/A
0N/A // get instance klass
0N/A load(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc), k_RInfo, T_OBJECT, NULL);
644N/A // perform the fast part of the checking logic
644N/A __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, &done, stub->entry(), NULL);
644N/A
644N/A // call out-of-line instance of __ check_klass_subtype_slow_path(...):
644N/A assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
0N/A __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
0N/A __ delayed()->nop();
0N/A __ cmp(G3, 0);
0N/A __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
0N/A __ delayed()->nop();
0N/A __ bind(done);
0N/A } else if (op->code() == lir_checkcast) {
0N/A // we always need a stub for the failure case.
0N/A CodeStub* stub = op->stub();
0N/A Register obj = op->object()->as_register();
0N/A Register k_RInfo = op->tmp1()->as_register();
0N/A Register klass_RInfo = op->tmp2()->as_register();
0N/A Register dst = op->result_opr()->as_register();
0N/A Register Rtmp1 = op->tmp3()->as_register();
0N/A ciKlass* k = op->klass();
0N/A
0N/A if (obj == k_RInfo) {
0N/A k_RInfo = klass_RInfo;
0N/A klass_RInfo = obj;
0N/A }
0N/A if (op->profiled_method() != NULL) {
0N/A ciMethod* method = op->profiled_method();
0N/A int bci = op->profiled_bci();
0N/A
0N/A // We need two temporaries to perform this operation on SPARC,
0N/A // so to keep things simple we perform a redundant test here
0N/A Label profile_done;
0N/A __ cmp(obj, 0);
0N/A __ br(Assembler::notEqual, false, Assembler::pn, profile_done);
0N/A __ delayed()->nop();
0N/A // Object is null; update methodDataOop
0N/A ciMethodData* md = method->method_data();
0N/A if (md == NULL) {
0N/A bailout("out of memory building methodDataOop");
0N/A return;
0N/A }
0N/A ciProfileData* data = md->bci_to_data(bci);
0N/A assert(data != NULL, "need data for checkcast");
0N/A assert(data->is_BitData(), "need BitData for checkcast");
0N/A Register mdo = k_RInfo;
0N/A Register data_val = Rtmp1;
989N/A jobject2reg(md->constant_encoding(), mdo);
0N/A
0N/A int mdo_offset_bias = 0;
0N/A if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
0N/A // The offset is large so bias the mdo by the base of the slot so
0N/A // that the ld can use simm13s to reference the slots of the data
0N/A mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
0N/A __ set(mdo_offset_bias, data_val);
0N/A __ add(mdo, data_val, mdo);
0N/A }
0N/A
0N/A
727N/A Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
0N/A __ ldub(flags_addr, data_val);
0N/A __ or3(data_val, BitData::null_seen_byte_constant(), data_val);
0N/A __ stb(data_val, flags_addr);
0N/A __ bind(profile_done);
0N/A }
0N/A
0N/A Label done;
0N/A // patching may screw with our temporaries on sparc,
0N/A // so let's do it before loading the class
0N/A if (k->is_loaded()) {
989N/A jobject2reg(k->constant_encoding(), k_RInfo);
0N/A } else {
0N/A jobject2reg_with_patching(k_RInfo, op->info_for_patch());
0N/A }
0N/A assert(obj != k_RInfo, "must be different");
0N/A __ cmp(obj, 0);
0N/A __ br(Assembler::equal, false, Assembler::pn, done);
0N/A __ delayed()->nop();
0N/A
0N/A // get object class
0N/A // not a safepoint as obj null check happens earlier
0N/A load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
0N/A if (op->fast_check()) {
0N/A assert_different_registers(klass_RInfo, k_RInfo);
0N/A __ cmp(k_RInfo, klass_RInfo);
0N/A __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry());
0N/A __ delayed()->nop();
0N/A __ bind(done);
0N/A } else {
644N/A bool need_slow_path = true;
0N/A if (k->is_loaded()) {
644N/A if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())
644N/A need_slow_path = false;
644N/A // perform the fast part of the checking logic
644N/A __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg,
644N/A (need_slow_path ? &done : NULL),
644N/A stub->entry(), NULL,
665N/A RegisterOrConstant(k->super_check_offset()));
0N/A } else {
644N/A // perform the fast part of the checking logic
644N/A __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7,
644N/A &done, stub->entry(), NULL);
644N/A }
644N/A if (need_slow_path) {
644N/A // call out-of-line instance of __ check_klass_subtype_slow_path(...):
644N/A assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
0N/A __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
0N/A __ delayed()->nop();
0N/A __ cmp(G3, 0);
0N/A __ br(Assembler::equal, false, Assembler::pn, *stub->entry());
0N/A __ delayed()->nop();
0N/A }
644N/A __ bind(done);
0N/A }
0N/A __ mov(obj, dst);
0N/A } else if (code == lir_instanceof) {
0N/A Register obj = op->object()->as_register();
0N/A Register k_RInfo = op->tmp1()->as_register();
0N/A Register klass_RInfo = op->tmp2()->as_register();
0N/A Register dst = op->result_opr()->as_register();
0N/A Register Rtmp1 = op->tmp3()->as_register();
0N/A ciKlass* k = op->klass();
0N/A
0N/A Label done;
0N/A if (obj == k_RInfo) {
0N/A k_RInfo = klass_RInfo;
0N/A klass_RInfo = obj;
0N/A }
0N/A // patching may screw with our temporaries on sparc,
0N/A // so let's do it before loading the class
0N/A if (k->is_loaded()) {
989N/A jobject2reg(k->constant_encoding(), k_RInfo);
0N/A } else {
0N/A jobject2reg_with_patching(k_RInfo, op->info_for_patch());
0N/A }
0N/A assert(obj != k_RInfo, "must be different");
0N/A __ cmp(obj, 0);
0N/A __ br(Assembler::equal, true, Assembler::pn, done);
0N/A __ delayed()->set(0, dst);
0N/A
0N/A // get object class
0N/A // not a safepoint as obj null check happens earlier
0N/A load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL);
0N/A if (op->fast_check()) {
0N/A __ cmp(k_RInfo, klass_RInfo);
0N/A __ br(Assembler::equal, true, Assembler::pt, done);
0N/A __ delayed()->set(1, dst);
0N/A __ set(0, dst);
0N/A __ bind(done);
0N/A } else {
644N/A bool need_slow_path = true;
0N/A if (k->is_loaded()) {
644N/A if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())
644N/A need_slow_path = false;
644N/A // perform the fast part of the checking logic
644N/A __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, O7, noreg,
644N/A (need_slow_path ? &done : NULL),
644N/A (need_slow_path ? &done : NULL), NULL,
665N/A RegisterOrConstant(k->super_check_offset()),
644N/A dst);
0N/A } else {
0N/A assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers");
644N/A // perform the fast part of the checking logic
644N/A __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, O7, dst,
644N/A &done, &done, NULL,
665N/A RegisterOrConstant(-1),
644N/A dst);
644N/A }
644N/A if (need_slow_path) {
644N/A // call out-of-line instance of __ check_klass_subtype_slow_path(...):
644N/A assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup");
0N/A __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
0N/A __ delayed()->nop();
0N/A __ mov(G3, dst);
0N/A }
644N/A __ bind(done);
0N/A }
0N/A } else {
0N/A ShouldNotReachHere();
0N/A }
0N/A
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
0N/A if (op->code() == lir_cas_long) {
0N/A assert(VM_Version::supports_cx8(), "wrong machine");
0N/A Register addr = op->addr()->as_pointer_register();
0N/A Register cmp_value_lo = op->cmp_value()->as_register_lo();
0N/A Register cmp_value_hi = op->cmp_value()->as_register_hi();
0N/A Register new_value_lo = op->new_value()->as_register_lo();
0N/A Register new_value_hi = op->new_value()->as_register_hi();
0N/A Register t1 = op->tmp1()->as_register();
0N/A Register t2 = op->tmp2()->as_register();
0N/A#ifdef _LP64
0N/A __ mov(cmp_value_lo, t1);
0N/A __ mov(new_value_lo, t2);
0N/A#else
0N/A // move high and low halves of long values into single registers
0N/A __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg
0N/A __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half
0N/A __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value
0N/A __ sllx(new_value_hi, 32, t2);
0N/A __ srl(new_value_lo, 0, new_value_lo);
0N/A __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap
0N/A#endif
0N/A // perform the compare and swap operation
0N/A __ casx(addr, t1, t2);
0N/A // generate condition code - if the swap succeeded, t2 ("new value" reg) was
0N/A // overwritten with the original value in "addr" and will be equal to t1.
0N/A __ cmp(t1, t2);
0N/A
0N/A } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
0N/A Register addr = op->addr()->as_pointer_register();
0N/A Register cmp_value = op->cmp_value()->as_register();
0N/A Register new_value = op->new_value()->as_register();
0N/A Register t1 = op->tmp1()->as_register();
0N/A Register t2 = op->tmp2()->as_register();
0N/A __ mov(cmp_value, t1);
0N/A __ mov(new_value, t2);
0N/A#ifdef _LP64
0N/A if (op->code() == lir_cas_obj) {
0N/A __ casx(addr, t1, t2);
0N/A } else
0N/A#endif
0N/A {
0N/A __ cas(addr, t1, t2);
0N/A }
0N/A __ cmp(t1, t2);
0N/A } else {
0N/A Unimplemented();
0N/A }
0N/A}
0N/A
0N/Avoid LIR_Assembler::set_24bit_FPU() {
0N/A Unimplemented();
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::reset_FPU() {
0N/A Unimplemented();
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::breakpoint() {
0N/A __ breakpoint_trap();
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::push(LIR_Opr opr) {
0N/A Unimplemented();
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::pop(LIR_Opr opr) {
0N/A Unimplemented();
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
0N/A Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
0N/A Register dst = dst_opr->as_register();
0N/A Register reg = mon_addr.base();
0N/A int offset = mon_addr.disp();
0N/A // compute pointer to BasicLock
0N/A if (mon_addr.is_simm13()) {
0N/A __ add(reg, offset, dst);
0N/A } else {
0N/A __ set(offset, dst);
0N/A __ add(dst, reg, dst);
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::emit_lock(LIR_OpLock* op) {
0N/A Register obj = op->obj_opr()->as_register();
0N/A Register hdr = op->hdr_opr()->as_register();
0N/A Register lock = op->lock_opr()->as_register();
0N/A
0N/A // obj may not be an oop
0N/A if (op->code() == lir_lock) {
0N/A MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
0N/A if (UseFastLocking) {
0N/A assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
0N/A // add debug info for NullPointerException only if one is possible
0N/A if (op->info() != NULL) {
0N/A add_debug_info_for_null_check_here(op->info());
0N/A }
0N/A __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
0N/A } else {
0N/A // always do slow locking
0N/A // note: the slow locking code could be inlined here, however if we use
0N/A // slow locking, speed doesn't matter anyway and this solution is
0N/A // simpler and requires less duplicated code - additionally, the
0N/A // slow locking code is the same in either case which simplifies
0N/A // debugging
0N/A __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
0N/A __ delayed()->nop();
0N/A }
0N/A } else {
0N/A assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
0N/A if (UseFastLocking) {
0N/A assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
0N/A __ unlock_object(hdr, obj, lock, *op->stub()->entry());
0N/A } else {
0N/A // always do slow unlocking
0N/A // note: the slow unlocking code could be inlined here, however if we use
0N/A // slow unlocking, speed doesn't matter anyway and this solution is
0N/A // simpler and requires less duplicated code - additionally, the
0N/A // slow unlocking code is the same in either case which simplifies
0N/A // debugging
0N/A __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry());
0N/A __ delayed()->nop();
0N/A }
0N/A }
0N/A __ bind(*op->stub()->continuation());
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
0N/A ciMethod* method = op->profiled_method();
0N/A int bci = op->profiled_bci();
0N/A
0N/A // Update counter for all call types
0N/A ciMethodData* md = method->method_data();
0N/A if (md == NULL) {
0N/A bailout("out of memory building methodDataOop");
0N/A return;
0N/A }
0N/A ciProfileData* data = md->bci_to_data(bci);
0N/A assert(data->is_CounterData(), "need CounterData for calls");
0N/A assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
0N/A assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
0N/A Register mdo = op->mdo()->as_register();
0N/A Register tmp1 = op->tmp1()->as_register();
989N/A jobject2reg(md->constant_encoding(), mdo);
0N/A int mdo_offset_bias = 0;
0N/A if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) +
0N/A data->size_in_bytes())) {
0N/A // The offset is large so bias the mdo by the base of the slot so
0N/A // that the ld can use simm13s to reference the slots of the data
0N/A mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
0N/A __ set(mdo_offset_bias, O7);
0N/A __ add(mdo, O7, mdo);
0N/A }
0N/A
727N/A Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
0N/A __ lduw(counter_addr, tmp1);
0N/A __ add(tmp1, DataLayout::counter_increment, tmp1);
0N/A __ stw(tmp1, counter_addr);
0N/A Bytecodes::Code bc = method->java_code_at_bci(bci);
0N/A // Perform additional virtual call profiling for invokevirtual and
0N/A // invokeinterface bytecodes
0N/A if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
0N/A Tier1ProfileVirtualCalls) {
0N/A assert(op->recv()->is_single_cpu(), "recv must be allocated");
0N/A Register recv = op->recv()->as_register();
0N/A assert_different_registers(mdo, tmp1, recv);
0N/A assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
0N/A ciKlass* known_klass = op->known_holder();
0N/A if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) {
0N/A // We know the type that will be seen at this call site; we can
0N/A // statically update the methodDataOop rather than needing to do
0N/A // dynamic tests on the receiver type
0N/A
0N/A // NOTE: we should probably put a lock around this search to
0N/A // avoid collisions by concurrent compilations
0N/A ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
0N/A uint i;
0N/A for (i = 0; i < VirtualCallData::row_limit(); i++) {
0N/A ciKlass* receiver = vc_data->receiver(i);
0N/A if (known_klass->equals(receiver)) {
727N/A Address data_addr(mdo, md->byte_offset_of_slot(data,
727N/A VirtualCallData::receiver_count_offset(i)) -
0N/A mdo_offset_bias);
0N/A __ lduw(data_addr, tmp1);
0N/A __ add(tmp1, DataLayout::counter_increment, tmp1);
0N/A __ stw(tmp1, data_addr);
0N/A return;
0N/A }
0N/A }
0N/A
0N/A // Receiver type not found in profile data; select an empty slot
0N/A
0N/A // Note that this is less efficient than it should be because it
0N/A // always does a write to the receiver part of the
0N/A // VirtualCallData rather than just the first time
0N/A for (i = 0; i < VirtualCallData::row_limit(); i++) {
0N/A ciKlass* receiver = vc_data->receiver(i);
0N/A if (receiver == NULL) {
727N/A Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
0N/A mdo_offset_bias);
989N/A jobject2reg(known_klass->constant_encoding(), tmp1);
0N/A __ st_ptr(tmp1, recv_addr);
727N/A Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
0N/A mdo_offset_bias);
0N/A __ lduw(data_addr, tmp1);
0N/A __ add(tmp1, DataLayout::counter_increment, tmp1);
0N/A __ stw(tmp1, data_addr);
0N/A return;
0N/A }
0N/A }
0N/A } else {
727N/A load(Address(recv, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT);
0N/A Label update_done;
0N/A uint i;
0N/A for (i = 0; i < VirtualCallData::row_limit(); i++) {
0N/A Label next_test;
0N/A // See if the receiver is receiver[n].
727N/A Address receiver_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
0N/A mdo_offset_bias);
0N/A __ ld_ptr(receiver_addr, tmp1);
0N/A __ verify_oop(tmp1);
0N/A __ cmp(recv, tmp1);
0N/A __ brx(Assembler::notEqual, false, Assembler::pt, next_test);
0N/A __ delayed()->nop();
727N/A Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
0N/A mdo_offset_bias);
0N/A __ lduw(data_addr, tmp1);
0N/A __ add(tmp1, DataLayout::counter_increment, tmp1);
0N/A __ stw(tmp1, data_addr);
0N/A __ br(Assembler::always, false, Assembler::pt, update_done);
0N/A __ delayed()->nop();
0N/A __ bind(next_test);
0N/A }
0N/A
0N/A // Didn't find receiver; find next empty slot and fill it in
0N/A for (i = 0; i < VirtualCallData::row_limit(); i++) {
0N/A Label next_test;
727N/A Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
0N/A mdo_offset_bias);
0N/A load(recv_addr, tmp1, T_OBJECT);
0N/A __ tst(tmp1);
0N/A __ brx(Assembler::notEqual, false, Assembler::pt, next_test);
0N/A __ delayed()->nop();
0N/A __ st_ptr(recv, recv_addr);
0N/A __ set(DataLayout::counter_increment, tmp1);
727N/A __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
727N/A mdo_offset_bias);
0N/A if (i < (VirtualCallData::row_limit() - 1)) {
0N/A __ br(Assembler::always, false, Assembler::pt, update_done);
0N/A __ delayed()->nop();
0N/A }
0N/A __ bind(next_test);
0N/A }
0N/A
0N/A __ bind(update_done);
0N/A }
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::align_backward_branch_target() {
0N/A __ align(16);
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::emit_delay(LIR_OpDelay* op) {
0N/A // make sure we are expecting a delay
0N/A // this has the side effect of clearing the delay state
0N/A // so we can use _masm instead of _masm->delayed() to do the
0N/A // code generation.
0N/A __ delayed();
0N/A
0N/A // make sure we only emit one instruction
0N/A int offset = code_offset();
0N/A op->delay_op()->emit_code(this);
0N/A#ifdef ASSERT
0N/A if (code_offset() - offset != NativeInstruction::nop_instruction_size) {
0N/A op->delay_op()->print();
0N/A }
0N/A assert(code_offset() - offset == NativeInstruction::nop_instruction_size,
0N/A "only one instruction can go in a delay slot");
0N/A#endif
0N/A
0N/A // we may also be emitting the call info for the instruction
0N/A // which we are the delay slot of.
0N/A CodeEmitInfo * call_info = op->call_info();
0N/A if (call_info) {
0N/A add_call_info(code_offset(), call_info);
0N/A }
0N/A
0N/A if (VerifyStackAtCalls) {
0N/A _masm->sub(FP, SP, O7);
0N/A _masm->cmp(O7, initial_frame_size_in_bytes());
0N/A _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 );
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
0N/A assert(left->is_register(), "can only handle registers");
0N/A
0N/A if (left->is_single_cpu()) {
0N/A __ neg(left->as_register(), dest->as_register());
0N/A } else if (left->is_single_fpu()) {
0N/A __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg());
0N/A } else if (left->is_double_fpu()) {
0N/A __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg());
0N/A } else {
0N/A assert (left->is_double_cpu(), "Must be a long");
0N/A Register Rlow = left->as_register_lo();
0N/A Register Rhi = left->as_register_hi();
0N/A#ifdef _LP64
0N/A __ sub(G0, Rlow, dest->as_register_lo());
0N/A#else
0N/A __ subcc(G0, Rlow, dest->as_register_lo());
0N/A __ subc (G0, Rhi, dest->as_register_hi());
0N/A#endif
0N/A }
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::fxch(int i) {
0N/A Unimplemented();
0N/A}
0N/A
0N/Avoid LIR_Assembler::fld(int i) {
0N/A Unimplemented();
0N/A}
0N/A
0N/Avoid LIR_Assembler::ffree(int i) {
0N/A Unimplemented();
0N/A}
0N/A
0N/Avoid LIR_Assembler::rt_call(LIR_Opr result, address dest,
0N/A const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
0N/A
0N/A // if tmp is invalid, then the function being called doesn't destroy the thread
0N/A if (tmp->is_valid()) {
0N/A __ save_thread(tmp->as_register());
0N/A }
0N/A __ call(dest, relocInfo::runtime_call_type);
0N/A __ delayed()->nop();
0N/A if (info != NULL) {
0N/A add_call_info_here(info);
0N/A }
0N/A if (tmp->is_valid()) {
0N/A __ restore_thread(tmp->as_register());
0N/A }
0N/A
0N/A#ifdef ASSERT
0N/A __ verify_thread();
0N/A#endif // ASSERT
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
0N/A#ifdef _LP64
0N/A ShouldNotReachHere();
0N/A#endif
0N/A
0N/A NEEDS_CLEANUP;
0N/A if (type == T_LONG) {
0N/A LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr();
0N/A
0N/A // (extended to allow indexed as well as constant displaced for JSR-166)
0N/A Register idx = noreg; // contains either constant offset or index
0N/A
0N/A int disp = mem_addr->disp();
0N/A if (mem_addr->index() == LIR_OprFact::illegalOpr) {
0N/A if (!Assembler::is_simm13(disp)) {
0N/A idx = O7;
0N/A __ set(disp, idx);
0N/A }
0N/A } else {
0N/A assert(disp == 0, "not both indexed and disp");
0N/A idx = mem_addr->index()->as_register();
0N/A }
0N/A
0N/A int null_check_offset = -1;
0N/A
0N/A Register base = mem_addr->base()->as_register();
0N/A if (src->is_register() && dest->is_address()) {
0N/A // G4 is high half, G5 is low half
0N/A if (VM_Version::v9_instructions_work()) {
0N/A // clear the top bits of G5, and scale up G4
0N/A __ srl (src->as_register_lo(), 0, G5);
0N/A __ sllx(src->as_register_hi(), 32, G4);
0N/A // combine the two halves into the 64 bits of G4
0N/A __ or3(G4, G5, G4);
0N/A null_check_offset = __ offset();
0N/A if (idx == noreg) {
0N/A __ stx(G4, base, disp);
0N/A } else {
0N/A __ stx(G4, base, idx);
0N/A }
0N/A } else {
0N/A __ mov (src->as_register_hi(), G4);
0N/A __ mov (src->as_register_lo(), G5);
0N/A null_check_offset = __ offset();
0N/A if (idx == noreg) {
0N/A __ std(G4, base, disp);
0N/A } else {
0N/A __ std(G4, base, idx);
0N/A }
0N/A }
0N/A } else if (src->is_address() && dest->is_register()) {
0N/A null_check_offset = __ offset();
0N/A if (VM_Version::v9_instructions_work()) {
0N/A if (idx == noreg) {
0N/A __ ldx(base, disp, G5);
0N/A } else {
0N/A __ ldx(base, idx, G5);
0N/A }
0N/A __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi
0N/A __ mov (G5, dest->as_register_lo()); // copy low half into lo
0N/A } else {
0N/A if (idx == noreg) {
0N/A __ ldd(base, disp, G4);
0N/A } else {
0N/A __ ldd(base, idx, G4);
0N/A }
0N/A // G4 is high half, G5 is low half
0N/A __ mov (G4, dest->as_register_hi());
0N/A __ mov (G5, dest->as_register_lo());
0N/A }
0N/A } else {
0N/A Unimplemented();
0N/A }
0N/A if (info != NULL) {
0N/A add_debug_info_for_null_check(null_check_offset, info);
0N/A }
0N/A
0N/A } else {
0N/A // use normal move for all other volatiles since they don't need
0N/A // special handling to remain atomic.
0N/A move_op(src, dest, type, lir_patch_none, info, false, false);
0N/A }
0N/A}
0N/A
0N/Avoid LIR_Assembler::membar() {
0N/A // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode
0N/A __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
0N/A}
0N/A
0N/Avoid LIR_Assembler::membar_acquire() {
0N/A // no-op on TSO
0N/A}
0N/A
0N/Avoid LIR_Assembler::membar_release() {
0N/A // no-op on TSO
0N/A}
0N/A
0N/A// Macro to Pack two sequential registers containing 32 bit values
0N/A// into a single 64 bit register.
0N/A// rs and rs->successor() are packed into rd
0N/A// rd and rs may be the same register.
0N/A// Note: rs and rs->successor() are destroyed.
0N/Avoid LIR_Assembler::pack64( Register rs, Register rd ) {
0N/A __ sllx(rs, 32, rs);
0N/A __ srl(rs->successor(), 0, rs->successor());
0N/A __ or3(rs, rs->successor(), rd);
0N/A}
0N/A
0N/A// Macro to unpack a 64 bit value in a register into
0N/A// two sequential registers.
0N/A// rd is unpacked into rd and rd->successor()
0N/Avoid LIR_Assembler::unpack64( Register rd ) {
0N/A __ mov(rd, rd->successor());
0N/A __ srax(rd, 32, rd);
0N/A __ sra(rd->successor(), 0, rd->successor());
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
0N/A LIR_Address* addr = addr_opr->as_address_ptr();
0N/A assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet");
0N/A __ add(addr->base()->as_register(), addr->disp(), dest->as_register());
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::get_thread(LIR_Opr result_reg) {
0N/A assert(result_reg->is_register(), "check");
0N/A __ mov(G2_thread, result_reg->as_register());
0N/A}
0N/A
0N/A
0N/Avoid LIR_Assembler::peephole(LIR_List* lir) {
0N/A LIR_OpList* inst = lir->instructions_list();
0N/A for (int i = 0; i < inst->length(); i++) {
0N/A LIR_Op* op = inst->at(i);
0N/A switch (op->code()) {
0N/A case lir_cond_float_branch:
0N/A case lir_branch: {
0N/A LIR_OpBranch* branch = op->as_OpBranch();
0N/A assert(branch->info() == NULL, "shouldn't be state on branches anymore");
0N/A LIR_Op* delay_op = NULL;
0N/A // we'd like to be able to pull following instructions into
0N/A // this slot but we don't know enough to do it safely yet so
0N/A // only optimize block to block control flow.
0N/A if (LIRFillDelaySlots && branch->block()) {
0N/A LIR_Op* prev = inst->at(i - 1);
0N/A if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) {
0N/A // swap previous instruction into delay slot
0N/A inst->at_put(i - 1, op);
0N/A inst->at_put(i, new LIR_OpDelay(prev, op->info()));
0N/A#ifndef PRODUCT
0N/A if (LIRTracePeephole) {
0N/A tty->print_cr("delayed");
0N/A inst->at(i - 1)->print();
0N/A inst->at(i)->print();
0N/A }
0N/A#endif
0N/A continue;
0N/A }
0N/A }
0N/A
0N/A if (!delay_op) {
0N/A delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL);
0N/A }
0N/A inst->insert_before(i + 1, delay_op);
0N/A break;
0N/A }
0N/A case lir_static_call:
0N/A case lir_virtual_call:
0N/A case lir_icvirtual_call:
0N/A case lir_optvirtual_call: {
0N/A LIR_Op* delay_op = NULL;
0N/A LIR_Op* prev = inst->at(i - 1);
0N/A if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL &&
0N/A (op->code() != lir_virtual_call ||
0N/A !prev->result_opr()->is_single_cpu() ||
0N/A prev->result_opr()->as_register() != O0) &&
0N/A LIR_Assembler::is_single_instruction(prev)) {
0N/A // Only moves without info can be put into the delay slot.
0N/A // Also don't allow the setup of the receiver in the delay
0N/A // slot for vtable calls.
0N/A inst->at_put(i - 1, op);
0N/A inst->at_put(i, new LIR_OpDelay(prev, op->info()));
0N/A#ifndef PRODUCT
0N/A if (LIRTracePeephole) {
0N/A tty->print_cr("delayed");
0N/A inst->at(i - 1)->print();
0N/A inst->at(i)->print();
0N/A }
0N/A#endif
0N/A continue;
0N/A }
0N/A
0N/A if (!delay_op) {
0N/A delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info());
0N/A inst->insert_before(i + 1, delay_op);
0N/A }
0N/A break;
0N/A }
0N/A }
0N/A }
0N/A}
0N/A
0N/A
0N/A
0N/A
0N/A#undef __