assembler_sparc.hpp revision 0
0N/A/*
0N/A * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved.
0N/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
0N/A *
0N/A * This code is free software; you can redistribute it and/or modify it
0N/A * under the terms of the GNU General Public License version 2 only, as
0N/A * published by the Free Software Foundation.
0N/A *
0N/A * This code is distributed in the hope that it will be useful, but WITHOUT
0N/A * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
0N/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
0N/A * version 2 for more details (a copy is included in the LICENSE file that
0N/A * accompanied this code).
0N/A *
0N/A * You should have received a copy of the GNU General Public License version
0N/A * 2 along with this work; if not, write to the Free Software Foundation,
0N/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
0N/A *
0N/A * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
0N/A * CA 95054 USA or visit www.sun.com if you need additional information or
0N/A * have any questions.
0N/A *
0N/A */
0N/A
0N/Aclass BiasedLockingCounters;
0N/A
0N/A// <sys/trap.h> promises that the system will not use traps 16-31
0N/A#define ST_RESERVED_FOR_USER_0 0x10
0N/A
0N/A/* Written: David Ungar 4/19/97 */
0N/A
0N/A// Contains all the definitions needed for sparc assembly code generation.
0N/A
0N/A// Register aliases for parts of the system:
0N/A
0N/A// 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe
0N/A// across context switches in V8+ ABI. Of course, there are no 64 bit regs
0N/A// in V8 ABI. All 64 bits are preserved in V9 ABI for all registers.
0N/A
0N/A// g2-g4 are scratch registers called "application globals". Their
0N/A// meaning is reserved to the "compilation system"--which means us!
0N/A// They are are not supposed to be touched by ordinary C code, although
0N/A// highly-optimized C code might steal them for temps. They are safe
0N/A// across thread switches, and the ABI requires that they be safe
0N/A// across function calls.
0N/A//
0N/A// g1 and g3 are touched by more modules. V8 allows g1 to be clobbered
0N/A// across func calls, and V8+ also allows g5 to be clobbered across
0N/A// func calls. Also, g1 and g5 can get touched while doing shared
0N/A// library loading.
0N/A//
0N/A// We must not touch g7 (it is the thread-self register) and g6 is
0N/A// reserved for certain tools. g0, of course, is always zero.
0N/A//
0N/A// (Sources: SunSoft Compilers Group, thread library engineers.)
0N/A
0N/A// %%%% The interpreter should be revisited to reduce global scratch regs.
0N/A
0N/A// This global always holds the current JavaThread pointer:
0N/A
0N/AREGISTER_DECLARATION(Register, G2_thread , G2);
0N/A
0N/A// The following globals are part of the Java calling convention:
0N/A
0N/AREGISTER_DECLARATION(Register, G5_method , G5);
0N/AREGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method);
0N/AREGISTER_DECLARATION(Register, G5_inline_cache_reg , G5_method);
0N/A
0N/A// The following globals are used for the new C1 & interpreter calling convention:
0N/AREGISTER_DECLARATION(Register, Gargs , G4); // pointing to the last argument
0N/A
0N/A// This local is used to preserve G2_thread in the interpreter and in stubs:
0N/AREGISTER_DECLARATION(Register, L7_thread_cache , L7);
0N/A
0N/A// These globals are used as scratch registers in the interpreter:
0N/A
0N/AREGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch
0N/AREGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME
0N/AREGISTER_DECLARATION(Register, G3_scratch , G3);
0N/AREGISTER_DECLARATION(Register, G4_scratch , G4);
0N/A
0N/A// These globals are used as short-lived scratch registers in the compiler:
0N/A
0N/AREGISTER_DECLARATION(Register, Gtemp , G5);
0N/A
0N/A// The compiler requires that G5_megamorphic_method is G5_inline_cache_klass,
0N/A// because a single patchable "set" instruction (NativeMovConstReg,
0N/A// or NativeMovConstPatching for compiler1) instruction
0N/A// serves to set up either quantity, depending on whether the compiled
0N/A// call site is an inline cache or is megamorphic. See the function
0N/A// CompiledIC::set_to_megamorphic.
0N/A//
0N/A// On the other hand, G5_inline_cache_klass must differ from G5_method,
0N/A// because both registers are needed for an inline cache that calls
0N/A// an interpreted method.
0N/A//
0N/A// Note that G5_method is only the method-self for the interpreter,
0N/A// and is logically unrelated to G5_megamorphic_method.
0N/A//
0N/A// Invariants on G2_thread (the JavaThread pointer):
0N/A// - it should not be used for any other purpose anywhere
0N/A// - it must be re-initialized by StubRoutines::call_stub()
0N/A// - it must be preserved around every use of call_VM
0N/A
0N/A// We can consider using g2/g3/g4 to cache more values than the
0N/A// JavaThread, such as the card-marking base or perhaps pointers into
0N/A// Eden. It's something of a waste to use them as scratch temporaries,
0N/A// since they are not supposed to be volatile. (Of course, if we find
0N/A// that Java doesn't benefit from application globals, then we can just
0N/A// use them as ordinary temporaries.)
0N/A//
0N/A// Since g1 and g5 (and/or g6) are the volatile (caller-save) registers,
0N/A// it makes sense to use them routinely for procedure linkage,
0N/A// whenever the On registers are not applicable. Examples: G5_method,
0N/A// G5_inline_cache_klass, and a double handful of miscellaneous compiler
0N/A// stubs. This means that compiler stubs, etc., should be kept to a
0N/A// maximum of two or three G-register arguments.
0N/A
0N/A
0N/A// stub frames
0N/A
0N/AREGISTER_DECLARATION(Register, Lentry_args , L0); // pointer to args passed to callee (interpreter) not stub itself
0N/A
0N/A// Interpreter frames
0N/A
0N/A#ifdef CC_INTERP
0N/AREGISTER_DECLARATION(Register, Lstate , L0); // interpreter state object pointer
0N/AREGISTER_DECLARATION(Register, L1_scratch , L1); // scratch
0N/AREGISTER_DECLARATION(Register, Lmirror , L1); // mirror (for native methods only)
0N/AREGISTER_DECLARATION(Register, L2_scratch , L2);
0N/AREGISTER_DECLARATION(Register, L3_scratch , L3);
0N/AREGISTER_DECLARATION(Register, L4_scratch , L4);
0N/AREGISTER_DECLARATION(Register, Lscratch , L5); // C1 uses
0N/AREGISTER_DECLARATION(Register, Lscratch2 , L6); // C1 uses
0N/AREGISTER_DECLARATION(Register, L7_scratch , L7); // constant pool cache
0N/AREGISTER_DECLARATION(Register, O5_savedSP , O5);
0N/AREGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply
0N/A // a copy SP, so in 64-bit it's a biased value. The bias
0N/A // is added and removed as needed in the frame code.
0N/A// Interface to signature handler
0N/AREGISTER_DECLARATION(Register, Llocals , L7); // pointer to locals for signature handler
0N/AREGISTER_DECLARATION(Register, Lmethod , L6); // methodOop when calling signature handler
0N/A
0N/A#else
0N/AREGISTER_DECLARATION(Register, Lesp , L0); // expression stack pointer
0N/AREGISTER_DECLARATION(Register, Lbcp , L1); // pointer to next bytecode
0N/AREGISTER_DECLARATION(Register, Lmethod , L2);
0N/AREGISTER_DECLARATION(Register, Llocals , L3);
0N/AREGISTER_DECLARATION(Register, Largs , L3); // pointer to locals for signature handler
0N/A // must match Llocals in asm interpreter
0N/AREGISTER_DECLARATION(Register, Lmonitors , L4);
0N/AREGISTER_DECLARATION(Register, Lbyte_code , L5);
0N/A// When calling out from the interpreter we record SP so that we can remove any extra stack
0N/A// space allocated during adapter transitions. This register is only live from the point
0N/A// of the call until we return.
0N/AREGISTER_DECLARATION(Register, Llast_SP , L5);
0N/AREGISTER_DECLARATION(Register, Lscratch , L5);
0N/AREGISTER_DECLARATION(Register, Lscratch2 , L6);
0N/AREGISTER_DECLARATION(Register, LcpoolCache , L6); // constant pool cache
0N/A
0N/AREGISTER_DECLARATION(Register, O5_savedSP , O5);
0N/AREGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply
0N/A // a copy SP, so in 64-bit it's a biased value. The bias
0N/A // is added and removed as needed in the frame code.
0N/AREGISTER_DECLARATION(Register, IdispatchTables , I4); // Base address of the bytecode dispatch tables
0N/AREGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode
0N/AREGISTER_DECLARATION(Register, ImethodDataPtr , I2); // Pointer to the current method data
0N/A#endif /* CC_INTERP */
0N/A
0N/A// NOTE: Lscratch2 and LcpoolCache point to the same registers in
0N/A// the interpreter code. If Lscratch2 needs to be used for some
0N/A// purpose than LcpoolCache should be restore after that for
0N/A// the interpreter to work right
0N/A// (These assignments must be compatible with L7_thread_cache; see above.)
0N/A
0N/A// Since Lbcp points into the middle of the method object,
0N/A// it is temporarily converted into a "bcx" during GC.
0N/A
0N/A// Exception processing
0N/A// These registers are passed into exception handlers.
0N/A// All exception handlers require the exception object being thrown.
0N/A// In addition, an nmethod's exception handler must be passed
0N/A// the address of the call site within the nmethod, to allow
0N/A// proper selection of the applicable catch block.
0N/A// (Interpreter frames use their own bcp() for this purpose.)
0N/A//
0N/A// The Oissuing_pc value is not always needed. When jumping to a
0N/A// handler that is known to be interpreted, the Oissuing_pc value can be
0N/A// omitted. An actual catch block in compiled code receives (from its
0N/A// nmethod's exception handler) the thrown exception in the Oexception,
0N/A// but it doesn't need the Oissuing_pc.
0N/A//
0N/A// If an exception handler (either interpreted or compiled)
0N/A// discovers there is no applicable catch block, it updates
0N/A// the Oissuing_pc to the continuation PC of its own caller,
0N/A// pops back to that caller's stack frame, and executes that
0N/A// caller's exception handler. Obviously, this process will
0N/A// iterate until the control stack is popped back to a method
0N/A// containing an applicable catch block. A key invariant is
0N/A// that the Oissuing_pc value is always a value local to
0N/A// the method whose exception handler is currently executing.
0N/A//
0N/A// Note: The issuing PC value is __not__ a raw return address (I7 value).
0N/A// It is a "return pc", the address __following__ the call.
0N/A// Raw return addresses are converted to issuing PCs by frame::pc(),
0N/A// or by stubs. Issuing PCs can be used directly with PC range tables.
0N/A//
0N/AREGISTER_DECLARATION(Register, Oexception , O0); // exception being thrown
0N/AREGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from
0N/A
0N/A
0N/A// These must occur after the declarations above
0N/A#ifndef DONT_USE_REGISTER_DEFINES
0N/A
0N/A#define Gthread AS_REGISTER(Register, Gthread)
0N/A#define Gmethod AS_REGISTER(Register, Gmethod)
0N/A#define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method)
0N/A#define Ginline_cache_reg AS_REGISTER(Register, Ginline_cache_reg)
0N/A#define Gargs AS_REGISTER(Register, Gargs)
0N/A#define Lthread_cache AS_REGISTER(Register, Lthread_cache)
0N/A#define Gframe_size AS_REGISTER(Register, Gframe_size)
0N/A#define Gtemp AS_REGISTER(Register, Gtemp)
0N/A
0N/A#ifdef CC_INTERP
0N/A#define Lstate AS_REGISTER(Register, Lstate)
0N/A#define Lesp AS_REGISTER(Register, Lesp)
0N/A#define L1_scratch AS_REGISTER(Register, L1_scratch)
0N/A#define Lmirror AS_REGISTER(Register, Lmirror)
0N/A#define L2_scratch AS_REGISTER(Register, L2_scratch)
0N/A#define L3_scratch AS_REGISTER(Register, L3_scratch)
0N/A#define L4_scratch AS_REGISTER(Register, L4_scratch)
0N/A#define Lscratch AS_REGISTER(Register, Lscratch)
0N/A#define Lscratch2 AS_REGISTER(Register, Lscratch2)
0N/A#define L7_scratch AS_REGISTER(Register, L7_scratch)
0N/A#define Ostate AS_REGISTER(Register, Ostate)
0N/A#else
0N/A#define Lesp AS_REGISTER(Register, Lesp)
0N/A#define Lbcp AS_REGISTER(Register, Lbcp)
0N/A#define Lmethod AS_REGISTER(Register, Lmethod)
0N/A#define Llocals AS_REGISTER(Register, Llocals)
0N/A#define Lmonitors AS_REGISTER(Register, Lmonitors)
0N/A#define Lbyte_code AS_REGISTER(Register, Lbyte_code)
0N/A#define Lscratch AS_REGISTER(Register, Lscratch)
0N/A#define Lscratch2 AS_REGISTER(Register, Lscratch2)
0N/A#define LcpoolCache AS_REGISTER(Register, LcpoolCache)
0N/A#endif /* ! CC_INTERP */
0N/A
0N/A#define Lentry_args AS_REGISTER(Register, Lentry_args)
0N/A#define I5_savedSP AS_REGISTER(Register, I5_savedSP)
0N/A#define O5_savedSP AS_REGISTER(Register, O5_savedSP)
0N/A#define IdispatchAddress AS_REGISTER(Register, IdispatchAddress)
0N/A#define ImethodDataPtr AS_REGISTER(Register, ImethodDataPtr)
0N/A#define IdispatchTables AS_REGISTER(Register, IdispatchTables)
0N/A
0N/A#define Oexception AS_REGISTER(Register, Oexception)
0N/A#define Oissuing_pc AS_REGISTER(Register, Oissuing_pc)
0N/A
0N/A
0N/A#endif
0N/A
0N/A// Address is an abstraction used to represent a memory location.
0N/A//
0N/A// Note: A register location is represented via a Register, not
0N/A// via an address for efficiency & simplicity reasons.
0N/A
0N/Aclass Address VALUE_OBJ_CLASS_SPEC {
0N/A private:
0N/A Register _base;
0N/A#ifdef _LP64
0N/A int _hi32; // bits 63::32
0N/A int _low32; // bits 31::0
0N/A#endif
0N/A int _hi;
0N/A int _disp;
0N/A RelocationHolder _rspec;
0N/A
0N/A RelocationHolder rspec_from_rtype(relocInfo::relocType rt, address a = NULL) {
0N/A switch (rt) {
0N/A case relocInfo::external_word_type:
0N/A return external_word_Relocation::spec(a);
0N/A case relocInfo::internal_word_type:
0N/A return internal_word_Relocation::spec(a);
0N/A#ifdef _LP64
0N/A case relocInfo::opt_virtual_call_type:
0N/A return opt_virtual_call_Relocation::spec();
0N/A case relocInfo::static_call_type:
0N/A return static_call_Relocation::spec();
0N/A case relocInfo::runtime_call_type:
0N/A return runtime_call_Relocation::spec();
0N/A#endif
0N/A case relocInfo::none:
0N/A return RelocationHolder();
0N/A default:
0N/A ShouldNotReachHere();
0N/A return RelocationHolder();
0N/A }
0N/A }
0N/A
0N/A public:
0N/A Address(Register b, address a, relocInfo::relocType rt = relocInfo::none)
0N/A : _rspec(rspec_from_rtype(rt, a))
0N/A {
0N/A _base = b;
0N/A#ifdef _LP64
0N/A _hi32 = (intptr_t)a >> 32; // top 32 bits in 64 bit word
0N/A _low32 = (intptr_t)a & ~0; // low 32 bits in 64 bit word
0N/A#endif
0N/A _hi = (intptr_t)a & ~0x3ff; // top 22 bits in low word
0N/A _disp = (intptr_t)a & 0x3ff; // bottom 10 bits
0N/A }
0N/A
0N/A Address(Register b, address a, RelocationHolder const& rspec)
0N/A : _rspec(rspec)
0N/A {
0N/A _base = b;
0N/A#ifdef _LP64
0N/A _hi32 = (intptr_t)a >> 32; // top 32 bits in 64 bit word
0N/A _low32 = (intptr_t)a & ~0; // low 32 bits in 64 bit word
0N/A#endif
0N/A _hi = (intptr_t)a & ~0x3ff; // top 22 bits
0N/A _disp = (intptr_t)a & 0x3ff; // bottom 10 bits
0N/A }
0N/A
0N/A Address(Register b, intptr_t h, intptr_t d, RelocationHolder const& rspec = RelocationHolder())
0N/A : _rspec(rspec)
0N/A {
0N/A _base = b;
0N/A#ifdef _LP64
0N/A// [RGV] Put in Assert to force me to check usage of this constructor
0N/A assert( h == 0, "Check usage of this constructor" );
0N/A _hi32 = h;
0N/A _low32 = d;
0N/A _hi = h;
0N/A _disp = d;
0N/A#else
0N/A _hi = h;
0N/A _disp = d;
0N/A#endif
0N/A }
0N/A
0N/A Address()
0N/A : _rspec(RelocationHolder())
0N/A {
0N/A _base = G0;
0N/A#ifdef _LP64
0N/A _hi32 = 0;
0N/A _low32 = 0;
0N/A#endif
0N/A _hi = 0;
0N/A _disp = 0;
0N/A }
0N/A
0N/A // fancier constructors
0N/A
0N/A enum addr_type {
0N/A extra_in_argument, // in the In registers
0N/A extra_out_argument // in the Outs
0N/A };
0N/A
0N/A Address( addr_type, int );
0N/A
0N/A // accessors
0N/A
0N/A Register base() const { return _base; }
0N/A#ifdef _LP64
0N/A int hi32() const { return _hi32; }
0N/A int low32() const { return _low32; }
0N/A#endif
0N/A int hi() const { return _hi; }
0N/A int disp() const { return _disp; }
0N/A#ifdef _LP64
0N/A intptr_t value() const { return ((intptr_t)_hi32 << 32) |
0N/A (intptr_t)(uint32_t)_low32; }
0N/A#else
0N/A int value() const { return _hi | _disp; }
0N/A#endif
0N/A const relocInfo::relocType rtype() { return _rspec.type(); }
0N/A const RelocationHolder& rspec() { return _rspec; }
0N/A
0N/A RelocationHolder rspec(int offset) const {
0N/A return offset == 0 ? _rspec : _rspec.plus(offset);
0N/A }
0N/A
0N/A inline bool is_simm13(int offset = 0); // check disp+offset for overflow
0N/A
0N/A Address split_disp() const { // deal with disp overflow
0N/A Address a = (*this);
0N/A int hi_disp = _disp & ~0x3ff;
0N/A if (hi_disp != 0) {
0N/A a._disp -= hi_disp;
0N/A a._hi += hi_disp;
0N/A }
0N/A return a;
0N/A }
0N/A
0N/A Address after_save() const {
0N/A Address a = (*this);
0N/A a._base = a._base->after_save();
0N/A return a;
0N/A }
0N/A
0N/A Address after_restore() const {
0N/A Address a = (*this);
0N/A a._base = a._base->after_restore();
0N/A return a;
0N/A }
0N/A
0N/A friend class Assembler;
0N/A};
0N/A
0N/A
0N/Ainline Address RegisterImpl::address_in_saved_window() const {
0N/A return (Address(SP, 0, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS));
0N/A}
0N/A
0N/A
0N/A
0N/A// Argument is an abstraction used to represent an outgoing
0N/A// actual argument or an incoming formal parameter, whether
0N/A// it resides in memory or in a register, in a manner consistent
0N/A// with the SPARC Application Binary Interface, or ABI. This is
0N/A// often referred to as the native or C calling convention.
0N/A
0N/Aclass Argument VALUE_OBJ_CLASS_SPEC {
0N/A private:
0N/A int _number;
0N/A bool _is_in;
0N/A
0N/A public:
0N/A#ifdef _LP64
0N/A enum {
0N/A n_register_parameters = 6, // only 6 registers may contain integer parameters
0N/A n_float_register_parameters = 16 // Can have up to 16 floating registers
0N/A };
0N/A#else
0N/A enum {
0N/A n_register_parameters = 6 // only 6 registers may contain integer parameters
0N/A };
0N/A#endif
0N/A
0N/A // creation
0N/A Argument(int number, bool is_in) : _number(number), _is_in(is_in) {}
0N/A
0N/A int number() const { return _number; }
0N/A bool is_in() const { return _is_in; }
0N/A bool is_out() const { return !is_in(); }
0N/A
0N/A Argument successor() const { return Argument(number() + 1, is_in()); }
0N/A Argument as_in() const { return Argument(number(), true ); }
0N/A Argument as_out() const { return Argument(number(), false); }
0N/A
0N/A // locating register-based arguments:
0N/A bool is_register() const { return _number < n_register_parameters; }
0N/A
0N/A#ifdef _LP64
0N/A // locating Floating Point register-based arguments:
0N/A bool is_float_register() const { return _number < n_float_register_parameters; }
0N/A
0N/A FloatRegister as_float_register() const {
0N/A assert(is_float_register(), "must be a register argument");
0N/A return as_FloatRegister(( number() *2 ) + 1);
0N/A }
0N/A FloatRegister as_double_register() const {
0N/A assert(is_float_register(), "must be a register argument");
0N/A return as_FloatRegister(( number() *2 ));
0N/A }
0N/A#endif
0N/A
0N/A Register as_register() const {
0N/A assert(is_register(), "must be a register argument");
0N/A return is_in() ? as_iRegister(number()) : as_oRegister(number());
0N/A }
0N/A
0N/A // locating memory-based arguments
0N/A Address as_address() const {
0N/A assert(!is_register(), "must be a memory argument");
0N/A return address_in_frame();
0N/A }
0N/A
0N/A // When applied to a register-based argument, give the corresponding address
0N/A // into the 6-word area "into which callee may store register arguments"
0N/A // (This is a different place than the corresponding register-save area location.)
0N/A Address address_in_frame() const {
0N/A return Address( is_in() ? Address::extra_in_argument
0N/A : Address::extra_out_argument,
0N/A _number );
0N/A }
0N/A
0N/A // debugging
0N/A const char* name() const;
0N/A
0N/A friend class Assembler;
0N/A};
0N/A
0N/A
0N/A// The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
0N/A// level; i.e., what you write
0N/A// is what you get. The Assembler is generating code into a CodeBuffer.
0N/A
0N/Aclass Assembler : public AbstractAssembler {
0N/A protected:
0N/A
0N/A static void print_instruction(int inst);
0N/A static int patched_branch(int dest_pos, int inst, int inst_pos);
0N/A static int branch_destination(int inst, int pos);
0N/A
0N/A
0N/A friend class AbstractAssembler;
0N/A
0N/A // code patchers need various routines like inv_wdisp()
0N/A friend class NativeInstruction;
0N/A friend class NativeGeneralJump;
0N/A friend class Relocation;
0N/A friend class Label;
0N/A
0N/A public:
0N/A // op carries format info; see page 62 & 267
0N/A
0N/A enum ops {
0N/A call_op = 1, // fmt 1
0N/A branch_op = 0, // also sethi (fmt2)
0N/A arith_op = 2, // fmt 3, arith & misc
0N/A ldst_op = 3 // fmt 3, load/store
0N/A };
0N/A
0N/A enum op2s {
0N/A bpr_op2 = 3,
0N/A fb_op2 = 6,
0N/A fbp_op2 = 5,
0N/A br_op2 = 2,
0N/A bp_op2 = 1,
0N/A cb_op2 = 7, // V8
0N/A sethi_op2 = 4
0N/A };
0N/A
0N/A enum op3s {
0N/A // selected op3s
0N/A add_op3 = 0x00,
0N/A and_op3 = 0x01,
0N/A or_op3 = 0x02,
0N/A xor_op3 = 0x03,
0N/A sub_op3 = 0x04,
0N/A andn_op3 = 0x05,
0N/A orn_op3 = 0x06,
0N/A xnor_op3 = 0x07,
0N/A addc_op3 = 0x08,
0N/A mulx_op3 = 0x09,
0N/A umul_op3 = 0x0a,
0N/A smul_op3 = 0x0b,
0N/A subc_op3 = 0x0c,
0N/A udivx_op3 = 0x0d,
0N/A udiv_op3 = 0x0e,
0N/A sdiv_op3 = 0x0f,
0N/A
0N/A addcc_op3 = 0x10,
0N/A andcc_op3 = 0x11,
0N/A orcc_op3 = 0x12,
0N/A xorcc_op3 = 0x13,
0N/A subcc_op3 = 0x14,
0N/A andncc_op3 = 0x15,
0N/A orncc_op3 = 0x16,
0N/A xnorcc_op3 = 0x17,
0N/A addccc_op3 = 0x18,
0N/A umulcc_op3 = 0x1a,
0N/A smulcc_op3 = 0x1b,
0N/A subccc_op3 = 0x1c,
0N/A udivcc_op3 = 0x1e,
0N/A sdivcc_op3 = 0x1f,
0N/A
0N/A taddcc_op3 = 0x20,
0N/A tsubcc_op3 = 0x21,
0N/A taddcctv_op3 = 0x22,
0N/A tsubcctv_op3 = 0x23,
0N/A mulscc_op3 = 0x24,
0N/A sll_op3 = 0x25,
0N/A sllx_op3 = 0x25,
0N/A srl_op3 = 0x26,
0N/A srlx_op3 = 0x26,
0N/A sra_op3 = 0x27,
0N/A srax_op3 = 0x27,
0N/A rdreg_op3 = 0x28,
0N/A membar_op3 = 0x28,
0N/A
0N/A flushw_op3 = 0x2b,
0N/A movcc_op3 = 0x2c,
0N/A sdivx_op3 = 0x2d,
0N/A popc_op3 = 0x2e,
0N/A movr_op3 = 0x2f,
0N/A
0N/A sir_op3 = 0x30,
0N/A wrreg_op3 = 0x30,
0N/A saved_op3 = 0x31,
0N/A
0N/A fpop1_op3 = 0x34,
0N/A fpop2_op3 = 0x35,
0N/A impdep1_op3 = 0x36,
0N/A impdep2_op3 = 0x37,
0N/A jmpl_op3 = 0x38,
0N/A rett_op3 = 0x39,
0N/A trap_op3 = 0x3a,
0N/A flush_op3 = 0x3b,
0N/A save_op3 = 0x3c,
0N/A restore_op3 = 0x3d,
0N/A done_op3 = 0x3e,
0N/A retry_op3 = 0x3e,
0N/A
0N/A lduw_op3 = 0x00,
0N/A ldub_op3 = 0x01,
0N/A lduh_op3 = 0x02,
0N/A ldd_op3 = 0x03,
0N/A stw_op3 = 0x04,
0N/A stb_op3 = 0x05,
0N/A sth_op3 = 0x06,
0N/A std_op3 = 0x07,
0N/A ldsw_op3 = 0x08,
0N/A ldsb_op3 = 0x09,
0N/A ldsh_op3 = 0x0a,
0N/A ldx_op3 = 0x0b,
0N/A
0N/A ldstub_op3 = 0x0d,
0N/A stx_op3 = 0x0e,
0N/A swap_op3 = 0x0f,
0N/A
0N/A lduwa_op3 = 0x10,
0N/A ldxa_op3 = 0x1b,
0N/A
0N/A stwa_op3 = 0x14,
0N/A stxa_op3 = 0x1e,
0N/A
0N/A ldf_op3 = 0x20,
0N/A ldfsr_op3 = 0x21,
0N/A ldqf_op3 = 0x22,
0N/A lddf_op3 = 0x23,
0N/A stf_op3 = 0x24,
0N/A stfsr_op3 = 0x25,
0N/A stqf_op3 = 0x26,
0N/A stdf_op3 = 0x27,
0N/A
0N/A prefetch_op3 = 0x2d,
0N/A
0N/A
0N/A ldc_op3 = 0x30,
0N/A ldcsr_op3 = 0x31,
0N/A lddc_op3 = 0x33,
0N/A stc_op3 = 0x34,
0N/A stcsr_op3 = 0x35,
0N/A stdcq_op3 = 0x36,
0N/A stdc_op3 = 0x37,
0N/A
0N/A casa_op3 = 0x3c,
0N/A casxa_op3 = 0x3e,
0N/A
0N/A alt_bit_op3 = 0x10,
0N/A cc_bit_op3 = 0x10
0N/A };
0N/A
0N/A enum opfs {
0N/A // selected opfs
0N/A fmovs_opf = 0x01,
0N/A fmovd_opf = 0x02,
0N/A
0N/A fnegs_opf = 0x05,
0N/A fnegd_opf = 0x06,
0N/A
0N/A fadds_opf = 0x41,
0N/A faddd_opf = 0x42,
0N/A fsubs_opf = 0x45,
0N/A fsubd_opf = 0x46,
0N/A
0N/A fmuls_opf = 0x49,
0N/A fmuld_opf = 0x4a,
0N/A fdivs_opf = 0x4d,
0N/A fdivd_opf = 0x4e,
0N/A
0N/A fcmps_opf = 0x51,
0N/A fcmpd_opf = 0x52,
0N/A
0N/A fstox_opf = 0x81,
0N/A fdtox_opf = 0x82,
0N/A fxtos_opf = 0x84,
0N/A fxtod_opf = 0x88,
0N/A fitos_opf = 0xc4,
0N/A fdtos_opf = 0xc6,
0N/A fitod_opf = 0xc8,
0N/A fstod_opf = 0xc9,
0N/A fstoi_opf = 0xd1,
0N/A fdtoi_opf = 0xd2
0N/A };
0N/A
0N/A enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7 };
0N/A
0N/A enum Condition {
0N/A // for FBfcc & FBPfcc instruction
0N/A f_never = 0,
0N/A f_notEqual = 1,
0N/A f_notZero = 1,
0N/A f_lessOrGreater = 2,
0N/A f_unorderedOrLess = 3,
0N/A f_less = 4,
0N/A f_unorderedOrGreater = 5,
0N/A f_greater = 6,
0N/A f_unordered = 7,
0N/A f_always = 8,
0N/A f_equal = 9,
0N/A f_zero = 9,
0N/A f_unorderedOrEqual = 10,
0N/A f_greaterOrEqual = 11,
0N/A f_unorderedOrGreaterOrEqual = 12,
0N/A f_lessOrEqual = 13,
0N/A f_unorderedOrLessOrEqual = 14,
0N/A f_ordered = 15,
0N/A
0N/A // V8 coproc, pp 123 v8 manual
0N/A
0N/A cp_always = 8,
0N/A cp_never = 0,
0N/A cp_3 = 7,
0N/A cp_2 = 6,
0N/A cp_2or3 = 5,
0N/A cp_1 = 4,
0N/A cp_1or3 = 3,
0N/A cp_1or2 = 2,
0N/A cp_1or2or3 = 1,
0N/A cp_0 = 9,
0N/A cp_0or3 = 10,
0N/A cp_0or2 = 11,
0N/A cp_0or2or3 = 12,
0N/A cp_0or1 = 13,
0N/A cp_0or1or3 = 14,
0N/A cp_0or1or2 = 15,
0N/A
0N/A
0N/A // for integers
0N/A
0N/A never = 0,
0N/A equal = 1,
0N/A zero = 1,
0N/A lessEqual = 2,
0N/A less = 3,
0N/A lessEqualUnsigned = 4,
0N/A lessUnsigned = 5,
0N/A carrySet = 5,
0N/A negative = 6,
0N/A overflowSet = 7,
0N/A always = 8,
0N/A notEqual = 9,
0N/A notZero = 9,
0N/A greater = 10,
0N/A greaterEqual = 11,
0N/A greaterUnsigned = 12,
0N/A greaterEqualUnsigned = 13,
0N/A carryClear = 13,
0N/A positive = 14,
0N/A overflowClear = 15
0N/A };
0N/A
0N/A enum CC {
0N/A icc = 0, xcc = 2,
0N/A // ptr_cc is the correct condition code for a pointer or intptr_t:
0N/A ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),
0N/A fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3
0N/A };
0N/A
0N/A enum PrefetchFcn {
0N/A severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
0N/A };
0N/A
0N/A public:
0N/A // Helper functions for groups of instructions
0N/A
0N/A enum Predict { pt = 1, pn = 0 }; // pt = predict taken
0N/A
0N/A enum Membar_mask_bits { // page 184, v9
0N/A StoreStore = 1 << 3,
0N/A LoadStore = 1 << 2,
0N/A StoreLoad = 1 << 1,
0N/A LoadLoad = 1 << 0,
0N/A
0N/A Sync = 1 << 6,
0N/A MemIssue = 1 << 5,
0N/A Lookaside = 1 << 4
0N/A };
0N/A
0N/A // test if x is within signed immediate range for nbits
0N/A static bool is_simm(int x, int nbits) { return -( 1 << nbits-1 ) <= x && x < ( 1 << nbits-1 ); }
0N/A
0N/A // test if -4096 <= x <= 4095
0N/A static bool is_simm13(int x) { return is_simm(x, 13); }
0N/A
0N/A enum ASIs { // page 72, v9
0N/A ASI_PRIMARY = 0x80,
0N/A ASI_PRIMARY_LITTLE = 0x88
0N/A // add more from book as needed
0N/A };
0N/A
0N/A protected:
0N/A // helpers
0N/A
0N/A // x is supposed to fit in a field "nbits" wide
0N/A // and be sign-extended. Check the range.
0N/A
0N/A static void assert_signed_range(intptr_t x, int nbits) {
0N/A assert( nbits == 32
0N/A || -(1 << nbits-1) <= x && x < ( 1 << nbits-1),
0N/A "value out of range");
0N/A }
0N/A
0N/A static void assert_signed_word_disp_range(intptr_t x, int nbits) {
0N/A assert( (x & 3) == 0, "not word aligned");
0N/A assert_signed_range(x, nbits + 2);
0N/A }
0N/A
0N/A static void assert_unsigned_const(int x, int nbits) {
0N/A assert( juint(x) < juint(1 << nbits), "unsigned constant out of range");
0N/A }
0N/A
0N/A // fields: note bits numbered from LSB = 0,
0N/A // fields known by inclusive bit range
0N/A
0N/A static int fmask(juint hi_bit, juint lo_bit) {
0N/A assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits");
0N/A return (1 << ( hi_bit-lo_bit + 1 )) - 1;
0N/A }
0N/A
0N/A // inverse of u_field
0N/A
0N/A static int inv_u_field(int x, int hi_bit, int lo_bit) {
0N/A juint r = juint(x) >> lo_bit;
0N/A r &= fmask( hi_bit, lo_bit);
0N/A return int(r);
0N/A }
0N/A
0N/A
0N/A // signed version: extract from field and sign-extend
0N/A
0N/A static int inv_s_field(int x, int hi_bit, int lo_bit) {
0N/A int sign_shift = 31 - hi_bit;
0N/A return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
0N/A }
0N/A
0N/A // given a field that ranges from hi_bit to lo_bit (inclusive,
0N/A // LSB = 0), and an unsigned value for the field,
0N/A // shift it into the field
0N/A
0N/A#ifdef ASSERT
0N/A static int u_field(int x, int hi_bit, int lo_bit) {
0N/A assert( ( x & ~fmask(hi_bit, lo_bit)) == 0,
0N/A "value out of range");
0N/A int r = x << lo_bit;
0N/A assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
0N/A return r;
0N/A }
0N/A#else
0N/A // make sure this is inlined as it will reduce code size significantly
0N/A #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit))
0N/A#endif
0N/A
0N/A static int inv_op( int x ) { return inv_u_field(x, 31, 30); }
0N/A static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }
0N/A static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }
0N/A static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }
0N/A
0N/A static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }
0N/A
0N/A static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); }
0N/A static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
0N/A static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); }
0N/A
0N/A static int op( int x) { return u_field(x, 31, 30); }
0N/A static int rd( Register r) { return u_field(r->encoding(), 29, 25); }
0N/A static int fcn( int x) { return u_field(x, 29, 25); }
0N/A static int op3( int x) { return u_field(x, 24, 19); }
0N/A static int rs1( Register r) { return u_field(r->encoding(), 18, 14); }
0N/A static int rs2( Register r) { return u_field(r->encoding(), 4, 0); }
0N/A static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); }
0N/A static int cond( int x) { return u_field(x, 28, 25); }
0N/A static int cond_mov( int x) { return u_field(x, 17, 14); }
0N/A static int rcond( RCondition x) { return u_field(x, 12, 10); }
0N/A static int op2( int x) { return u_field(x, 24, 22); }
0N/A static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); }
0N/A static int branchcc( CC fcca) { return u_field(fcca, 21, 20); }
0N/A static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); }
0N/A static int imm_asi( int x) { return u_field(x, 12, 5); }
0N/A static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); }
0N/A static int opf_low6( int w) { return u_field(w, 10, 5); }
0N/A static int opf_low5( int w) { return u_field(w, 9, 5); }
0N/A static int trapcc( CC cc) { return u_field(cc, 12, 11); }
0N/A static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
0N/A static int opf( int x) { return u_field(x, 13, 5); }
0N/A
0N/A static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
0N/A static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
0N/A
0N/A static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
0N/A static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
0N/A static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
0N/A
0N/A // some float instructions use this encoding on the op3 field
0N/A static int alt_op3(int op, FloatRegisterImpl::Width w) {
0N/A int r;
0N/A switch(w) {
0N/A case FloatRegisterImpl::S: r = op + 0; break;
0N/A case FloatRegisterImpl::D: r = op + 3; break;
0N/A case FloatRegisterImpl::Q: r = op + 2; break;
0N/A default: ShouldNotReachHere(); break;
0N/A }
0N/A return op3(r);
0N/A }
0N/A
0N/A
0N/A // compute inverse of simm
0N/A static int inv_simm(int x, int nbits) {
0N/A return (int)(x << (32 - nbits)) >> (32 - nbits);
0N/A }
0N/A
0N/A static int inv_simm13( int x ) { return inv_simm(x, 13); }
0N/A
0N/A // signed immediate, in low bits, nbits long
0N/A static int simm(int x, int nbits) {
0N/A assert_signed_range(x, nbits);
0N/A return x & (( 1 << nbits ) - 1);
0N/A }
0N/A
0N/A // compute inverse of wdisp16
0N/A static intptr_t inv_wdisp16(int x, intptr_t pos) {
0N/A int lo = x & (( 1 << 14 ) - 1);
0N/A int hi = (x >> 20) & 3;
0N/A if (hi >= 2) hi |= ~1;
0N/A return (((hi << 14) | lo) << 2) + pos;
0N/A }
0N/A
0N/A // word offset, 14 bits at LSend, 2 bits at B21, B20
0N/A static int wdisp16(intptr_t x, intptr_t off) {
0N/A intptr_t xx = x - off;
0N/A assert_signed_word_disp_range(xx, 16);
0N/A int r = (xx >> 2) & ((1 << 14) - 1)
0N/A | ( ( (xx>>(2+14)) & 3 ) << 20 );
0N/A assert( inv_wdisp16(r, off) == x, "inverse is not inverse");
0N/A return r;
0N/A }
0N/A
0N/A
0N/A // word displacement in low-order nbits bits
0N/A
0N/A static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
0N/A int pre_sign_extend = x & (( 1 << nbits ) - 1);
0N/A int r = pre_sign_extend >= ( 1 << (nbits-1) )
0N/A ? pre_sign_extend | ~(( 1 << nbits ) - 1)
0N/A : pre_sign_extend;
0N/A return (r << 2) + pos;
0N/A }
0N/A
0N/A static int wdisp( intptr_t x, intptr_t off, int nbits ) {
0N/A intptr_t xx = x - off;
0N/A assert_signed_word_disp_range(xx, nbits);
0N/A int r = (xx >> 2) & (( 1 << nbits ) - 1);
0N/A assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse");
0N/A return r;
0N/A }
0N/A
0N/A
0N/A // Extract the top 32 bits in a 64 bit word
0N/A static int32_t hi32( int64_t x ) {
0N/A int32_t r = int32_t( (uint64_t)x >> 32 );
0N/A return r;
0N/A }
0N/A
0N/A // given a sethi instruction, extract the constant, left-justified
0N/A static int inv_hi22( int x ) {
0N/A return x << 10;
0N/A }
0N/A
0N/A // create an imm22 field, given a 32-bit left-justified constant
0N/A static int hi22( int x ) {
0N/A int r = int( juint(x) >> 10 );
0N/A assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'");
0N/A return r;
0N/A }
0N/A
0N/A // create a low10 __value__ (not a field) for a given a 32-bit constant
0N/A static int low10( int x ) {
0N/A return x & ((1 << 10) - 1);
0N/A }
0N/A
0N/A // instruction only in v9
0N/A static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); }
0N/A
0N/A // instruction only in v8
0N/A static void v8_only() { assert( VM_Version::v8_instructions_work(), "This instruction only works on SPARC V8"); }
0N/A
0N/A // instruction deprecated in v9
0N/A static void v9_dep() { } // do nothing for now
0N/A
0N/A // some float instructions only exist for single prec. on v8
0N/A static void v8_s_only(FloatRegisterImpl::Width w) { if (w != FloatRegisterImpl::S) v9_only(); }
0N/A
0N/A // v8 has no CC field
0N/A static void v8_no_cc(CC cc) { if (cc) v9_only(); }
0N/A
0N/A protected:
0N/A // Simple delay-slot scheme:
0N/A // In order to check the programmer, the assembler keeps track of deley slots.
0N/A // It forbids CTIs in delay slots (conservative, but should be OK).
0N/A // Also, when putting an instruction into a delay slot, you must say
0N/A // asm->delayed()->add(...), in order to check that you don't omit
0N/A // delay-slot instructions.
0N/A // To implement this, we use a simple FSA
0N/A
0N/A#ifdef ASSERT
0N/A #define CHECK_DELAY
0N/A#endif
0N/A#ifdef CHECK_DELAY
0N/A enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
0N/A#endif
0N/A
0N/A public:
0N/A // Tells assembler next instruction must NOT be in delay slot.
0N/A // Use at start of multinstruction macros.
0N/A void assert_not_delayed() {
0N/A // This is a separate overloading to avoid creation of string constants
0N/A // in non-asserted code--with some compilers this pollutes the object code.
0N/A#ifdef CHECK_DELAY
0N/A assert_not_delayed("next instruction should not be a delay slot");
0N/A#endif
0N/A }
0N/A void assert_not_delayed(const char* msg) {
0N/A#ifdef CHECK_DELAY
0N/A assert_msg ( delay_state == no_delay, msg);
0N/A#endif
0N/A }
0N/A
0N/A protected:
0N/A // Delay slot helpers
0N/A // cti is called when emitting control-transfer instruction,
0N/A // BEFORE doing the emitting.
0N/A // Only effective when assertion-checking is enabled.
0N/A void cti() {
0N/A#ifdef CHECK_DELAY
0N/A assert_not_delayed("cti should not be in delay slot");
0N/A#endif
0N/A }
0N/A
0N/A // called when emitting cti with a delay slot, AFTER emitting
0N/A void has_delay_slot() {
0N/A#ifdef CHECK_DELAY
0N/A assert_not_delayed("just checking");
0N/A delay_state = at_delay_slot;
0N/A#endif
0N/A }
0N/A
0N/Apublic:
0N/A // Tells assembler you know that next instruction is delayed
0N/A Assembler* delayed() {
0N/A#ifdef CHECK_DELAY
0N/A assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
0N/A delay_state = filling_delay_slot;
0N/A#endif
0N/A return this;
0N/A }
0N/A
0N/A void flush() {
0N/A#ifdef CHECK_DELAY
0N/A assert ( delay_state == no_delay, "ending code with a delay slot");
0N/A#endif
0N/A AbstractAssembler::flush();
0N/A }
0N/A
0N/A inline void emit_long(int); // shadows AbstractAssembler::emit_long
0N/A inline void emit_data(int x) { emit_long(x); }
0N/A inline void emit_data(int, RelocationHolder const&);
0N/A inline void emit_data(int, relocInfo::relocType rtype);
0N/A // helper for above fcns
0N/A inline void check_delay();
0N/A
0N/A
0N/A public:
0N/A // instructions, refer to page numbers in the SPARC Architecture Manual, V9
0N/A
0N/A // pp 135 (addc was addx in v8)
0N/A
0N/A inline void add( Register s1, Register s2, Register d );
0N/A inline void add( Register s1, int simm13a, Register d, relocInfo::relocType rtype = relocInfo::none);
0N/A inline void add( Register s1, int simm13a, Register d, RelocationHolder const& rspec);
0N/A inline void add( const Address& a, Register d, int offset = 0);
0N/A
0N/A void addcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
0N/A void addcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void addc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); }
0N/A void addc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void addccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
0N/A void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A
0N/A // pp 136
0N/A
0N/A inline void bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
0N/A inline void bpr( RCondition c, bool a, Predict p, Register s1, Label& L);
0N/A
0N/A protected: // use MacroAssembler::br instead
0N/A
0N/A // pp 138
0N/A
0N/A inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
0N/A inline void fb( Condition c, bool a, Label& L );
0N/A
0N/A // pp 141
0N/A
0N/A inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
0N/A inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
0N/A
0N/A public:
0N/A
0N/A // pp 144
0N/A
0N/A inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
0N/A inline void br( Condition c, bool a, Label& L );
0N/A
0N/A // pp 146
0N/A
0N/A inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
0N/A inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
0N/A
0N/A // pp 121 (V8)
0N/A
0N/A inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
0N/A inline void cb( Condition c, bool a, Label& L );
0N/A
0N/A // pp 149
0N/A
0N/A inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
0N/A inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
0N/A
0N/A // pp 150
0N/A
0N/A // These instructions compare the contents of s2 with the contents of
0N/A // memory at address in s1. If the values are equal, the contents of memory
0N/A // at address s1 is swapped with the data in d. If the values are not equal,
0N/A // the the contents of memory at s1 is loaded into d, without the swap.
0N/A
0N/A void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
0N/A void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
0N/A
0N/A // pp 152
0N/A
0N/A void udiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); }
0N/A void udiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void sdiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); }
0N/A void sdiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void udivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
0N/A void udivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void sdivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
0N/A void sdivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A
0N/A // pp 155
0N/A
0N/A void done() { v9_only(); cti(); emit_long( op(arith_op) | fcn(0) | op3(done_op3) ); }
0N/A void retry() { v9_only(); cti(); emit_long( op(arith_op) | fcn(1) | op3(retry_op3) ); }
0N/A
0N/A // pp 156
0N/A
0N/A void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); }
0N/A void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); }
0N/A
0N/A // pp 157
0N/A
0N/A void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
0N/A void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
0N/A
0N/A // pp 159
0N/A
0N/A void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
0N/A void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
0N/A
0N/A // pp 160
0N/A
0N/A void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); }
0N/A
0N/A // pp 161
0N/A
0N/A void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, w)); }
0N/A void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, w)); }
0N/A
0N/A // pp 162
0N/A
0N/A void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
0N/A
0N/A void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); }
0N/A
0N/A // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fnegs is the only instruction available
0N/A // on v8 to do negation of single, double and quad precision floats.
0N/A
0N/A void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x05) | fs2(sd, w)); }
0N/A
0N/A void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); }
0N/A
0N/A // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fabss is the only instruction available
0N/A // on v8 to do abs operation on single/double/quad precision floats.
0N/A
0N/A void fabs( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x09) | fs2(sd, w)); }
0N/A
0N/A // pp 163
0N/A
0N/A void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); }
0N/A void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
0N/A void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); }
0N/A
0N/A // pp 164
0N/A
0N/A void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
0N/A
0N/A // pp 165
0N/A
0N/A inline void flush( Register s1, Register s2 );
0N/A inline void flush( Register s1, int simm13a);
0N/A
0N/A // pp 167
0N/A
0N/A void flushw() { v9_only(); emit_long( op(arith_op) | op3(flushw_op3) ); }
0N/A
0N/A // pp 168
0N/A
0N/A void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_long( op(branch_op) | u_field(const22a, 21, 0) ); }
0N/A // v8 unimp == illtrap(0)
0N/A
0N/A // pp 169
0N/A
0N/A void impdep1( int id1, int const19a ) { v9_only(); emit_long( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); }
0N/A void impdep2( int id1, int const19a ) { v9_only(); emit_long( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); }
0N/A
0N/A // pp 149 (v8)
0N/A
0N/A void cpop1( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_long( op(arith_op) | fcn(crd) | op3(impdep1_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
0N/A void cpop2( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_long( op(arith_op) | fcn(crd) | op3(impdep2_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
0N/A
0N/A // pp 170
0N/A
0N/A void jmpl( Register s1, Register s2, Register d );
0N/A void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
0N/A
0N/A inline void jmpl( Address& a, Register d, int offset = 0);
0N/A
0N/A // 171
0N/A
0N/A inline void ldf( FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d );
0N/A inline void ldf( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d );
0N/A
0N/A inline void ldf( FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0);
0N/A
0N/A
0N/A inline void ldfsr( Register s1, Register s2 );
0N/A inline void ldfsr( Register s1, int simm13a);
0N/A inline void ldxfsr( Register s1, Register s2 );
0N/A inline void ldxfsr( Register s1, int simm13a);
0N/A
0N/A // pp 94 (v8)
0N/A
0N/A inline void ldc( Register s1, Register s2, int crd );
0N/A inline void ldc( Register s1, int simm13a, int crd);
0N/A inline void lddc( Register s1, Register s2, int crd );
0N/A inline void lddc( Register s1, int simm13a, int crd);
0N/A inline void ldcsr( Register s1, Register s2, int crd );
0N/A inline void ldcsr( Register s1, int simm13a, int crd);
0N/A
0N/A
0N/A // 173
0N/A
0N/A void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
0N/A void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A
0N/A // pp 175, lduw is ld on v8
0N/A
0N/A inline void ldsb( Register s1, Register s2, Register d );
0N/A inline void ldsb( Register s1, int simm13a, Register d);
0N/A inline void ldsh( Register s1, Register s2, Register d );
0N/A inline void ldsh( Register s1, int simm13a, Register d);
0N/A inline void ldsw( Register s1, Register s2, Register d );
0N/A inline void ldsw( Register s1, int simm13a, Register d);
0N/A inline void ldub( Register s1, Register s2, Register d );
0N/A inline void ldub( Register s1, int simm13a, Register d);
0N/A inline void lduh( Register s1, Register s2, Register d );
0N/A inline void lduh( Register s1, int simm13a, Register d);
0N/A inline void lduw( Register s1, Register s2, Register d );
0N/A inline void lduw( Register s1, int simm13a, Register d);
0N/A inline void ldx( Register s1, Register s2, Register d );
0N/A inline void ldx( Register s1, int simm13a, Register d);
0N/A inline void ld( Register s1, Register s2, Register d );
0N/A inline void ld( Register s1, int simm13a, Register d);
0N/A inline void ldd( Register s1, Register s2, Register d );
0N/A inline void ldd( Register s1, int simm13a, Register d);
0N/A
0N/A inline void ldsb( const Address& a, Register d, int offset = 0 );
0N/A inline void ldsh( const Address& a, Register d, int offset = 0 );
0N/A inline void ldsw( const Address& a, Register d, int offset = 0 );
0N/A inline void ldub( const Address& a, Register d, int offset = 0 );
0N/A inline void lduh( const Address& a, Register d, int offset = 0 );
0N/A inline void lduw( const Address& a, Register d, int offset = 0 );
0N/A inline void ldx( const Address& a, Register d, int offset = 0 );
0N/A inline void ld( const Address& a, Register d, int offset = 0 );
0N/A inline void ldd( const Address& a, Register d, int offset = 0 );
0N/A
0N/A // pp 177
0N/A
0N/A void ldsba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
0N/A void ldsba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void ldsha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
0N/A void ldsha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
0N/A void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void lduba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
0N/A void lduba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void lduha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
0N/A void lduha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void lduwa( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
0N/A void lduwa( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
0N/A void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void ldda( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
0N/A void ldda( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A
0N/A // pp 179
0N/A
0N/A inline void ldstub( Register s1, Register s2, Register d );
0N/A inline void ldstub( Register s1, int simm13a, Register d);
0N/A
0N/A // pp 180
0N/A
0N/A void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
0N/A void ldstuba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A
0N/A // pp 181
0N/A
0N/A void and3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); }
0N/A void and3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void andcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
0N/A void andcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void andn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); }
0N/A void andn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void andncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
0N/A void andncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void or3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
0N/A void or3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void orcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
0N/A void orcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void orn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
0N/A void orn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void orncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
0N/A void orncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void xor3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); }
0N/A void xor3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void xorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
0N/A void xorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void xnor( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); }
0N/A void xnor( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void xnorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
0N/A void xnorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A
0N/A // pp 183
0N/A
0N/A void membar( Membar_mask_bits const7a ) { v9_only(); emit_long( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); }
0N/A
0N/A // pp 185
0N/A
0N/A void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); }
0N/A
0N/A // pp 189
0N/A
0N/A void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); }
0N/A
0N/A // pp 191
0N/A
0N/A void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); }
0N/A void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); }
0N/A
0N/A // pp 195
0N/A
0N/A void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); }
0N/A void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); }
0N/A
0N/A // pp 196
0N/A
0N/A void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); }
0N/A void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
0N/A void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
0N/A void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A
0N/A // pp 197
0N/A
0N/A void umul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); }
0N/A void umul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void smul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); }
0N/A void smul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void umulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
0N/A void umulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void smulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
0N/A void smulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A
0N/A // pp 199
0N/A
0N/A void mulscc( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | rs2(s2) ); }
0N/A void mulscc( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A
0N/A // pp 201
0N/A
0N/A void nop() { emit_long( op(branch_op) | op2(sethi_op2) ); }
0N/A
0N/A
0N/A // pp 202
0N/A
0N/A void popc( Register s, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
0N/A void popc( int simm13a, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
0N/A
0N/A // pp 203
0N/A
0N/A void prefetch( Register s1, Register s2, PrefetchFcn f);
0N/A void prefetch( Register s1, int simm13a, PrefetchFcn f);
0N/A void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
0N/A void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A
0N/A inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0);
0N/A
0N/A // pp 208
0N/A
0N/A // not implementing read privileged register
0N/A
0N/A inline void rdy( Register d) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); }
0N/A inline void rdccr( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); }
0N/A inline void rdasi( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); }
0N/A inline void rdtick( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon!
0N/A inline void rdpc( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); }
0N/A inline void rdfprs( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); }
0N/A
0N/A // pp 213
0N/A
0N/A inline void rett( Register s1, Register s2);
0N/A inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
0N/A
0N/A // pp 214
0N/A
0N/A void save( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); }
0N/A void save( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A
0N/A void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); }
0N/A void restore( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A
0N/A // pp 216
0N/A
0N/A void saved() { v9_only(); emit_long( op(arith_op) | fcn(0) | op3(saved_op3)); }
0N/A void restored() { v9_only(); emit_long( op(arith_op) | fcn(1) | op3(saved_op3)); }
0N/A
0N/A // pp 217
0N/A
0N/A inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
0N/A // pp 218
0N/A
0N/A void sll( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
0N/A void sll( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
0N/A void srl( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
0N/A void srl( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
0N/A void sra( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
0N/A void sra( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
0N/A
0N/A void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
0N/A void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
0N/A void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
0N/A void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
0N/A void srax( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
0N/A void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
0N/A
0N/A // pp 220
0N/A
0N/A void sir( int simm13a ) { emit_long( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); }
0N/A
0N/A // pp 221
0N/A
0N/A void stbar() { emit_long( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); }
0N/A
0N/A // pp 222
0N/A
0N/A inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2 );
0N/A inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
0N/A inline void stf( FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0);
0N/A
0N/A inline void stfsr( Register s1, Register s2 );
0N/A inline void stfsr( Register s1, int simm13a);
0N/A inline void stxfsr( Register s1, Register s2 );
0N/A inline void stxfsr( Register s1, int simm13a);
0N/A
0N/A // pp 224
0N/A
0N/A void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
0N/A void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A
0N/A // p 226
0N/A
0N/A inline void stb( Register d, Register s1, Register s2 );
0N/A inline void stb( Register d, Register s1, int simm13a);
0N/A inline void sth( Register d, Register s1, Register s2 );
0N/A inline void sth( Register d, Register s1, int simm13a);
0N/A inline void stw( Register d, Register s1, Register s2 );
0N/A inline void stw( Register d, Register s1, int simm13a);
0N/A inline void st( Register d, Register s1, Register s2 );
0N/A inline void st( Register d, Register s1, int simm13a);
0N/A inline void stx( Register d, Register s1, Register s2 );
0N/A inline void stx( Register d, Register s1, int simm13a);
0N/A inline void std( Register d, Register s1, Register s2 );
0N/A inline void std( Register d, Register s1, int simm13a);
0N/A
0N/A inline void stb( Register d, const Address& a, int offset = 0 );
0N/A inline void sth( Register d, const Address& a, int offset = 0 );
0N/A inline void stw( Register d, const Address& a, int offset = 0 );
0N/A inline void stx( Register d, const Address& a, int offset = 0 );
0N/A inline void st( Register d, const Address& a, int offset = 0 );
0N/A inline void std( Register d, const Address& a, int offset = 0 );
0N/A
0N/A // pp 177
0N/A
0N/A void stba( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
0N/A void stba( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void stha( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
0N/A void stha( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void stwa( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
0N/A void stwa( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
0N/A void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void stda( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
0N/A void stda( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A
0N/A // pp 97 (v8)
0N/A
0N/A inline void stc( int crd, Register s1, Register s2 );
0N/A inline void stc( int crd, Register s1, int simm13a);
0N/A inline void stdc( int crd, Register s1, Register s2 );
0N/A inline void stdc( int crd, Register s1, int simm13a);
0N/A inline void stcsr( int crd, Register s1, Register s2 );
0N/A inline void stcsr( int crd, Register s1, int simm13a);
0N/A inline void stdcq( int crd, Register s1, Register s2 );
0N/A inline void stdcq( int crd, Register s1, int simm13a);
0N/A
0N/A // pp 230
0N/A
0N/A void sub( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); }
0N/A void sub( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void subcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
0N/A void subcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void subc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); }
0N/A void subc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void subccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
0N/A void subccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A
0N/A // pp 231
0N/A
0N/A inline void swap( Register s1, Register s2, Register d );
0N/A inline void swap( Register s1, int simm13a, Register d);
0N/A inline void swap( Address& a, Register d, int offset = 0 );
0N/A
0N/A // pp 232
0N/A
0N/A void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
0N/A void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A
0N/A // pp 234, note op in book is wrong, see pp 268
0N/A
0N/A void taddcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); }
0N/A void taddcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void taddcctv( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | rs2(s2) ); }
0N/A void taddcctv( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A
0N/A // pp 235
0N/A
0N/A void tsubcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); }
0N/A void tsubcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A void tsubcctv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | rs2(s2) ); }
0N/A void tsubcctv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
0N/A
0N/A // pp 237
0N/A
0N/A void trap( Condition c, CC cc, Register s1, Register s2 ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
0N/A void trap( Condition c, CC cc, Register s1, int trapa ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
0N/A // simple uncond. trap
0N/A void trap( int trapa ) { trap( always, icc, G0, trapa ); }
0N/A
0N/A // pp 239 omit write priv register for now
0N/A
0N/A inline void wry( Register d) { v9_dep(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
0N/A inline void wrccr(Register s) { v9_only(); emit_long( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
0N/A inline void wrccr(Register s, int simm13a) { v9_only(); emit_long( op(arith_op) |
0N/A rs1(s) |
0N/A op3(wrreg_op3) |
0N/A u_field(2, 29, 25) |
0N/A u_field(1, 13, 13) |
0N/A simm(simm13a, 13)); }
0N/A inline void wrasi( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
0N/A inline void wrfprs( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
0N/A
0N/A
0N/A // Creation
0N/A Assembler(CodeBuffer* code) : AbstractAssembler(code) {
0N/A#ifdef CHECK_DELAY
0N/A delay_state = no_delay;
0N/A#endif
0N/A }
0N/A
0N/A // Testing
0N/A#ifndef PRODUCT
0N/A void test_v9();
0N/A void test_v8_onlys();
0N/A#endif
0N/A};
0N/A
0N/A
0N/Aclass RegistersForDebugging : public StackObj {
0N/A public:
0N/A intptr_t i[8], l[8], o[8], g[8];
0N/A float f[32];
0N/A double d[32];
0N/A
0N/A void print(outputStream* s);
0N/A
0N/A static int i_offset(int j) { return offset_of(RegistersForDebugging, i[j]); }
0N/A static int l_offset(int j) { return offset_of(RegistersForDebugging, l[j]); }
0N/A static int o_offset(int j) { return offset_of(RegistersForDebugging, o[j]); }
0N/A static int g_offset(int j) { return offset_of(RegistersForDebugging, g[j]); }
0N/A static int f_offset(int j) { return offset_of(RegistersForDebugging, f[j]); }
0N/A static int d_offset(int j) { return offset_of(RegistersForDebugging, d[j / 2]); }
0N/A
0N/A // gen asm code to save regs
0N/A static void save_registers(MacroAssembler* a);
0N/A
0N/A // restore global registers in case C code disturbed them
0N/A static void restore_registers(MacroAssembler* a, Register r);
0N/A};
0N/A
0N/A
0N/A// MacroAssembler extends Assembler by a few frequently used macros.
0N/A//
0N/A// Most of the standard SPARC synthetic ops are defined here.
0N/A// Instructions for which a 'better' code sequence exists depending
0N/A// on arguments should also go in here.
0N/A
0N/A#define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__)
0N/A#define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__)
0N/A#define JUMP(a, off) jump(a, off, __FILE__, __LINE__)
0N/A#define JUMPL(a, d, off) jumpl(a, d, off, __FILE__, __LINE__)
0N/A
0N/A
0N/Aclass MacroAssembler: public Assembler {
0N/A protected:
0N/A // Support for VM calls
0N/A // This is the base routine called by the different versions of call_VM_leaf. The interpreter
0N/A // may customize this version by overriding it for its purposes (e.g., to save/restore
0N/A // additional registers when doing a VM call).
0N/A#ifdef CC_INTERP
0N/A #define VIRTUAL
0N/A#else
0N/A #define VIRTUAL virtual
0N/A#endif
0N/A
0N/A VIRTUAL void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments);
0N/A
0N/A //
0N/A // It is imperative that all calls into the VM are handled via the call_VM macros.
0N/A // They make sure that the stack linkage is setup correctly. call_VM's correspond
0N/A // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
0N/A //
0N/A // This is the base routine called by the different versions of call_VM. The interpreter
0N/A // may customize this version by overriding it for its purposes (e.g., to save/restore
0N/A // additional registers when doing a VM call).
0N/A //
0N/A // A non-volatile java_thread_cache register should be specified so
0N/A // that the G2_thread value can be preserved across the call.
0N/A // (If java_thread_cache is noreg, then a slow get_thread call
0N/A // will re-initialize the G2_thread.) call_VM_base returns the register that contains the
0N/A // thread.
0N/A //
0N/A // If no last_java_sp is specified (noreg) than SP will be used instead.
0N/A
0N/A virtual void call_VM_base(
0N/A Register oop_result, // where an oop-result ends up if any; use noreg otherwise
0N/A Register java_thread_cache, // the thread if computed before ; use noreg otherwise
0N/A Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
0N/A address entry_point, // the entry point
0N/A int number_of_arguments, // the number of arguments (w/o thread) to pop after call
0N/A bool check_exception=true // flag which indicates if exception should be checked
0N/A );
0N/A
0N/A // This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code.
0N/A // The implementation is only non-empty for the InterpreterMacroAssembler,
0N/A // as only the interpreter handles and ForceEarlyReturn PopFrame requests.
0N/A virtual void check_and_handle_popframe(Register scratch_reg);
0N/A virtual void check_and_handle_earlyret(Register scratch_reg);
0N/A
0N/A public:
0N/A MacroAssembler(CodeBuffer* code) : Assembler(code) {}
0N/A
0N/A // Support for NULL-checks
0N/A //
0N/A // Generates code that causes a NULL OS exception if the content of reg is NULL.
0N/A // If the accessed location is M[reg + offset] and the offset is known, provide the
0N/A // offset. No explicit code generation is needed if the offset is within a certain
0N/A // range (0 <= offset <= page_size).
0N/A //
0N/A // %%%%%% Currently not done for SPARC
0N/A
0N/A void null_check(Register reg, int offset = -1);
0N/A static bool needs_explicit_null_check(intptr_t offset);
0N/A
0N/A // support for delayed instructions
0N/A MacroAssembler* delayed() { Assembler::delayed(); return this; }
0N/A
0N/A // branches that use right instruction for v8 vs. v9
0N/A inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
0N/A inline void br( Condition c, bool a, Predict p, Label& L );
0N/A inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
0N/A inline void fb( Condition c, bool a, Predict p, Label& L );
0N/A
0N/A // compares register with zero and branches (V9 and V8 instructions)
0N/A void br_zero( Condition c, bool a, Predict p, Register s1, Label& L);
0N/A // Compares a pointer register with zero and branches on (not)null.
0N/A // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
0N/A void br_null ( Register s1, bool a, Predict p, Label& L );
0N/A void br_notnull( Register s1, bool a, Predict p, Label& L );
0N/A
0N/A inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
0N/A inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
0N/A
0N/A // Branch that tests xcc in LP64 and icc in !LP64
0N/A inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
0N/A inline void brx( Condition c, bool a, Predict p, Label& L );
0N/A
0N/A // unconditional short branch
0N/A inline void ba( bool a, Label& L );
0N/A
0N/A // Branch that tests fp condition codes
0N/A inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
0N/A inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
0N/A
0N/A // get PC the best way
0N/A inline int get_pc( Register d );
0N/A
0N/A // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual)
0N/A inline void cmp( Register s1, Register s2 ) { subcc( s1, s2, G0 ); }
0N/A inline void cmp( Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); }
0N/A
0N/A inline void jmp( Register s1, Register s2 );
0N/A inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
0N/A
0N/A inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
0N/A inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
0N/A inline void callr( Register s1, Register s2 );
0N/A inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
0N/A
0N/A // Emits nothing on V8
0N/A inline void iprefetch( address d, relocInfo::relocType rt = relocInfo::none );
0N/A inline void iprefetch( Label& L);
0N/A
0N/A inline void tst( Register s ) { orcc( G0, s, G0 ); }
0N/A
0N/A#ifdef PRODUCT
0N/A inline void ret( bool trace = TraceJumps ) { if (trace) {
0N/A mov(I7, O7); // traceable register
0N/A JMP(O7, 2 * BytesPerInstWord);
0N/A } else {
0N/A jmpl( I7, 2 * BytesPerInstWord, G0 );
0N/A }
0N/A }
0N/A
0N/A inline void retl( bool trace = TraceJumps ) { if (trace) JMP(O7, 2 * BytesPerInstWord);
0N/A else jmpl( O7, 2 * BytesPerInstWord, G0 ); }
0N/A#else
0N/A void ret( bool trace = TraceJumps );
0N/A void retl( bool trace = TraceJumps );
0N/A#endif /* PRODUCT */
0N/A
0N/A // Required platform-specific helpers for Label::patch_instructions.
0N/A // They _shadow_ the declarations in AbstractAssembler, which are undefined.
0N/A void pd_patch_instruction(address branch, address target);
0N/A#ifndef PRODUCT
0N/A static void pd_print_patched_instruction(address branch);
0N/A#endif
0N/A
0N/A // sethi Macro handles optimizations and relocations
0N/A void sethi( Address& a, bool ForceRelocatable = false );
0N/A void sethi( intptr_t imm22a, Register d, bool ForceRelocatable = false, RelocationHolder const& rspec = RelocationHolder());
0N/A
0N/A // compute the size of a sethi/set
0N/A static int size_of_sethi( address a, bool worst_case = false );
0N/A static int worst_case_size_of_set();
0N/A
0N/A // set may be either setsw or setuw (high 32 bits may be zero or sign)
0N/A void set( intptr_t value, Register d, RelocationHolder const& rspec = RelocationHolder() );
0N/A void setsw( int value, Register d, RelocationHolder const& rspec = RelocationHolder() );
0N/A void set64( jlong value, Register d, Register tmp);
0N/A
0N/A // sign-extend 32 to 64
0N/A inline void signx( Register s, Register d ) { sra( s, G0, d); }
0N/A inline void signx( Register d ) { sra( d, G0, d); }
0N/A
0N/A inline void not1( Register s, Register d ) { xnor( s, G0, d ); }
0N/A inline void not1( Register d ) { xnor( d, G0, d ); }
0N/A
0N/A inline void neg( Register s, Register d ) { sub( G0, s, d ); }
0N/A inline void neg( Register d ) { sub( G0, d, d ); }
0N/A
0N/A inline void cas( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY); }
0N/A inline void casx( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY); }
0N/A // Functions for isolating 64 bit atomic swaps for LP64
0N/A // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's
0N/A inline void cas_ptr( Register s1, Register s2, Register d) {
0N/A#ifdef _LP64
0N/A casx( s1, s2, d );
0N/A#else
0N/A cas( s1, s2, d );
0N/A#endif
0N/A }
0N/A
0N/A // Functions for isolating 64 bit shifts for LP64
0N/A inline void sll_ptr( Register s1, Register s2, Register d );
0N/A inline void sll_ptr( Register s1, int imm6a, Register d );
0N/A inline void srl_ptr( Register s1, Register s2, Register d );
0N/A inline void srl_ptr( Register s1, int imm6a, Register d );
0N/A
0N/A // little-endian
0N/A inline void casl( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY_LITTLE); }
0N/A inline void casxl( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY_LITTLE); }
0N/A
0N/A inline void inc( Register d, int const13 = 1 ) { add( d, const13, d); }
0N/A inline void inccc( Register d, int const13 = 1 ) { addcc( d, const13, d); }
0N/A
0N/A inline void dec( Register d, int const13 = 1 ) { sub( d, const13, d); }
0N/A inline void deccc( Register d, int const13 = 1 ) { subcc( d, const13, d); }
0N/A
0N/A inline void btst( Register s1, Register s2 ) { andcc( s1, s2, G0 ); }
0N/A inline void btst( int simm13a, Register s ) { andcc( s, simm13a, G0 ); }
0N/A
0N/A inline void bset( Register s1, Register s2 ) { or3( s1, s2, s2 ); }
0N/A inline void bset( int simm13a, Register s ) { or3( s, simm13a, s ); }
0N/A
0N/A inline void bclr( Register s1, Register s2 ) { andn( s1, s2, s2 ); }
0N/A inline void bclr( int simm13a, Register s ) { andn( s, simm13a, s ); }
0N/A
0N/A inline void btog( Register s1, Register s2 ) { xor3( s1, s2, s2 ); }
0N/A inline void btog( int simm13a, Register s ) { xor3( s, simm13a, s ); }
0N/A
0N/A inline void clr( Register d ) { or3( G0, G0, d ); }
0N/A
0N/A inline void clrb( Register s1, Register s2);
0N/A inline void clrh( Register s1, Register s2);
0N/A inline void clr( Register s1, Register s2);
0N/A inline void clrx( Register s1, Register s2);
0N/A
0N/A inline void clrb( Register s1, int simm13a);
0N/A inline void clrh( Register s1, int simm13a);
0N/A inline void clr( Register s1, int simm13a);
0N/A inline void clrx( Register s1, int simm13a);
0N/A
0N/A // copy & clear upper word
0N/A inline void clruw( Register s, Register d ) { srl( s, G0, d); }
0N/A // clear upper word
0N/A inline void clruwu( Register d ) { srl( d, G0, d); }
0N/A
0N/A // membar psuedo instruction. takes into account target memory model.
0N/A inline void membar( Assembler::Membar_mask_bits const7a );
0N/A
0N/A // returns if membar generates anything.
0N/A inline bool membar_has_effect( Assembler::Membar_mask_bits const7a );
0N/A
0N/A // mov pseudo instructions
0N/A inline void mov( Register s, Register d) {
0N/A if ( s != d ) or3( G0, s, d);
0N/A else assert_not_delayed(); // Put something useful in the delay slot!
0N/A }
0N/A
0N/A inline void mov_or_nop( Register s, Register d) {
0N/A if ( s != d ) or3( G0, s, d);
0N/A else nop();
0N/A }
0N/A
0N/A inline void mov( int simm13a, Register d) { or3( G0, simm13a, d); }
0N/A
0N/A // address pseudos: make these names unlike instruction names to avoid confusion
0N/A inline void split_disp( Address& a, Register temp );
0N/A inline intptr_t load_pc_address( Register reg, int bytes_to_skip );
0N/A inline void load_address( Address& a, int offset = 0 );
0N/A inline void load_contents( Address& a, Register d, int offset = 0 );
0N/A inline void load_ptr_contents( Address& a, Register d, int offset = 0 );
0N/A inline void store_contents( Register s, Address& a, int offset = 0 );
0N/A inline void store_ptr_contents( Register s, Address& a, int offset = 0 );
0N/A inline void jumpl_to( Address& a, Register d, int offset = 0 );
0N/A inline void jump_to( Address& a, int offset = 0 );
0N/A
0N/A // ring buffer traceable jumps
0N/A
0N/A void jmp2( Register r1, Register r2, const char* file, int line );
0N/A void jmp ( Register r1, int offset, const char* file, int line );
0N/A
0N/A void jumpl( Address& a, Register d, int offset, const char* file, int line );
0N/A void jump ( Address& a, int offset, const char* file, int line );
0N/A
0N/A
0N/A // argument pseudos:
0N/A
0N/A inline void load_argument( Argument& a, Register d );
0N/A inline void store_argument( Register s, Argument& a );
0N/A inline void store_ptr_argument( Register s, Argument& a );
0N/A inline void store_float_argument( FloatRegister s, Argument& a );
0N/A inline void store_double_argument( FloatRegister s, Argument& a );
0N/A inline void store_long_argument( Register s, Argument& a );
0N/A
0N/A // handy macros:
0N/A
0N/A inline void round_to( Register r, int modulus ) {
0N/A assert_not_delayed();
0N/A inc( r, modulus - 1 );
0N/A and3( r, -modulus, r );
0N/A }
0N/A
0N/A // --------------------------------------------------
0N/A
0N/A // Functions for isolating 64 bit loads for LP64
0N/A // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's
0N/A // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's
0N/A inline void ld_ptr( Register s1, Register s2, Register d );
0N/A inline void ld_ptr( Register s1, int simm13a, Register d);
0N/A inline void ld_ptr( const Address& a, Register d, int offset = 0 );
0N/A inline void st_ptr( Register d, Register s1, Register s2 );
0N/A inline void st_ptr( Register d, Register s1, int simm13a);
0N/A inline void st_ptr( Register d, const Address& a, int offset = 0 );
0N/A
0N/A // ld_long will perform ld for 32 bit VM's and ldx for 64 bit VM's
0N/A // st_long will perform st for 32 bit VM's and stx for 64 bit VM's
0N/A inline void ld_long( Register s1, Register s2, Register d );
0N/A inline void ld_long( Register s1, int simm13a, Register d );
0N/A inline void ld_long( const Address& a, Register d, int offset = 0 );
0N/A inline void st_long( Register d, Register s1, Register s2 );
0N/A inline void st_long( Register d, Register s1, int simm13a );
0N/A inline void st_long( Register d, const Address& a, int offset = 0 );
0N/A
0N/A // --------------------------------------------------
0N/A
0N/A public:
0N/A // traps as per trap.h (SPARC ABI?)
0N/A
0N/A void breakpoint_trap();
0N/A void breakpoint_trap(Condition c, CC cc = icc);
0N/A void flush_windows_trap();
0N/A void clean_windows_trap();
0N/A void get_psr_trap();
0N/A void set_psr_trap();
0N/A
0N/A // V8/V9 flush_windows
0N/A void flush_windows();
0N/A
0N/A // Support for serializing memory accesses between threads
0N/A void serialize_memory(Register thread, Register tmp1, Register tmp2);
0N/A
0N/A // Stack frame creation/removal
0N/A void enter();
0N/A void leave();
0N/A
0N/A // V8/V9 integer multiply
0N/A void mult(Register s1, Register s2, Register d);
0N/A void mult(Register s1, int simm13a, Register d);
0N/A
0N/A // V8/V9 read and write of condition codes.
0N/A void read_ccr(Register d);
0N/A void write_ccr(Register s);
0N/A
0N/A // Manipulation of C++ bools
0N/A // These are idioms to flag the need for care with accessing bools but on
0N/A // this platform we assume byte size
0N/A
0N/A inline void stbool( Register d, const Address& a, int offset = 0 ) { stb(d, a, offset); }
0N/A inline void ldbool( const Address& a, Register d, int offset = 0 ) { ldsb( a, d, offset ); }
0N/A inline void tstbool( Register s ) { tst(s); }
0N/A inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); }
0N/A
0N/A // Support for managing the JavaThread pointer (i.e.; the reference to
0N/A // thread-local information).
0N/A void get_thread(); // load G2_thread
0N/A void verify_thread(); // verify G2_thread contents
0N/A void save_thread (const Register threache); // save to cache
0N/A void restore_thread(const Register thread_cache); // restore from cache
0N/A
0N/A // Support for last Java frame (but use call_VM instead where possible)
0N/A void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
0N/A void reset_last_Java_frame(void);
0N/A
0N/A // Call into the VM.
0N/A // Passes the thread pointer (in O0) as a prepended argument.
0N/A // Makes sure oop return values are visible to the GC.
0N/A void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
0N/A void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
0N/A void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
0N/A void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
0N/A
0N/A // these overloadings are not presently used on SPARC:
0N/A void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
0N/A void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
0N/A void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
0N/A void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
0N/A
0N/A void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0);
0N/A void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1);
0N/A void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2);
0N/A void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3);
0N/A
0N/A void get_vm_result (Register oop_result);
0N/A void get_vm_result_2(Register oop_result);
0N/A
0N/A // vm result is currently getting hijacked to for oop preservation
0N/A void set_vm_result(Register oop_result);
0N/A
0N/A // if call_VM_base was called with check_exceptions=false, then call
0N/A // check_and_forward_exception to handle exceptions when it is safe
0N/A void check_and_forward_exception(Register scratch_reg);
0N/A
0N/A private:
0N/A // For V8
0N/A void read_ccr_trap(Register ccr_save);
0N/A void write_ccr_trap(Register ccr_save1, Register scratch1, Register scratch2);
0N/A
0N/A#ifdef ASSERT
0N/A // For V8 debugging. Uses V8 instruction sequence and checks
0N/A // result with V9 insturctions rdccr and wrccr.
0N/A // Uses Gscatch and Gscatch2
0N/A void read_ccr_v8_assert(Register ccr_save);
0N/A void write_ccr_v8_assert(Register ccr_save);
0N/A#endif // ASSERT
0N/A
0N/A public:
0N/A // Stores
0N/A void store_check(Register tmp, Register obj); // store check for obj - register is destroyed afterwards
0N/A void store_check(Register tmp, Register obj, Register offset); // store check for obj - register is destroyed afterwards
0N/A
0N/A // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
0N/A void push_fTOS();
0N/A
0N/A // pops double TOS element from CPU stack and pushes on FPU stack
0N/A void pop_fTOS();
0N/A
0N/A void empty_FPU_stack();
0N/A
0N/A void push_IU_state();
0N/A void pop_IU_state();
0N/A
0N/A void push_FPU_state();
0N/A void pop_FPU_state();
0N/A
0N/A void push_CPU_state();
0N/A void pop_CPU_state();
0N/A
0N/A // Debugging
0N/A void _verify_oop(Register reg, const char * msg, const char * file, int line);
0N/A void _verify_oop_addr(Address addr, const char * msg, const char * file, int line);
0N/A
0N/A#define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__)
0N/A#define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__)
0N/A
0N/A // only if +VerifyOops
0N/A void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
0N/A // only if +VerifyFPU
0N/A void stop(const char* msg); // prints msg, dumps registers and stops execution
0N/A void warn(const char* msg); // prints msg, but don't stop
0N/A void untested(const char* what = "");
0N/A void unimplemented(const char* what = "") { char* b = new char[1024]; sprintf(b, "unimplemented: %s", what); stop(b); }
0N/A void should_not_reach_here() { stop("should not reach here"); }
0N/A void print_CPU_state();
0N/A
0N/A // oops in code
0N/A Address allocate_oop_address( jobject obj, Register d ); // allocate_index
0N/A Address constant_oop_address( jobject obj, Register d ); // find_index
0N/A inline void set_oop ( jobject obj, Register d ); // uses allocate_oop_address
0N/A inline void set_oop_constant( jobject obj, Register d ); // uses constant_oop_address
0N/A inline void set_oop ( Address obj_addr ); // same as load_address
0N/A
0N/A // nop padding
0N/A void align(int modulus);
0N/A
0N/A // declare a safepoint
0N/A void safepoint();
0N/A
0N/A // factor out part of stop into subroutine to save space
0N/A void stop_subroutine();
0N/A // factor out part of verify_oop into subroutine to save space
0N/A void verify_oop_subroutine();
0N/A
0N/A // side-door communication with signalHandler in os_solaris.cpp
0N/A static address _verify_oop_implicit_branch[3];
0N/A
0N/A#ifndef PRODUCT
0N/A static void test();
0N/A#endif
0N/A
0N/A // convert an incoming arglist to varargs format; put the pointer in d
0N/A void set_varargs( Argument a, Register d );
0N/A
0N/A int total_frame_size_in_bytes(int extraWords);
0N/A
0N/A // used when extraWords known statically
0N/A void save_frame(int extraWords);
0N/A void save_frame_c1(int size_in_bytes);
0N/A // make a frame, and simultaneously pass up one or two register value
0N/A // into the new register window
0N/A void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register());
0N/A
0N/A // give no. (outgoing) params, calc # of words will need on frame
0N/A void calc_mem_param_words(Register Rparam_words, Register Rresult);
0N/A
0N/A // used to calculate frame size dynamically
0N/A // result is in bytes and must be negated for save inst
0N/A void calc_frame_size(Register extraWords, Register resultReg);
0N/A
0N/A // calc and also save
0N/A void calc_frame_size_and_save(Register extraWords, Register resultReg);
0N/A
0N/A static void debug(char* msg, RegistersForDebugging* outWindow);
0N/A
0N/A // implementations of bytecodes used by both interpreter and compiler
0N/A
0N/A void lcmp( Register Ra_hi, Register Ra_low,
0N/A Register Rb_hi, Register Rb_low,
0N/A Register Rresult);
0N/A
0N/A void lneg( Register Rhi, Register Rlow );
0N/A
0N/A void lshl( Register Rin_high, Register Rin_low, Register Rcount,
0N/A Register Rout_high, Register Rout_low, Register Rtemp );
0N/A
0N/A void lshr( Register Rin_high, Register Rin_low, Register Rcount,
0N/A Register Rout_high, Register Rout_low, Register Rtemp );
0N/A
0N/A void lushr( Register Rin_high, Register Rin_low, Register Rcount,
0N/A Register Rout_high, Register Rout_low, Register Rtemp );
0N/A
0N/A#ifdef _LP64
0N/A void lcmp( Register Ra, Register Rb, Register Rresult);
0N/A#endif
0N/A
0N/A void float_cmp( bool is_float, int unordered_result,
0N/A FloatRegister Fa, FloatRegister Fb,
0N/A Register Rresult);
0N/A
0N/A void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
0N/A void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { Assembler::fneg(w, sd); }
0N/A void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
0N/A void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
0N/A
0N/A void save_all_globals_into_locals();
0N/A void restore_globals_from_locals();
0N/A
0N/A void casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
0N/A address lock_addr=0, bool use_call_vm=false);
0N/A void cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
0N/A address lock_addr=0, bool use_call_vm=false);
0N/A void casn (Register addr_reg, Register cmp_reg, Register set_reg) ;
0N/A
0N/A // These set the icc condition code to equal if the lock succeeded
0N/A // and notEqual if it failed and requires a slow case
0N/A void compiler_lock_object(Register Roop, Register Rmark, Register Rbox, Register Rscratch,
0N/A BiasedLockingCounters* counters = NULL);
0N/A void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox, Register Rscratch);
0N/A
0N/A // Biased locking support
0N/A // Upon entry, lock_reg must point to the lock record on the stack,
0N/A // obj_reg must contain the target object, and mark_reg must contain
0N/A // the target object's header.
0N/A // Destroys mark_reg if an attempt is made to bias an anonymously
0N/A // biased lock. In this case a failure will go either to the slow
0N/A // case or fall through with the notEqual condition code set with
0N/A // the expectation that the slow case in the runtime will be called.
0N/A // In the fall-through case where the CAS-based lock is done,
0N/A // mark_reg is not destroyed.
0N/A void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg,
0N/A Label& done, Label* slow_case = NULL,
0N/A BiasedLockingCounters* counters = NULL);
0N/A // Upon entry, the base register of mark_addr must contain the oop.
0N/A // Destroys temp_reg.
0N/A
0N/A // If allow_delay_slot_filling is set to true, the next instruction
0N/A // emitted after this one will go in an annulled delay slot if the
0N/A // biased locking exit case failed.
0N/A void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false);
0N/A
0N/A // allocation
0N/A void eden_allocate(
0N/A Register obj, // result: pointer to object after successful allocation
0N/A Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
0N/A int con_size_in_bytes, // object size in bytes if known at compile time
0N/A Register t1, // temp register
0N/A Register t2, // temp register
0N/A Label& slow_case // continuation point if fast allocation fails
0N/A );
0N/A void tlab_allocate(
0N/A Register obj, // result: pointer to object after successful allocation
0N/A Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
0N/A int con_size_in_bytes, // object size in bytes if known at compile time
0N/A Register t1, // temp register
0N/A Label& slow_case // continuation point if fast allocation fails
0N/A );
0N/A void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
0N/A
0N/A // Stack overflow checking
0N/A
0N/A // Note: this clobbers G3_scratch
0N/A void bang_stack_with_offset(int offset) {
0N/A // stack grows down, caller passes positive offset
0N/A assert(offset > 0, "must bang with negative offset");
0N/A set((-offset)+STACK_BIAS, G3_scratch);
0N/A st(G0, SP, G3_scratch);
0N/A }
0N/A
0N/A // Writes to stack successive pages until offset reached to check for
0N/A // stack overflow + shadow pages. Clobbers tsp and scratch registers.
0N/A void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch);
0N/A
0N/A void verify_tlab();
0N/A
0N/A Condition negate_condition(Condition cond);
0N/A
0N/A // Helper functions for statistics gathering.
0N/A // Conditionally (non-atomically) increments passed counter address, preserving condition codes.
0N/A void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2);
0N/A // Unconditional increment.
0N/A void inc_counter(address counter_addr, Register Rtemp1, Register Rtemp2);
0N/A
0N/A#undef VIRTUAL
0N/A
0N/A};
0N/A
0N/A/**
0N/A * class SkipIfEqual:
0N/A *
0N/A * Instantiating this class will result in assembly code being output that will
0N/A * jump around any code emitted between the creation of the instance and it's
0N/A * automatic destruction at the end of a scope block, depending on the value of
0N/A * the flag passed to the constructor, which will be checked at run-time.
0N/A */
0N/Aclass SkipIfEqual : public StackObj {
0N/A private:
0N/A MacroAssembler* _masm;
0N/A Label _label;
0N/A
0N/A public:
0N/A // 'temp' is a temp register that this object can use (and trash)
0N/A SkipIfEqual(MacroAssembler*, Register temp,
0N/A const bool* flag_addr, Assembler::Condition condition);
0N/A ~SkipIfEqual();
0N/A};
0N/A
0N/A#ifdef ASSERT
0N/A// On RISC, there's no benefit to verifying instruction boundaries.
0N/Ainline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
0N/A#endif