dmake clobber

dmake config

cd src

dmake kadd

Temperature overview about AMD CPU

===================================

Basically there are 3 temperature points, which are the most important for

AMD CPUs.

NOTE that all these T_* values below are not physical temperatures. So e.g.

a value of 70 may correspond to a physical temperature of 50C, 90C or whatever

(so seeing it as a difference between 2 current sources may help).

1) T_thermtrip: At this point the CPU damages are possible and thus the CPU

asserts the THERMTRIP_L signal and tries to switch off all clock and reduces

power consumption of the CPU to a minimum. The external chipset is expected

to power off the system (when it encounters the THERMTRIP_L signal).

Whether this functionallity is available/enabled, can be determined by

checking the Thermtrip Register F3xE4. The value of the related temperature

depends on the CPU and can not be retrieved programatically. The Electrical

DataSheet for 0Fh mentions a physical die temperature of 125C and that

THERMTRIP uses an internal temperature sensor independent of the thermal

diode!

2) T_htc_limit: At this point the CPU is getting really hot, enters a critical

area: "worst-case expected temperature under normal conditions" and thus

tries to cool it down by reducing the power consumption and performance

(by limiting all cores to a certain P-state, throttleing the clocks) for a

short time, periodically.

Also it signals this condition called HTC-active state by asserting

the PROCHOT_L pin. Whether this functionality (HTC) is supported can

be usually determined by checking the Northbridge capabilities register

F3xE8. Whether it is enabled and what value marks the T_htc_limit can be

usually deduced by checking the Hardware Thermal Control (HTC) Register

F3x64A.

NOTE: For Athlon64/Opteron (family < 04h) there is no documented way

to retrieve these values. For 0Fh family one can only determine,

whether the CPU is HTC capable, but neither whether it is enabled

nor the corresponding HTC limit value.

NOTE: This value is also referred as T control max. It corresponds to

T case max or T die max, which are physical values. So if this limit

has been reached, it also means, that T case/die max has been reached.

T control max. is usually about 70C, whereby T case max (lidded CPUs)

is ~70C+-15C and T case die (lidless CPUs) ~100+-5C.

NOTE: For Athlon64/Opteron revision D and E the T case max value is

programmed into the CPU and can be obtained from the Thermtrip Register

F3xE4. For all other CPUs these values can be found in the Power and Thermal

Data Sheet of the related family.

3) T_htc_hyst: Once a CPU entered the HTC-active state it tries to cool down

by reducing power and performance periodically until the CPU temperature

drops below or is equal to this value. At this point it also deasserts the

PROCHOT_L pin.

Usually this value can be determined as well by checking the HTC Register

F3x64A. The value returned here is the difference between T_htc_limit and

T_htc_hyst.

NOTE: For Athlon64/Opteron and for 0Fh family there is no documented way

to obtain this value.

So finally the following equation should always be true:

T_thermtrip > T_htc_limit > T_htc_hyst

The actual "CPU temperature value" which gets compared against the ones

mentioned above is called "control temperature" or "T control". Obviously

this is not a physical temperature as well and it should be clear, that no

physical temperature is needed for temperature control at all (and that e.g.

an increment of 1C physical may result in an increment e.g. of 2 of the control

temperature value).

The the T control can be obtained be obtain for family 10h and better via

the Reported Temperature Control Register F3xA4, for family 0Fh revision G

or better via the Thermtrip Register F3xE4. For older revisions incl. the

Athlon64/Opteron there is no documented way to obtain this value.

NOTE: Before T control gets compared against of other limit/hysteresis one

needs to add a possible diode offset. For family 12h and better there is

no such value, for 11h and less its value can be obtained from the Thermtrip

Register F3xE4 as well. This value is based on a ideality factor of 1.008.

If the thermal monitor has a different value, a small correction to this offset

is required. Contact the diode thermal monitor vendor to determine if

additional correction is required.

NOTE: Since Athlon64/Opteron does not provide a T control value and all models

of the 0Fh family are affected by erratum 141 (inaccurate temperature values),

actually using T control for something valueable start to make sense only

beginning with family 10h. However, in 10h there are some silicon revisions,

which provide inaccurate temperature values too (erratum 319). So take care!

Here the only useful thing which can be done is to poll the HTCactive state

and perhaps ThermtripSense bits of the related registers to e.g. log, that a

CPU got hot.

Last but not least and for completness, it should be mentioned, that some CPUs

also provided a 2nd register analog to the HTC. E.g. for 0F and 10h it is

called Software Thermal Control (STC) Register F3x68 and has in principal the

same semantics as the HTC, but does not assert PROCHOT_L if the limit has been

reached and may trigger and interrupt or bus cycle. In 12h and 14h it is

called Local Hardware Thermal Control (LHTC) F3x138, whereby they do not

provide any trigger facilities.

Thermtrip Register F3xE4 overview:

----------------------------------

/* Thermtrip 0xE4

* Athlon64/Opteron 0Fh 10h,11h 12h/14h/15h

* 31 SwThermtp 31 SwThermtp 31 SwThermtp 31 SwThermtp

* 30-29 reserved 30-29 reserved 30-15 reserved 30-06 reserved

* 28-25 TcaseMax 28-24 TjOffset

* 24 DiodeOffsetSignBit (D)

* 23-14 reserved 23-14 CurTmp

* 13-08 DiodeOffset 13-08 DiodeOffset 14-08 DiodeOffset

* 07-06 reserved 07 reserved 07-06 reserved

* 06 ThermSenseSel

* 05 ThermtpEn 05 ThermtpEn 05 ThermtpEn 05 ThermtpEn

* 04 ThermtpSense1 04 ThermtpSense1 04 reserved 04 reserved

* 03 ThermtpSense0 03 ThermtpSense0 03 ThermtpSense 03 ThermtpSense

* 02 reserved 02 ThermSenseCoreSel 02 reserved 02 reserved

* 01 Thermtp 01 Thermtp 01 Thermtp 01 Thermtp

* 00 reserved 00 reserved 00 reserved 00 reserved

*/

Last update: 2012-06-04 (Jens Elkner)