mach_sfmmu.h revision d39fefdf3aeec16d43d13967fd24e698a60d8e94
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* VM - Hardware Address Translation management.
*
* This file describes the contents of the sun reference mmu (sfmmu)
* specific hat data structures and the sfmmu specific hat procedures.
*/
#ifndef _VM_MACH_SFMMU_H
#define _VM_MACH_SFMMU_H
#pragma ident "%Z%%M% %I% %E% SMI"
#include <sys/hypervisor_api.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* Define UTSB_PHYS if user TSB is always accessed via physical address.
* On sun4v platform, user TSB is accessed via physical address.
*/
#define UTSB_PHYS 1
/*
* Hypervisor TSB info
*/
#define NHV_TSB_INFO 2
#ifndef _ASM
struct hv_tsb_block {
};
#endif /* _ASM */
#ifdef _ASM
/*
* This macro is used in the MMU code to check if TL should be lowered from
* 2 to 1 to pop trapstat's state. See the block comment in trapstat.c
* for details.
*/
nop; \
9:
/*
* The following macros allow us to share majority of the
* SFMMU code between sun4u and sun4v platforms.
*/
/*
* Macro to swtich to alternate global register on sun4u platforms
* (not applicable to sun4v platforms)
*/
#define USE_ALTERNATE_GLOBALS(scr)
/*
* Macro to set %gl register value on sun4v platforms
* (not applicable to sun4u platforms)
*/
#define SET_GL_REG(val) \
/*
* Get pseudo-tagacc value and context from the MMU fault area. Pseudo-tagacc
* is the faulting virtual address OR'd with 0 for KCONTEXT, INVALID_CONTEXT
* (1) for invalid context, and USER_CONTEXT (2) for user context.
*
* In:
* tagacc, ctxtype = scratch registers
* Out:
* tagacc = MMU data tag access register value
* ctx = context type (KCONTEXT, INVALID_CONTEXT or USER_CONTEXT)
*/
/*
* Synthesize/get data tag access register value from the MMU fault area
*
* In:
* tagacc, scr1 = scratch registers
* Out:
* tagacc = MMU data tag access register value
*/
/*
* Synthesize/get data tag target register value from the MMU fault area
*
* In:
* ttarget, scr1 = scratch registers
* Out:
* ttarget = MMU data tag target register value
*/
/*
* Synthesize/get data/instruction psuedo tag access register values
* from the MMU fault area (context is 0 for kernel, 1 for invalid, 2 for user)
*
* In:
* dtagacc, itagacc, scr1, scr2 = scratch registers
* Out:
* dtagacc = MMU data tag access register value w/psuedo-context
* itagacc = MMU instruction tag access register value w/pseudo-context
*/
/*
* Synthesize/get MMU data fault address from the MMU fault area
*
* In:
* daddr, scr1 = scratch registers
* Out:
* daddr = MMU data fault address
*/
/*
* Get pseudo-tagacc value and context from the MMU fault area. Pseudo-tagacc
* is the faulting virtual address OR'd with 0 for KCONTEXT, INVALID_CONTEXT
* (1) for invalid context, and USER_CONTEXT (2) for user context.
*
* In:
* tagacc, ctxtype = scratch registers
* Out:
* tagacc = MMU instruction tag access register value
* ctxtype = context type (KCONTEXT, INVALID_CONTEXT or USER_CONTEXT)
*/
/*
* Load ITLB entry
*
* In:
* tte = reg containing tte
* scr1, scr2, scr3, scr4 = scratch registers
*/
MMU_FAULT_STATUS_AREA(%o2); \
ta MMU_MAP_ADDR; \
/* BEGIN CSTYLED */ \
/* END CSTYLED */ \
/*
* Load DTLB entry
*
* In:
* tte = reg containing tte
* scr1, scr2, scr3, scr4 = scratch registers
*/
MMU_FAULT_STATUS_AREA(%o2); \
ta MMU_MAP_ADDR; \
/* BEGIN CSTYLED */ \
/* END CSTYLED */ \
/*
* Returns PFN given the TTE and vaddr
*
* In:
* tte = reg containing tte
* vaddr = reg containing vaddr
* scr1, scr2, scr3 = scratch registers
* Out:
* tte = PFN value
*/
/* CSTYLED */ \
/* CSTYLED */ \
/*
* TTE_SET_REF_ML is a macro that updates the reference bit if it is
* not already set.
*
* Parameters:
* tte = reg containing tte
* ttepa = physical pointer to tte
* tteva = virtual ptr to tte
* tsbarea = tsb miss area
* tmp1 = tmp reg
* label = temporary label
*/
/* BEGIN CSTYLED */ \
/* check reference bit */ \
nop; \
/* update reference bit */ \
/* END CSTYLED */
/*
* TTE_SET_REFMOD_ML is a macro that updates the reference and modify bits
* if not already set.
*
* Parameters:
* tte = reg containing tte
* ttepa = physical pointer to tte
* tteva = virtual ptr to tte
* tsbarea = tsb miss area
* tmp1 = tmp reg
* label = temporary label
* exitlabel = label where to jump to if write perm bit not set.
*/
exitlabel) \
/* BEGIN CSTYLED */ \
/* check reference bit */ \
nop; \
/* update reference bit */ \
/* END CSTYLED */
/*
* Synthesize a TSB base register contents for a process.
*
* In:
* tsbinfo = TSB info pointer (ro)
* tsbreg, tmp1 = scratch registers
* Out:
* tsbreg = value to program into TSB base register
*/
/*
* Load TSB base register into a dedicated scratchpad register.
* This register contains utsb_pabase in bits 63:13, and TSB size
* code in bits 2:0.
*
* In:
* tsbreg = value to load (ro)
* regnum = constant or register
* tmp1 = scratch register
* Out:
* Specified scratchpad register updated
*
*/
/*
* Get TSB base register from the scratchpad
*
* In:
* regnum = constant or register
* tsbreg = scratch
* Out:
* tsbreg = tsbreg from the specified scratchpad register
*/
/*
* Get the location of the TSB entry in the first TSB to probe
*
* In:
* tagacc = tag access register (not clobbered)
* tsbe, tmp1, tmp2 = scratch registers
* Out:
* tsbe = pointer to the tsbe in the 1st TSB
*/
/* BEGIN CSTYLED */ \
/* END CSTYLED */
/*
* Will probe the first TSB, and if it finds a match, will insert it
* into the TLB and retry.
*
* tsbe_ptr = precomputed first TSB entry pointer (in, ro)
* vpg_4m = 4M virtual page number for tag matching (in, ro)
* label = where to branch to if this is a miss (text)
* %asi = atomic ASI to use for the TSB access
*
* For trapstat, we have to explicily use these registers.
* g4 = location tag will be retrieved into from TSB (out)
* g5 = location data(tte) will be retrieved into from TSB (out)
*/
/* BEGIN CSTYLED */ \
nop ;\
nop ;\
TT_TRACE(trace_tsbhit) ;\
/* trapstat expects tte in %g5 */ ;\
retry /* retry faulted instruction */ ;\
/* END CSTYLED */
/*
* Same as above, only if the TTE doesn't have the execute
* bit set, will branch to exec_fault directly.
*/
/* BEGIN CSTYLED */ \
nop ;\
nop ;\
nop ;\
TT_TRACE(trace_tsbhit) ;\
retry /* retry faulted instruction */ ;\
/* END CSTYLED */
/*
* Get the location in the 2nd TSB of the tsbe for this fault.
* Assumes that the second TSB only contains 4M mappings.
*
* In:
* tagacc = tag access register (not clobbered)
* tsbe, tmp1, tmp2 = scratch registers
* Out:
* tsbe = pointer to the tsbe in the 2nd TSB
*/
/*
* vpg_4m = 4M virtual page number for tag matching (in)
* tsbe_ptr = precomputed second TSB entry pointer (in)
* label = label to use to make branch targets unique (text)
*
* For trapstat, we have to explicity use these registers.
* g4 = tag portion of TSBE (out)
* g5 = data portion of TSBE (out)
*/
/* BEGIN CSTYLED */ \
/* since we are looking at 2nd tsb, if it's valid, it must be 4M */ ;\
nop ;\
nop ;\
TT_TRACE(trace_tsbhit) ;\
/* trapstat expects tte in %g5 */ ;\
retry /* retry faulted instruction */ ;\
/* END CSTYLED */
/*
* Same as above, with the following additions:
* If the TTE found is not executable, branch directly
* to exec_fault. If a TSB miss, branch to TSB miss handler.
*/
/* BEGIN CSTYLED */ \
nop ;\
nop ;\
TT_TRACE(trace_tsbhit) ;\
retry /* retry faulted instruction */ \
/* END CSTYLED */
#endif /* _ASM */
#ifdef __cplusplus
}
#endif
#endif /* _VM_MACH_SFMMU_H */