nxge_phy_hw.h revision 4496171313bed39e96f21bc2f9faf2868e267ae3
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_NXGE_NXGE_PHY_HW_H
#define _SYS_NXGE_NXGE_PHY_HW_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
#include <nxge_defs.h>
#define BCM5464_NEPTUNE_PORT_ADDR_BASE 10
#define BCM8704_NEPTUNE_PORT_ADDR_BASE 8
#define BCM8704_N2_PORT_ADDR_BASE 16
#define BCM8704_PMA_PMD_DEV_ADDR 1
#define BCM8704_PCS_DEV_ADDR 3
#define BCM8704_USER_DEV3_ADDR 3
#define BCM8704_PHYXS_ADDR 4
#define BCM8704_USER_DEV4_ADDR 4
/* Definitions for BCM 5464R PHY chip */
#define BCM5464R_PHY_ECR 16
#define BCM5464R_PHY_ESR 17
#define BCM5464R_RXERR_CNT 18
#define BCM5464R_FALSECS_CNT 19
#define BCM5464R_RX_NOTOK_CNT 20
#define BCM5464R_ER_DATA 21
#define BCM5464R_RES 22
#define BCM5464R_ER_ACC 23
#define BCM5464R_AUX_CTL 24
#define BCM5464R_AUX_S 25
#define BCM5464R_INTR_S 26
#define BCM5464R_INTR_M 27
#define BCM5464R_MISC 28
#define BCM5464R_MISC1 29
#define BCM5464R_TESTR1 30
#define PHY_BCM_5464R_OUI 0x001018
#define PHY_BCM_5464R_MODEL 0x0B
/*
* MII Register 16: PHY Extended Control Register
*/
typedef union _mii_phy_ecr_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
/*
* MII Register 17: PHY Extended Status Register
*/
typedef union _mii_phy_esr_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
/*
* MII Register 18: Receive Error Counter Register
*/
typedef union _mii_rxerr_cnt_t {
struct {
} bits;
/*
* MII Register 19: False Carrier Sense Counter Register
*/
typedef union _mii_falsecs_cnt_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
/*
* MII Register 20: Receiver NOT_OK Counter Register
*/
typedef union _mii_rx_notok_cnt_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
/*
* MII Register 21: Expansion Register Data Register
*/
typedef union _mii_er_data_t {
struct {
} bits;
/*
* MII Register 23: Expansion Register Access Register
*/
typedef union _mii_er_acc_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
#define EXP_RXTX_PKT_CNT 0x0
#define EXP_INTR_STAT 0x1
#define MULTICOL_LED_SEL 0x4
#define MULTICOL_LED_FLASH_RATE_CTL 0x5
#define MULTICOL_LED_BLINK_CTL 0x6
#define CABLE_DIAG_CTL 0x10
#define CABLE_DIAG_RES 0x11
#define CABLE_DIAG_LEN_CH_2_1 0x12
#define CABLE_DIAG_LEN_CH_4_3 0x13
/*
* MII Register 24: Auxiliary Control Register
*/
typedef union _mii_aux_ctl_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
#define AUX_REG 0x0
#define AUX_10BASET 0x1
#define AUX_PWR_CTL 0x2
#define AUX_MISC_TEST 0x4
#define AUX_MISC_CTL 0x7
/*
* MII Register 25: Auxiliary Status Summary Register
*/
typedef union _mii_aux_s_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
} mii_aux_s_t, *p_mii_aux_s_t;
/*
* MII Register 26, 27: Interrupt Status and Mask Registers
*/
typedef union _mii_intr_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
} mii_intr_t, *p_mii_intr_t;
/*
* MII Register 28: Register 1C Access Register
*/
typedef union _mii_misc_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
} mii_misc_t, *p_mii_misc_t;
#define LINK_LED_MODE 0x2
#define CLK_ALIGN_CTL 0x3
#define WIRE_SP_RETRY 0x4
#define CLK125 0x5
#define LED_STATUS 0x8
#define LED_CONTROL 0x9
#define AUTO_PWR_DOWN 0xA
#define LED_SEL1 0xD
#define LED_SEL2 0xE
/*
*/
typedef union _mii_misc1_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
} mii_misc1_t, *p_mii_misc1_t;
/*
* MII Register 30: Test Register 1
*/
typedef union _mii_test1_t {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
} mii_test1_t, *p_mii_test1_t;
/* Definitions of BCM8704 */
#define BCM8704_PMD_CONTROL_REG 0
#define BCM8704_PMD_STATUS_REG 0x1
#define BCM8704_PMD_ID_0_REG 0x2
#define BCM8704_PMD_ID_1_REG 0x3
#define BCM8704_PMD_SPEED_ABIL_REG 0x4
#define BCM8704_PMD_DEV_IN_PKG1_REG 0x5
#define BCM8704_PMD_DEV_IN_PKG2_REG 0x6
#define BCM8704_PMD_CONTROL2_REG 0x7
#define BCM8704_PMD_STATUS2_REG 0x8
#define BCM8704_PMD_TRANSMIT_DIS_REG 0x9
#define BCM8704_PMD_RECEIVE_SIG_DETECT 0xa
#define BCM8704_PMD_ORG_UNIQUE_ID_0_REG 0xe
#define BCM8704_PMD_ORG_UNIQUE_ID_1_REG 0xf
#define BCM8704_PCS_CONTROL_REG 0
#define BCM8704_PCS_STATUS1_REG 0x1
#define BCM8704_PCS_ID_0_REG 0x2
#define BCM8704_PCS_ID_1_REG 0x3
#define BCM8704_PCS_SPEED_ABILITY_REG 0x4
#define BCM8704_PCS_DEV_IN_PKG1_REG 0x5
#define BCM8704_PCS_DEV_IN_PKG2_REG 0x6
#define BCM8704_PCS_CONTROL2_REG 0x7
#define BCM8704_PCS_STATUS2_REG 0x8
#define BCM8704_PCS_ORG_UNIQUE_ID_0_REG 0xe
#define BCM8704_PCS_ORG_UNIQUE_ID_1_REG 0xf
#define BCM8704_PCS_STATUS_REG 0x18
#define BCM8704_10GBASE_R_PCS_STATUS_REG 0x20
#define BCM8704_10GBASE_R_PCS_STATUS2_REG 0x21
#define BCM8704_PHYXS_CONTROL_REG 0
#define BCM8704_PHYXS_STATUS_REG 0x1
#define BCM8704_PHY_ID_0_REG 0x2
#define BCM8704_PHY_ID_1_REG 0x3
#define BCM8704_PHYXS_SPEED_ABILITY_REG 0x4
#define BCM8704_PHYXS_DEV_IN_PKG2_REG 0x5
#define BCM8704_PHYXS_DEV_IN_PKG1_REG 0x6
#define BCM8704_PHYXS_STATUS2_REG 0x8
#define BCM8704_PHYXS_ORG_UNIQUE_ID_0_REG 0xe
#define BCM8704_PHYXS_ORG_UNIQUE_ID_1_REG 0xf
#define BCM8704_PHYXS_XGXS_LANE_STATUS_REG 0x18
#define BCM8704_PHYXS_XGXS_TEST_CONTROL_REG 0x19
#define BCM8704_USER_CONTROL_REG 0xC800
#define BCM8704_USER_ANALOG_CLK_REG 0xC801
#define BCM8704_USER_PMD_RX_CONTROL_REG 0xC802
#define BCM8704_USER_PMD_TX_CONTROL_REG 0xC803
#define BCM8704_USER_ANALOG_STATUS0_REG 0xC804
#define BCM8704_USER_OPTICS_DIGITAL_CTRL_REG 0xC808
#define BCM8704_USER_RX2_CONTROL1_REG 0x80C6
#define BCM8704_USER_RX1_CONTROL1_REG 0x80D6
#define BCM8704_USER_RX0_CONTROL1_REG 0x80E6
#define BCM8704_USER_TX_ALARM_STATUS_REG 0x9004
/* Rx Channel Control1 Register bits */
#define BCM8704_RXPOL_FLIP 0x20
typedef union _phyxs_control {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
typedef union _control {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
} control_t, *p_control_t;
typedef union _pmd_tx_control {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
typedef union _optics_dcntr {
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} bits;
/* PMD Receive Signal Detect Register (Dev = 1 Register Address = 0x000A) */
#define PMD_RX_SIG_DET3 0x10
#define PMD_RX_SIG_DET2 0x08
#define PMD_RX_SIG_DET1 0x04
#define PMD_RX_SIG_DET0 0x02
#define GLOB_PMD_RX_SIG_OK 0x01
/* 10GBase-R PCS Status Register (Dev = 3, Register Address = 0x0020) */
#define PCS_10GBASE_RX_LINK_STATUS 0x1000
#define PCS_PRBS31_ABLE 0x0004
#define PCS_10GBASE_R_HI_BER 0x0002
#define PCS_10GBASE_R_PCS_BLK_LOCK 0x0001
/* XGXS Lane Status Register (Dev = 4, Register Address = 0x0018) */
#define XGXS_LANE_ALIGN_STATUS 0x1000
#define XGXS_PATTERN_TEST_ABILITY 0x0800
#define XGXS_LANE3_SYNC 0x0008
#define XGXS_LANE2_SYNC 0x0004
#define XGXS_LANE1_SYNC 0x0002
#define XGXS_LANE0_SYNC 0x0001
#ifdef __cplusplus
}
#endif
#endif /* _SYS_NXGE_NXGE_PHY_HW_H */