mmu.h revision 05d3dc4b6755c54754109ffbe7e792f4e5b7c7c9
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fa9e4066f08beec538e775443c5be79dd423fcabahrens * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
fa9e4066f08beec538e775443c5be79dd423fcabahrens * Use is subject to license terms.
fa9e4066f08beec538e775443c5be79dd423fcabahrens#pragma ident "%Z%%M% %I% %E% SMI"
fa9e4066f08beec538e775443c5be79dd423fcabahrensextern "C" {
fa9e4066f08beec538e775443c5be79dd423fcabahrens * Definitions for the SOFT MMU
fa9e4066f08beec538e775443c5be79dd423fcabahrens * Constants defining alternate spaces
fa9e4066f08beec538e775443c5be79dd423fcabahrens * and register layouts within them,
fa9e4066f08beec538e775443c5be79dd423fcabahrens * and a few other interesting assembly constants.
fa9e4066f08beec538e775443c5be79dd423fcabahrens * vaddr offsets of various registers
1d452cf5123cb6ac0a013a4dbd4dcceeb0da314dahrens#define MMU_PCONTEXT 0x08 /* primary context number */
1d452cf5123cb6ac0a013a4dbd4dcceeb0da314dahrens#define MMU_SCONTEXT 0x10 /* secondary context number */
1d452cf5123cb6ac0a013a4dbd4dcceeb0da314dahrens#define MMU_PCONTEXT0 MMU_PCONTEXT /* primary context# 0 */
1d452cf5123cb6ac0a013a4dbd4dcceeb0da314dahrens#define MMU_SCONTEXT0 MMU_SCONTEXT /* secondary context# 0 */
1d452cf5123cb6ac0a013a4dbd4dcceeb0da314dahrens#define MMU_SCONTEXT1 0x110 /* secondary context# 1 */
1d452cf5123cb6ac0a013a4dbd4dcceeb0da314dahrens * Pseudo Synchronous Fault Status Register Layout
1d452cf5123cb6ac0a013a4dbd4dcceeb0da314dahrens * IMMU and DMMU maintain their own pseudo SFSR Register
1d452cf5123cb6ac0a013a4dbd4dcceeb0da314dahrens * +------------------------------------------------+
1d452cf5123cb6ac0a013a4dbd4dcceeb0da314dahrens * | Reserved | Context | FT |
1d452cf5123cb6ac0a013a4dbd4dcceeb0da314dahrens * +----------------------|-------------------------+
1d452cf5123cb6ac0a013a4dbd4dcceeb0da314dahrens * 63 32 31 16 15 0
1d452cf5123cb6ac0a013a4dbd4dcceeb0da314dahrens * Definition of FT (Fault Type) bit field of sfsr.
1d452cf5123cb6ac0a013a4dbd4dcceeb0da314dahrens#define FT_PRIV MMFSA_F_PRIV /* privilege violation */
1d452cf5123cb6ac0a013a4dbd4dcceeb0da314dahrens#define FT_SPEC_LD MMFSA_F_SOPG /* speculative ld to e page */
1d452cf5123cb6ac0a013a4dbd4dcceeb0da314dahrens#define FT_ATOMIC_NC MMFSA_F_NCATM /* atomic to nc page */
1d452cf5123cb6ac0a013a4dbd4dcceeb0da314dahrens#define FT_ILL_ALT MMFSA_F_INVASI /* illegal lda/sta */
1d452cf5123cb6ac0a013a4dbd4dcceeb0da314dahrens#define FT_NFO MMFSA_F_NFO /* normal access to nfo page */
1d452cf5123cb6ac0a013a4dbd4dcceeb0da314dahrens#define FT_RANGE MMFSA_F_INVVA /* dmmu or immu address out of range */
1d452cf5123cb6ac0a013a4dbd4dcceeb0da314dahrens#define FT_NEW_FPROT MMFSA_F_FPROT /* fast protection */
fa9e4066f08beec538e775443c5be79dd423fcabahrens#define FT_NEW_PROT MMFSA_F_PROT /* protection violation */
fa9e4066f08beec538e775443c5be79dd423fcabahrens#define FT_NEW_PRVACT MMFSA_F_PRVACT /* privileged action */
fa9e4066f08beec538e775443c5be79dd423fcabahrens#define FT_NEW_UNALIGN MMFSA_F_UNALIGN /* unaligned access */
fa9e4066f08beec538e775443c5be79dd423fcabahrens#define FT_NEW_INVPGSZ MMFSA_F_INVPGSZ /* invalid page size */
fa9e4066f08beec538e775443c5be79dd423fcabahrens#define SFSR_FT_SHIFT 0 /* amt. to shift right to get flt type */
fa9e4066f08beec538e775443c5be79dd423fcabahrens#define SFSR_CTX_SHIFT 16 /* to shift right to get context */
fa9e4066f08beec538e775443c5be79dd423fcabahrens#define X_FAULT_TYPE(x) (((x) & SFSR_FT) >> SFSR_FT_SHIFT)
fa9e4066f08beec538e775443c5be79dd423fcabahrens#define X_FAULT_CTX(x) (((x) & SFSR_CTX) >> SFSR_CTX_SHIFT)
fa9e4066f08beec538e775443c5be79dd423fcabahrens * MMU TAG TARGET register Layout
fa9e4066f08beec538e775443c5be79dd423fcabahrens * +---------------+------+-------------------------+
b81d61a68b235e0529ebadc18e14d9d1dd52a258lling * | context | -- | virtual address [63:22] |
b81d61a68b235e0529ebadc18e14d9d1dd52a258lling * +---------------+------+-------------------------+
b81d61a68b235e0529ebadc18e14d9d1dd52a258lling * 63 48 47 42 41 0
b81d61a68b235e0529ebadc18e14d9d1dd52a258lling * Some sun4v processors only use a 13-bit context ID, so bits 61-63 will be
b81d61a68b235e0529ebadc18e14d9d1dd52a258lling * zero in that case. This layout allows us to use the same code for any sun4v
b81d61a68b235e0529ebadc18e14d9d1dd52a258lling * processors, whether they support 13 bit or 16 bit context IDs (or something
b81d61a68b235e0529ebadc18e14d9d1dd52a258lling * in between).
b81d61a68b235e0529ebadc18e14d9d1dd52a258lling * Pseudo MMU TAG ACCESS register Layout
fa9e4066f08beec538e775443c5be79dd423fcabahrens * +-------------------------+------------------+
fa9e4066f08beec538e775443c5be79dd423fcabahrens * | virtual address [63:13] | 0 | type |
fa9e4066f08beec538e775443c5be79dd423fcabahrens * +-------------------------+------------------+
fa9e4066f08beec538e775443c5be79dd423fcabahrens * 63 13 12 2 1 0
fa9e4066f08beec538e775443c5be79dd423fcabahrens * 16-bit context IDs don't fit into the 13 bit field as they did on sun4u,
fa9e4066f08beec538e775443c5be79dd423fcabahrens * so we use a context type, 0 = kernel context, 1 = invalid context,
fa9e4066f08beec538e775443c5be79dd423fcabahrens * 2 = user context.
fa9e4066f08beec538e775443c5be79dd423fcabahrens * The kernel always runs in KCONTEXT, and no user mappings
fa9e4066f08beec538e775443c5be79dd423fcabahrens * are ever valid in it (so any user access pagefaults).
fa9e4066f08beec538e775443c5be79dd423fcabahrens * FLUSH_ADDR is used in the flush instruction to guarantee stores to mmu
fa9e4066f08beec538e775443c5be79dd423fcabahrens * registers complete. It is selected so it won't miss in the tlb.
fa9e4066f08beec538e775443c5be79dd423fcabahrens#define MAX_NCTXS_BITS 16 /* sun4v max. contexts bits */
fa9e4066f08beec538e775443c5be79dd423fcabahrens * MIN_NCONTEXTS and MIN_NTSBS are the minimum number of contexts and tsbs
fa9e4066f08beec538e775443c5be79dd423fcabahrens * necessary for shared context support.
fa9e4066f08beec538e775443c5be79dd423fcabahrens#endif /* _SYS_MMU_H */