fillsysinfo.c revision fedab560fb18c85777c255ea9f445ffaf6830d30
2N/A * The contents of this file are subject to the terms of the 2N/A * Common Development and Distribution License (the "License"). 2N/A * You may not use this file except in compliance with the License. 2N/A * See the License for the specific language governing permissions 2N/A * and limitations under the License. 2N/A * When distributing Covered Code, include this CDDL HEADER in each 2N/A * If applicable, add the following below this CDDL HEADER, with the 2N/A * fields enclosed by brackets "[]" replaced with your own identifying 2N/A * information: Portions Copyright [yyyy] [name of copyright owner] 2N/A * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 2N/A * Use is subject to license terms. 2N/A#
pragma ident "%Z%%M% %I% %E% SMI" 2N/A/* prevent compilation with VAC defined */ 2N/A#
error "The sun4v architecture does not support VAC" 2N/A * For backward compatibility we need to verify that we can handle 2N/A * running on platforms which shipped with missing MD properties. 2N/A "cpu excluded from configuration",
cpuid);
2N/A * Since the CPU cannot be used, make sure it 2N/A * is in a safe place. If the firmware does not 2N/A * support CPU stop, this is known to be true. 2N/A * If it fails to stop for any other reason, the 2N/A * system is in an inconsistent state and cannot 2N/A * be allowed to continue. 2N/A "fit into the cpunode name buffer");
2N/A * Compute scaling factor based on rate of %tick. This is used 2N/A * to convert from ticks derived from %tick to nanoseconds. See * The nodeid is not used in sun4v at all. Setting it * to positive value to make starting of slave CPUs * Obtain the L2 cache information from MD. * If "Cache" node exists, then set L2 cache properties * If node does not exists, then set the L2 cache properties * in individual CPU module. * Do not expect L2 cache properties to be bigger * Start off by assigning the cpu id as the default * Find the cpu integer exec units - and * setup the mappings appropriately. /* Spin through and find all the integer exec units */ /* ignore nodes with no type */ for (p =
val; *p !=
'\0'; p +=
strlen(p) +
1) {
* find the cpus attached to this EU and * update their mapping indices " not attached to a cpu node");
for (j = 0; j <
num; j++) {
* All the common setup of sun4v CPU modules is done by this routine. "failed or incorrect number of CPUs in MD");
* XXX Sun4v cpus don't have virtual caches * Get the valid mmu page sizes mask, Q sizes and isalist/r * from the MD for the first available CPU in cpulist. * Do not expect the MMU page sizes mask to be more than 32-bit. * If MD is broken then append the passed ISA set, * otherwise trust the MD. * ra_limit is the highest real address in the machine. * Block stores invalidate all pages of the d$ so pagecopy * et. al. do not need virtual translations with virtual * coloring taken into consideration. * The kpm mapping window. * The size of a single kpm range. * The overall size will be: kpm_size * vac_colors. * The virtual start address of the kpm range within the kernel * virtual address space. kpm_vbase has to be kpm_size aligned. * Make kpm_vbase, kpm_size aligned to kpm_size_shift. * To do this find the nearest power of 2 size that the * actual ra_limit fits within. * If it is an even power of two use that, otherwise use the * next power of two larger than ra_limit. * No virtual caches on sun4v so size matches size shift * kpm_base = hole_end + 1TB * Starting 1TB beyond where VA hole ends because on Niagara * processor software must not use pages within 4GB of the * VA hole as instruction pages to avoid problems with * prefetching into the VA hole. }
else {
/* Number of VA bits 64 ... no VA hole */ * The traptrace code uses either %tick or %stick for * timestamping. The sun4v require use of %stick. * sun4v provides demap_all * Get the nctxs from MD. If absent panic. * Initalize supported page sizes information. * Set to 0, if the page sizes mask information is absent in MD. * This routine gets the isalist information from MD and appends * the CPU module ISA set if required. * We support binaries for all the cpus that have shipped so far. * The kernel emulates instructions that are not supported by hardware. * Construct the space separated isa_list. * Allocate the buffer of MD isa buffer length + CPU module md_isalist[0] =
'\0';
/* create an empty string to start */ * Check if the isa_set is present in isalist returned by MD. * If yes, then no need to append it, if no then append it to * isalist returned by MD. /* Get rid of any trailing white spaces */ * This routine sets the globals for CPU and DEV mondo queue entries and * resumable and non-resumable error queue entries. /* Do not expect number of VA bits to be more than 32-bit quantity */ * Correct the value for VA bits on UltraSPARC-T1 based systems * This routine returns the L2 cache information such as -- associativity, * The "cache" node is optional in MD, therefore ncaches can be 0. /* If properties are missing from this cache ignore it */ * The broken_md_flag is set to 1, if the MD doesn't have * the domaining-enabled property in the platform node and the platforms * are Ontario and Erie. This flag is used to workaround some of the * incorrect MD properties. panic(
"platform name not found in machine description");
* If domaining-enable prop doesn't exist and the platform name is * Ontario or Erie the md is broken.