fillsysinfo.c revision f273041ff6419d6156c10c02bb1a527bfcfdc457
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <sys/promimpl.h>
#include <sys/machsystm.h>
#include <sys/cpu_module.h>
#include <vm/hat_sfmmu.h>
#include <sys/sysmacros.h>
#include <sys/mach_descrip.h>
#include <sys/archsystm.h>
int ncpunode;
static void set_at_flags(char *, int, char **);
uint64_t *);
int niobus = 0;
uint_t niommu_tsbs = 0;
/* prevent compilation with VAC defined */
#ifdef VAC
#error "The sun4v architecture does not support VAC"
#endif
#define S_VAC_SIZE MMU_PAGESIZE
#define S_VAC_SHIFT MMU_PAGESHIFT
int vac_size = S_VAC_SIZE;
int vac_shift = S_VAC_SHIFT;
void
{
}
void
{
char *namebuf;
char *namebufp;
int namelen;
return;
}
/* All out-of-range cpus will be stopped later. */
"cpu excluded from configuration\n", cpuid);
return;
}
"property");
}
namebufp += 5;
"fit into the cpunode name buffer");
"clock-frequency", &clk_freq)) {
clk_freq = 0;
}
/*
* Compute scaling factor based on rate of %tick. This is used
* to convert from ticks derived from %tick to nanoseconds. See
*/
/*
* The nodeid is not used in sun4v at all. Setting it
* to positive value to make starting of slave CPUs
* code happy.
*/
/*
* Obtain the L2 cache information from MD.
* If "Cache" node exists, then set L2 cache properties
* as read from MD.
* If node does not exists, then set the L2 cache properties
* in individual CPU module.
*/
} else {
/*
* Do not expect L2 cache properties to be bigger
* than 32-bit quantity.
*/
}
/*
* Start off by assigning the cpu id as the default
* mapping index.
*/
if (ecache_setsize == 0)
if (ecache_alignsize == 0)
ncpunode++;
}
void
{
ncpunode--;
}
void
{
int idx, i, j;
/*
* Find the cpu integer exec units - and
* setup the mappings appropriately.
*/
if (num < 1)
if (num > 1)
" description");
"fwd", &eunit);
if (num_eunits > 0) {
/* Spin through and find all the integer exec units */
for (i = 0; i < num_eunits; i++) {
char *p;
char *val;
int vallen;
/* ignore nodes with no type */
if (strcmp(p, match_type) == 0)
goto found;
}
continue;
/*
* find the cpus attached to this EU and
* update their mapping indices
*/
"back", &node);
if (num < 1)
" not attached to a cpu node");
for (j = 0; j < num; j++) {
&lcpuid))
continue;
continue;
}
}
}
}
/*
* All the common setup of sun4v CPU modules is done by this routine.
*/
void
cpu_setup_common(char **cpu_module_isa_set)
{
extern int disable_delay_tlb_flush, delay_tlb_flush;
extern int mmu_exported_pagesize_mask;
int nocpus, i;
if (nocpus < 1) {
"failed or incorrect number of CPUs in MD");
}
if (use_page_coloring) {
do_pg_coloring = 1;
if (use_virtual_coloring) {
/*
* XXX Sun4v cpus don't have virtual caches
*/
do_virtual_coloring = 1;
}
}
/*
* Get the valid mmu page sizes mask, Q sizes and isalist/r
* from the MD for the first available CPU in cpulist.
*
* Do not expect the MMU page sizes mask to be more than 32-bit.
*/
for (i = 0; i < nocpus; i++)
/*
* If MD is broken then append the passed ISA set,
* otherwise trust the MD.
*/
if (broken_md_flag)
else
/*
* ra_limit is the highest real address in the machine.
*/
(void) md_fini_handle(mdp);
/*
* Block stores invalidate all pages of the d$ so pagecopy
* et. al. do not need virtual translations with virtual
* coloring taken into consideration.
*/
/*
* The kpm mapping window.
* kpm_size:
* The size of a single kpm range.
* The overall size will be: kpm_size * vac_colors.
* kpm_vbase:
* The virtual start address of the kpm range within the kernel
* virtual address space. kpm_vbase has to be kpm_size aligned.
*/
/*
* Make kpm_vbase, kpm_size aligned to kpm_size_shift.
* To do this find the nearest power of 2 size that the
* actual ra_limit fits within.
* If it is an even power of two use that, otherwise use the
* next power of two larger than ra_limit.
*/
/*
* No virtual caches on sun4v so size matches size shift
*/
if (va_bits < VA_ADDRESS_SPACE_BITS) {
/*
* In case of VA hole
* kpm_base = hole_end + 1TB
* Starting 1TB beyond where VA hole ends because on Niagara
* processor software must not use pages within 4GB of the
* VA hole as instruction pages to avoid problems with
* prefetching into the VA hole.
*/
(1ull << 40));
} else { /* Number of VA bits 64 ... no VA hole */
}
/*
* The traptrace code uses either %tick or %stick for
* timestamping. The sun4v require use of %stick.
*/
traptrace_use_stick = 1;
/*
* sun4v provides demap_all
*/
if (!disable_delay_tlb_flush)
delay_tlb_flush = 1;
}
/*
* Get the nctxs from MD. If absent panic.
*/
static uint64_t
{
&ctx_bits))
ctx_bits = 0;
"returned by MD", ctx_bits);
return (ctx_bits);
}
/*
* Initalize supported page sizes information.
* Set to 0, if the page sizes mask information is absent in MD.
*/
static uint64_t
{
mmu_page_size_list = 0;
"by MD", mmu_page_size_list);
return (mmu_page_size_list);
}
/*
* This routine gets the isalist information from MD and appends
* the CPU module ISA set if required.
*/
static char *
char **cpu_module_isa_set)
{
extern int at_flags;
char *md_isalist;
int md_isalen;
char *isabuf;
int isalen;
char **isa_set;
char *p, *q;
int cpu_module_isalen = 0, found = 0;
/*
* We support binaries for all the cpus that have shipped so far.
* The kernel emulates instructions that are not supported by hardware.
*/
/*
* Construct the space separated isa_list.
*/
if (cpu_module_isa_set != NULL) {
isa_set++) {
cpu_module_isalen++; /* for space character */
}
}
/*
* Allocate the buffer of MD isa buffer length + CPU module
* isa buffer length.
*/
if (md_isalist == NULL)
"md_isalist");
}
/*
* Check if the isa_set is present in isalist returned by MD.
* If yes, then no need to append it, if no then append it to
* isalist returned by MD.
*/
if (cpu_module_isa_set != NULL) {
isa_set++) {
found = 0;
p += strlen(p) + 1) {
found = 1;
break;
}
}
if (!found) {
}
}
}
/* Get rid of any trailing white spaces */
return (md_isalist);
}
{
int i;
int memnodes;
int nmblock;
if (nmblock < 1)
for (i = 0; i < nmblock; i++) {
" mblock node");
" mblock node");
}
if (ra_limit > MAX_REAL_ADDRESS) {
" clipping to %llx\n", MAX_REAL_ADDRESS);
}
return (ra_limit);
}
/*
* This routine sets the globals for CPU and DEV mondo queue entries and
* resumable and non-resumable error queue entries.
*
* First, look up the number of bits available to pass an entry number.
* This can vary by platform and may result in allocating an unreasonably
* (or impossibly) large amount of memory for the corresponding table,
* so we clamp it by 'max_entries'. If the prop is missing, use
* 'default_entries'.
*/
static uint64_t
{
if (default_entries > max_entries)
if (!broken_md_flag)
qnamep);
} else {
}
return (entries);
}
/* Scaling constant used to compute size of cpu mondo queue */
#define CPU_MONDO_Q_MULTIPLIER 8
static void
{
int nrnode;
/*
* Compute the maximum number of entries for the cpu mondo queue.
* Use the appropriate property in the platform node, if it is
* available. Else, base it on NCPU.
*/
}
static void
{
/* Do not expect number of VA bits to be more than 32-bit quantity */
/*
* Correct the value for VA bits on UltraSPARC-T1 based systems
* in case of broken MD.
*/
if (broken_md_flag)
}
/*
* This routine returns the L2 cache information such as -- associativity,
* size and linesize.
*/
static int
{
int ncaches, i;
"fwd", &cachelist);
/*
* The "cache" node is optional in MD, therefore ncaches can be 0.
*/
if (ncaches < 1) {
return (0);
}
max_level = 0;
for (i = 0; i < ncaches; i++) {
continue;
if (cache_level <= max_level) continue;
/* If properties are missing from this cache ignore it */
"associativity", &local_assoc))) {
continue;
}
"size", &local_size))) {
continue;
}
"line-size", &local_lsize))) {
continue;
}
*size = local_size;
*linesize = local_lsize;
}
return ((max_level > 0) ? 1 : 0);
}
/*
* Set the broken_md_flag to 1 if the MD doesn't have
* the domaining-enabled property in the platform node and the
* platform uses the UltraSPARC-T1 cpu. This flag is used to
* workaround some of the incorrect MD properties.
*/
static void
{
int nrnode;
char *namebuf;
int namelen;
&platlist);
if (nrnode < 1)
"Cannot read 'compatible' property of 'cpu' node");
}
broken_md_flag = 1;
}