sun4v/os/cmp.c

	cmp.c revision 0e7515250c8395f368aa45fb9acae7c4f8f8b786
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq/*
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * CDDL HEADER START
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq *
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * The contents of this file are subject to the terms of the
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * Common Development and Distribution License (the "License").
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * You may not use this file except in compliance with the License.
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq *
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * or http://www.opensolaris.org/os/licensing.
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * See the License for the specific language governing permissions
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * and limitations under the License.
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq *
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * When distributing Covered Code, include this CDDL HEADER in each
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * If applicable, add the following below this CDDL HEADER, with the
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * fields enclosed by brackets "[]" replaced with your own identifying
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * information: Portions Copyright [yyyy] [name of copyright owner]
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq *
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * CDDL HEADER END
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq */
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq/*
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
55f5292c612446ce6f93ddd248c0019b5974618bFrank Van Der Linden * Use is subject to license terms.
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq */
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq#include <sys/types.h>
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq#include <sys/machsystm.h>
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq#include <sys/cmp.h>
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq#include <sys/cmt.h>
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq/*
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * Note: For now assume the chip ID as 0 for all the cpus until additional
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * information is available via machine description table
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq */
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq/*
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * Returns 1 if cpuid is CMP-capable, 0 otherwise.
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq */
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq/*ARGSUSED*/
c7158ae983f5a04c4a998f468ecefba6d23ba721tariqint
c7158ae983f5a04c4a998f468ecefba6d23ba721tariqcmp_cpu_is_cmp(processorid_t cpuid)
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq{
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq    return (0);
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq}
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq/*
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * Indicate that this core (cpuid) resides on the chip indicated by chipid.
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * Called during boot and DR add.
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq */
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq/*ARGSUSED*/
c7158ae983f5a04c4a998f468ecefba6d23ba721tariqvoid
c7158ae983f5a04c4a998f468ecefba6d23ba721tariqcmp_add_cpu(chipid_t chipid, processorid_t cpuid)
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq{
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq}
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq/*
121d13daefbeb0546d0d9c6ef16c753aa6890290Frank Van Der Linden * Indicate that this core (cpuid) is being DR removed.
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq */
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq/*ARGSUSED*/
c7158ae983f5a04c4a998f468ecefba6d23ba721tariqvoid
c7158ae983f5a04c4a998f468ecefba6d23ba721tariqcmp_delete_cpu(processorid_t cpuid)
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq{
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq}
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq/*
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * Called when cpuid is being onlined or offlined.  If the offlined
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * processor is CMP-capable then current target of the CMP Error Steering
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * Register is set to either the lowest numbered on-line sibling core, if
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * one exists, or else to this core.
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq */
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq/*ARGSUSED*/
c7158ae983f5a04c4a998f468ecefba6d23ba721tariqvoid
c7158ae983f5a04c4a998f468ecefba6d23ba721tariqcmp_error_resteer(processorid_t cpuid)
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq{
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq}
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq/*
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * Return 0, shortterm workaround until MD table is updated
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq * to provide cpu-chip mapping
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq */
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq/*ARGSUSED*/
c7158ae983f5a04c4a998f468ecefba6d23ba721tariqchipid_t
c7158ae983f5a04c4a998f468ecefba6d23ba721tariqcmp_cpu_to_chip(processorid_t cpuid)
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq{
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq    return (cpu[cpuid]->cpu_m.cpu_chip);
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq}
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq/*ARGSUSED*/
c7158ae983f5a04c4a998f468ecefba6d23ba721tariqint
c7158ae983f5a04c4a998f468ecefba6d23ba721tariqpg_plat_hw_shared(cpu_t *cp, pghw_type_t hw)
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq{
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq    switch (hw) {
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq    case PGHW_IPIPE:
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq        return (1);
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq    case PGHW_FPU:
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq        return (1);
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq    case PGHW_MPIPE:
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq        return (1);
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq    }
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq    return (0);
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq}
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq
c7158ae983f5a04c4a998f468ecefba6d23ba721tariqint
c7158ae983f5a04c4a998f468ecefba6d23ba721tariqpg_plat_cpus_share(cpu_t *cpu_a, cpu_t *cpu_b, pghw_type_t hw)
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq{
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq    if (pg_plat_hw_shared(cpu_a, hw) == 0 ||
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq        pg_plat_hw_shared(cpu_b, hw) == 0)
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq        return (0);
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq    return (pg_plat_hw_instance_id(cpu_a, hw) ==
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq        pg_plat_hw_instance_id(cpu_b, hw));
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq}
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq
c7158ae983f5a04c4a998f468ecefba6d23ba721tariqid_t
c7158ae983f5a04c4a998f468ecefba6d23ba721tariqpg_plat_hw_instance_id(cpu_t *cpu, pghw_type_t hw)
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq{
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq    switch (hw) {
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq    case PGHW_IPIPE:
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq        return (cpu->cpu_m.cpu_ipipe);
c7158ae983f5a04c4a998f468ecefba6d23ba721tariq    case PGHW_CHIP:
        return (cpu->cpu_m.cpu_chip);
    case PGHW_MPIPE:
        return (cpu->cpu_m.cpu_mpipe);
    case PGHW_FPU:
        return (cpu->cpu_m.cpu_fpu);
    default:
        return (-1);
    }
}

/*
 * Rank the relative importance of optimizing for hw1 or hw2
 */
pghw_type_t
pg_plat_hw_rank(pghw_type_t hw1, pghw_type_t hw2)
{
    int i;
    int rank1 = 0;
    int rank2 = 0;

    static pghw_type_t hw_hier[] = {
        PGHW_IPIPE,
        PGHW_FPU,
        PGHW_MPIPE,
        PGHW_NUM_COMPONENTS
    };

    for (i = 0; hw_hier[i] != PGHW_NUM_COMPONENTS; i++) {
        if (hw_hier[i] == hw1)
            rank1 = i;
        if (hw_hier[i] == hw2)
            rank2 = i;
    }
    if (rank1 > rank2)
        return (hw1);
    else
        return (hw2);
}

/*
 * Override the default CMT dispatcher policy for the specified
 * hardware sharing relationship
 */
/* ARGSUSED */
pg_cmt_policy_t
pg_plat_cmt_policy(pghw_type_t hw)
{
    /* Accept the default policies */
    return (CMT_NO_POLICY);
}

id_t
pg_plat_get_core_id(cpu_t *cpu)
{
    return (cpu->cpu_m.cpu_core);
}

void
cmp_set_nosteal_interval(void)
{
    nosteal_nsec = 0;
}
/*
 * Return 1 if CMT load balancing policies should be
 * implemented across instances of the specified hardware
 * sharing relationship.
 */
int
pg_cmt_load_bal_hw(pghw_type_t hw)
{
    if (hw == PGHW_IPIPE ||
        hw == PGHW_FPU ||
        hw == PGHW_MPIPE)
        return (1);
    else
        return (0);
}
/*
 * Return 1 if thread affinity policies should be implemented
 * for instances of the specifed hardware sharing relationship.
 */
int
pg_cmt_affinity_hw(pghw_type_t hw)
{
    if (hw == PGHW_CACHE)
        return (1);
    else
        return (0);
}