* The contents of this file are subject to the terms of the * Common Development and Distribution License (the "License"). * You may not use this file except in compliance with the License. * See the License for the specific language governing permissions * and limitations under the License. * When distributing Covered Code, include this CDDL HEADER in each * If applicable, add the following below this CDDL HEADER, with the * fields enclosed by brackets "[]" replaced with your own identifying * information: Portions Copyright [yyyy] [name of copyright owner] * Copyright 2009 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. * Note: For now assume the chip ID as 0 for all the cpus until additional * information is available via machine description table * Returns 1 if cpuid is CMP-capable, 0 otherwise. * Indicate that this core (cpuid) resides on the chip indicated by chipid. * Called during boot and DR add. * Indicate that this core (cpuid) is being DR removed. * Called when cpuid is being onlined or offlined. If the offlined * processor is CMP-capable then current target of the CMP Error Steering * Register is set to either the lowest numbered on-line sibling core, if * one exists, or else to this core. * Return 0, shortterm workaround until MD table is updated * to provide cpu-chip mapping * Rank the relative importance of optimizing for hw1 or hw2 * Override the default CMT dispatcher policy for the specified * hardware sharing relationship /* Accept the default policies */ * Return 1 if CMT load balancing policies should be * implemented across instances of the specified hardware * Return 1 if thread affinity policies should be implemented * for instances of the specifed hardware sharing relationship. * Return number of counter events requested to measure hardware capacity and * utilization and setup CPC requests for specified CPU if list where to add /* LINTED E_FUNC_ARG_UNUSED */ * Return error to tell common code to decide what counter events to * program on this CPU for measuring hardware capacity and utilization