hcall.s revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* Hypervisor calls
*/
#include <sys/asm_linkage.h>
#include <sys/machparam.h>
#include <sys/hypervisor_api.h>
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0);}
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
#ifdef SET_MMU_STATS
/*ARGSUSED*/
{ return (0); }
#endif /* SET_MMU_STATS */
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
hv_cpu_yield(void)
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
#else /* lint || __lint */
/*
* %o0 - character
*/
/*
* %o0 pointer to character buffer
* return values:
* 0 success
* hv_errno failure
*/
be 1f
be 1f
1:
/*
* Map permanent address
* arg0 vaddr (%o0)
* arg1 context (%o1)
* arg2 tte (%o2)
* arg3 flags (%o3) 0x1=d 0x2=i
*/
/*
* Unmap permanent address
* arg0 vaddr (%o0)
* arg1 context (%o1)
* arg2 flags (%o2) 0x1=d 0x2=i
*/
/*
* Set TSB for context 0
* arg0 ntsb_descriptor (%o0)
* arg1 desc_ra (%o1)
*/
/*
* Set TSB for context non0
* arg0 ntsb_descriptor (%o0)
* arg1 desc_ra (%o1)
*/
#ifdef SET_MMU_STATS
/*
* Returns old stat area on success
*/
#endif /* SET_MMU_STATS */
/*
* CPU Q Configure
* arg0 queue (%o0)
* arg1 Base address RA (%o1)
* arg2 Size (%o2)
*/
/*
* arg0 - devhandle
* arg1 - pci_device
* arg2 - pci_config_offset
* arg3 - pci_config_size
*
* ret0 - status
* ret1 - error_flag
* ret2 - pci_cfg_data
*/
1: retl
/*
* arg0 - devhandle
* arg1 - pci_device
* arg2 - pci_config_offset
* arg3 - pci_config_size
* arg4 - pci_cfg_data
*
* ret0 - status
* ret1 - error_flag
*/
/*
* arg0 - devhandle
* arg1 - devino
*
* ret0 - status
* ret1 - sysino
*/
1: retl
/*
* arg0 - sysino
*
* ret0 - status
* ret1 - intr_valid_state
*/
1: retl
/*
* arg0 - sysino
* arg1 - intr_valid_state
*
* ret0 - status
*/
/*
* arg0 - sysino
*
* ret0 - status
* ret1 - intr_state
*/
1: retl
/*
* arg0 - sysino
* arg1 - intr_state
*
* ret0 - status
*/
/*
* arg0 - sysino
*
* ret0 - status
* ret1 - cpu_id
*/
1: retl
/*
* arg0 - sysino
* arg1 - cpu_id
*
* ret0 - status
*/
/*
* arg0 - devhandle
* arg1 - tsbid
* arg2 - pages
* arg3 - io_attributes
* arg4 - io_page_list_p
*
* ret1 - pages_mapped
*/
1:
/*
* arg0 - devhandle
* arg1 - tsbid
* arg2 - pages
*
* ret1 - pages_demapped
*/
1: retl
/*
* arg0 - devhandle
* arg1 - tsbid
*
*
* ret0 - status
* ret1 - io_attributes
* ret2 - r_addr
*/
1:
/*
* arg0 - devhandle
* arg1 - r_addr
* arg2 - io_attributes
*
*
* ret0 - status
* ret1 - io_addr
*/
1: retl
/*
* arg0 - devhandle
* arg1 - r_addr
* arg2 - size
*
* ret1 - error_flag
* ret2 - data
*/
1:
/*
* arg0 - devhandle
* arg1 - r_addr
* arg2 - sizes
* arg3 - data
* arg4 - r_addr2
*
* ret1 - error_flag
*/
1:
/*
* arg0 - devhandle
* arg1 - r_addr
* arg2 - num_bytes
* arg3 - io_sync_direction
*
* ret0 - status
* ret1 - bytes_synched
*/
1: retl
/*
* arg0 - devhandle
* arg1 - msiq_id
* arg2 - r_addr
* arg3 - nentries
*
* ret0 - status
*/
/*
* arg0 - devhandle
* arg1 - msiq_id
*
* ret0 - status
* ret1 - r_addr
* ret1 - nentries
*/
brnz 1f
1: retl
/*
* arg0 - devhandle
* arg1 - msiq_id
*
* ret0 - status
* ret1 - msiq_valid_state
*/
1: retl
/*
* arg0 - devhandle
* arg1 - msiq_id
* arg2 - msiq_valid_state
*
* ret0 - status
*/
/*
* arg0 - devhandle
* arg1 - msiq_id
*
* ret0 - status
* ret1 - msiq_state
*/
1: retl
/*
* arg0 - devhandle
* arg1 - msiq_id
* arg2 - msiq_state
*
* ret0 - status
*/
/*
* arg0 - devhandle
* arg1 - msiq_id
*
* ret0 - status
* ret1 - msiq_head
*/
1: retl
/*
* arg0 - devhandle
* arg1 - msiq_id
* arg2 - msiq_head
*
* ret0 - status
*/
/*
* arg0 - devhandle
* arg1 - msiq_id
*
* ret0 - status
* ret1 - msiq_tail
*/
1: retl
/*
* arg0 - devhandle
* arg1 - msi_num
*
* ret0 - status
* ret1 - msiq_id
*/
1: retl
/*
* arg0 - devhandle
* arg1 - msi_num
* arg2 - msiq_id
* arg2 - msitype
*
* ret0 - status
*/
/*
* arg0 - devhandle
* arg1 - msi_num
*
* ret0 - status
* ret1 - msi_valid_state
*/
1: retl
/*
* arg0 - devhandle
* arg1 - msi_num
* arg2 - msi_valid_state
*
* ret0 - status
*/
/*
* arg0 - devhandle
* arg1 - msi_num
*
* ret0 - status
* ret1 - msi_state
*/
1: retl
/*
* arg0 - devhandle
* arg1 - msi_num
* arg2 - msi_state
*
* ret0 - status
*/
/*
* arg0 - devhandle
* arg1 - msg_type
*
* ret0 - status
* ret1 - msiq_id
*/
1: retl
/*
* arg0 - devhandle
* arg1 - msg_type
* arg2 - msiq_id
*
* ret0 - status
*/
/*
* arg0 - devhandle
* arg1 - msg_type
*
* ret0 - status
* ret1 - msg_valid_state
*/
1: retl
/*
* arg0 - devhandle
* arg1 - msg_type
* arg2 - msg_valid_state
*
* ret0 - status
*/
/*
* hv_cpu_yield(void)
*/
#ifdef NIAGARA_ERRATUM_39
/*
* If niagara_erratum_39 is set, then we need to halt the strand by
* executing a synthetic "halt" instruction which maps to a
* wrasr %asr26 with a data value which has bit 0 clear.
*
* Note that we don't halt the strand if there are any pending
* soft interrupts (%asr22).
*/
brnz %o1, 1f
nop
wr %o0, %asr26 ! halt the strand
1:
mov %g0, %o0
retl
nop
2:
#endif /* NIAGARA_ERRATUM_39 */
mov HV_CPU_YIELD, %o5
ta FAST_TRAP
retl
nop
SET_SIZE(hv_cpu_yield)
/*
* hv_service_recv(uint64_t s_id, uint64_t buf_pa,
* uint64_t size, uint64_t *recv_bytes);
*/
ENTRY(hv_service_recv)
save %sp, -SA(MINFRAME), %sp
mov %i0, %o0
mov %i1, %o1
mov %i2, %o2
mov %i3, %o3
mov SVC_RECV, %o5
ta FAST_TRAP
brnz %o0, 1f
mov %o0, %i0
stx %o1, [%i3]
1:
ret
restore
SET_SIZE(hv_service_recv)
/*
* hv_service_send(uint64_t s_id, uint64_t buf_pa,
* uint64_t size, uint64_t *recv_bytes);
*/
ENTRY(hv_service_send)
save %sp, -SA(MINFRAME), %sp
mov %i0, %o0
mov %i1, %o1
mov %i2, %o2
mov %i3, %o3
mov SVC_SEND, %o5
ta FAST_TRAP
brnz %o0, 1f
mov %o0, %i0
stx %o1, [%i3]
1:
ret
restore
SET_SIZE(hv_service_send)
/*
* hv_service_getstatus(uint64_t s_id, uint64_t *vreg);
*/
ENTRY(hv_service_getstatus)
mov %o1, %o4 ! save datap
mov SVC_GETSTATUS, %o5
ta FAST_TRAP
brz,a %o0, 1f
stx %o1, [%o4]
1:
retl
nop
SET_SIZE(hv_service_getstatus)
/*
* hv_service_clrstatus(uint64_t s_id, uint64_t bits);
*/
ENTRY(hv_service_clrstatus)
mov SVC_CLRSTATUS, %o5
ta FAST_TRAP
retl
nop
SET_SIZE(hv_service_clrstatus)
/*
* int hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state);
*/
ENTRY(hv_cpu_state)
mov %o1, %o4 ! save datap
mov HV_CPU_STATE, %o5
ta FAST_TRAP
brz,a %o0, 1f
stx %o1, [%o4]
1:
retl
nop
SET_SIZE(hv_cpu_state)
/*
* HV state dump zone Configure
* arg0 real adrs of dump buffer (%o0)
* arg1 size of dump buffer (%o1)
* ret0 status (%o0)
* ret1 size of buffer on success and min size on EINVAL (%o1)
* hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *ret_size)
*/
ENTRY(hv_dump_buf_update)
mov DUMP_BUF_UPDATE, %o5
ta FAST_TRAP
retl
stx %o1, [%o2]
SET_SIZE(hv_dump_buf_update)
/*
* For memory scrub
* int hv_mem_scrub(uint64_t real_addr, uint64_t length,
* uint64_t *scrubbed_len);
* Retun %o0 -- status
* %o1 -- bytes scrubbed
*/
ENTRY(hv_mem_scrub)
mov %o2, %o4
mov HV_MEM_SCRUB, %o5
ta FAST_TRAP
retl
stx %o1, [%o4]
SET_SIZE(hv_mem_scrub)
/*
* Flush ecache
* int hv_mem_sync(uint64_t real_addr, uint64_t length,
* uint64_t *flushed_len);
* Retun %o0 -- status
* %o1 -- bytes flushed
*/
ENTRY(hv_mem_sync)
mov %o2, %o4
mov HV_MEM_SYNC, %o5
ta FAST_TRAP
retl
stx %o1, [%o4]
SET_SIZE(hv_mem_sync)
/*
* TTRACE_BUF_CONF Configure
* arg0 RA base of buffer (%o0)
* arg1 buf size in no. of entries (%o1)
* ret0 status (%o0)
* ret1 minimum size in no. of entries on failure,
* actual size in no. of entries on success (%o1)
*/
ENTRY(hv_ttrace_buf_conf)
mov TTRACE_BUF_CONF, %o5
ta FAST_TRAP
retl
stx %o1, [%o2]
SET_SIZE(hv_ttrace_buf_conf)
/*
* TTRACE_BUF_INFO
* ret0 status (%o0)
* ret1 RA base of buffer (%o1)
* ret2 size in no. of entries (%o2)
*/
ENTRY(hv_ttrace_buf_info)
mov %o0, %o3
mov %o1, %o4
mov TTRACE_BUF_INFO, %o5
ta FAST_TRAP
stx %o1, [%o3]
retl
stx %o2, [%o4]
SET_SIZE(hv_ttrace_buf_info)
/*
* TTRACE_ENABLE
* arg0 enable/ disable (%o0)
* ret0 status (%o0)
* ret1 previous enable state (%o1)
*/
ENTRY(hv_ttrace_enable)
mov %o1, %o2
mov TTRACE_ENABLE, %o5
ta FAST_TRAP
retl
stx %o1, [%o2]
SET_SIZE(hv_ttrace_enable)
/*
* TTRACE_FREEZE
* arg0 enable/ freeze (%o0)
* ret0 status (%o0)
* ret1 previous freeze state (%o1)
*/
ENTRY(hv_ttrace_freeze)
mov %o1, %o2
mov TTRACE_FREEZE, %o5
ta FAST_TRAP
retl
stx %o1, [%o2]
SET_SIZE(hv_ttrace_freeze)
/*
* MACH_DESC
* arg0 buffer real address
* arg1 pointer to uint64_t for size of buffer
* ret0 status
* ret1 return required size of buffer / returned data size
*/
ENTRY(hv_mach_desc)
mov %o1, %o4 ! save datap
ldx [%o1], %o1
mov HV_MACH_DESC, %o5
ta FAST_TRAP
retl
stx %o1, [%o4]
SET_SIZE(hv_mach_desc)
/*
* hv_ncs_request(int cmd, uint64_t realaddr, size_t sz)
*/
ENTRY(hv_ncs_request)
mov HV_NCS_REQUEST, %o5
ta FAST_TRAP
retl
nop
SET_SIZE(hv_ncs_request)
#ifdef NIAGARA_ERRATUM_39
.seg ".data"
.align 4
.global niagara_erratum_39
niagara_erratum_39:
.word 0
.seg ".text"
#endif
#endif /* lint || __lint */