px_hcall.s revision c9eab9d4e096bb9b983e9b007577edfa73c32eff
0N/A/*
196N/A * CDDL HEADER START
0N/A *
0N/A * The contents of this file are subject to the terms of the
0N/A * Common Development and Distribution License (the "License").
0N/A * You may not use this file except in compliance with the License.
0N/A *
0N/A * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
0N/A * or http://www.opensolaris.org/os/licensing.
0N/A * See the License for the specific language governing permissions
0N/A * and limitations under the License.
0N/A *
0N/A * When distributing Covered Code, include this CDDL HEADER in each
0N/A * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
0N/A * If applicable, add the following below this CDDL HEADER, with the
0N/A * fields enclosed by brackets "[]" replaced with your own identifying
0N/A * information: Portions Copyright [yyyy] [name of copyright owner]
0N/A *
0N/A * CDDL HEADER END
0N/A */
0N/A/*
0N/A * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
0N/A * Use is subject to license terms.
0N/A */
0N/A
0N/A
0N/A/*
0N/A * Hypervisor calls called by px nexus driver.
0N/A*/
0N/A
0N/A#include <sys/asm_linkage.h>
0N/A#include <sys/hypervisor_api.h>
0N/A#include <sys/dditypes.h>
0N/A#include <px_ioapi.h>
0N/A#include "px_lib4v.h"
0N/A
0N/A#if defined(lint) || defined(__lint)
0N/A
0N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, pci_config_offset_t off,
0N/A pci_config_size_t size, pci_cfg_data_t *data_p)
0N/A{ return (0); }
0N/A
0N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, pci_config_offset_t off,
0N/A pci_config_size_t size, pci_cfg_data_t data)
0N/A{ return (0); }
0N/A
0N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages,
0N/A io_attributes_t attr, io_page_list_t *io_page_list_p,
0N/A pages_t *pages_mapped)
0N/A{ return (0); }
0N/A
0N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages,
304N/A pages_t *pages_demapped)
304N/A{ return (0); }
304N/A
304N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, io_attributes_t *attr_p,
0N/A r_addr_t *r_addr_p)
0N/A{ return (0); }
0N/A
0N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, io_attributes_t attr,
0N/A io_addr_t *io_addr_p)
0N/A{ return (0); }
304N/A
304N/A/*ARGSUSED*/
304N/Auint64_t
304N/Ahvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, uint32_t *status,
304N/A uint64_t *data_p)
304N/A{ return (0); }
304N/A
304N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_poke(devhandle_t dev_hdl, r_addr_t ra, uint64_t sizes, uint64_t data,
0N/A r_addr_t ra2, uint32_t *rdbk_status)
0N/A{ return (0); }
0N/A
0N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, size_t num_bytes,
0N/A io_sync_direction_t io_sync_direction, size_t *bytes_synched)
0N/A{ return (0); }
0N/A
0N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t ra,
0N/A uint_t msiq_rec_cnt)
0N/A{ return (0); }
0N/A
0N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t *r_addr_p,
0N/A uint_t *msiq_rec_cnt_p)
0N/A{ return (0); }
0N/A
0N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
0N/A pci_msiq_valid_state_t *msiq_valid_state)
0N/A{ return (0); }
0N/A
0N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
304N/A pci_msiq_valid_state_t msiq_valid_state)
304N/A{ return (0); }
304N/A
304N/A/*ARGSUSED*/
304N/Auint64_t
304N/Ahvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id,
304N/A pci_msiq_state_t *msiq_state)
304N/A{ return (0); }
0N/A
0N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id,
304N/A pci_msiq_state_t msiq_state)
0N/A{ return (0); }
0N/A
304N/A/*ARGSUSED*/
304N/Auint64_t
304N/Ahvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id,
304N/A msiqhead_t *msiq_head)
304N/A{ return (0); }
304N/A
0N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id,
0N/A msiqhead_t msiq_head)
0N/A{ return (0); }
0N/A
0N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id,
0N/A msiqtail_t *msiq_tail)
0N/A{ return (0); }
0N/A
0N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num,
0N/A msiqid_t *msiq_id)
0N/A{ return (0); }
304N/A
304N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num,
0N/A msiqid_t msiq_id, msi_type_t msitype)
0N/A{ return (0); }
0N/A
0N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num,
0N/A pci_msi_valid_state_t *msi_valid_state)
304N/A{ return (0); }
304N/A
304N/A/*ARGSUSED*/
304N/Auint64_t
304N/Ahvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num,
0N/A pci_msi_valid_state_t msi_valid_state)
0N/A{ return (0); }
304N/A
304N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num,
0N/A pci_msi_state_t *msi_state)
0N/A{ return (0); }
0N/A
0N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num,
0N/A pci_msi_state_t msi_state)
0N/A{ return (0); }
0N/A
0N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
0N/A msiqid_t *msiq_id)
0N/A{ return (0); }
0N/A
0N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
0N/A msiqid_t msiq_id)
0N/A{ return (0); }
0N/A
0N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
0N/A pcie_msg_valid_state_t *msg_valid_state)
0N/A{ return (0); }
0N/A
0N/A/*ARGSUSED*/
0N/Auint64_t
0N/Ahvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
0N/A pcie_msg_valid_state_t msg_valid_state)
0N/A{ return (0); }
0N/A
0N/A/*
0N/A * First arg to both of these functions is a dummy, to accomodate how
0N/A * hv_hpriv() works.
0N/A */
0N/A/*ARGSUSED*/
0N/Aint
0N/Apx_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr)
0N/A{ return (0); }
0N/A
0N/A#else /* lint || __lint */
0N/A
0N/A /*
0N/A * arg0 - devhandle
0N/A * arg1 - pci_device
0N/A * arg2 - pci_config_offset
0N/A * arg3 - pci_config_size
0N/A *
0N/A * ret0 - status
0N/A * ret1 - error_flag
0N/A * ret2 - pci_cfg_data
0N/A */
0N/A ENTRY(hvio_config_get)
0N/A mov HVIO_CONFIG_GET, %o5
0N/A ta FAST_TRAP
0N/A brnz %o0, 1f
0N/A movrnz %o1, -1, %o2
0N/A brz,a %o1, 1f
0N/A stuw %o2, [%o4]
0N/A1: retl
0N/A nop
0N/A SET_SIZE(hvio_config_get)
0N/A
0N/A /*
0N/A * arg0 - devhandle
0N/A * arg1 - pci_device
0N/A * arg2 - pci_config_offset
0N/A * arg3 - pci_config_size
0N/A * arg4 - pci_cfg_data
0N/A *
0N/A * ret0 - status
0N/A * ret1 - error_flag
0N/A */
0N/A ENTRY(hvio_config_put)
0N/A mov HVIO_CONFIG_PUT, %o5
0N/A ta FAST_TRAP
0N/A retl
0N/A nop
0N/A SET_SIZE(hvio_config_put)
0N/A
0N/A /*
0N/A * arg0 - devhandle
0N/A * arg1 - tsbid
0N/A * arg2 - pages
0N/A * arg3 - io_attributes
0N/A * arg4 - io_page_list_p
0N/A *
0N/A * ret1 - pages_mapped
0N/A */
0N/A ENTRY(hvio_iommu_map)
0N/A save %sp, -SA(MINFRAME64), %sp
0N/A mov %i0, %o0
0N/A mov %i1, %o1
0N/A mov %i2, %o2
0N/A mov %i3, %o3
0N/A mov %i4, %o4
0N/A mov HVIO_IOMMU_MAP, %o5
0N/A ta FAST_TRAP
0N/A brnz %o0, 1f
0N/A mov %o0, %i0
0N/A stuw %o1, [%i5]
0N/A1:
0N/A ret
0N/A restore
0N/A SET_SIZE(hvio_iommu_map)
0N/A
0N/A /*
0N/A * arg0 - devhandle
0N/A * arg1 - tsbid
0N/A * arg2 - pages
0N/A *
0N/A * ret1 - pages_demapped
0N/A */
0N/A ENTRY(hvio_iommu_demap)
0N/A mov HVIO_IOMMU_DEMAP, %o5
0N/A ta FAST_TRAP
0N/A brz,a %o0, 1f
0N/A stuw %o1, [%o3]
0N/A1: retl
0N/A nop
0N/A SET_SIZE(hvio_iommu_demap)
0N/A
0N/A /*
0N/A * arg0 - devhandle
0N/A * arg1 - tsbid
0N/A *
0N/A *
0N/A * ret0 - status
0N/A * ret1 - io_attributes
0N/A * ret2 - r_addr
0N/A */
0N/A ENTRY(hvio_iommu_getmap)
0N/A mov %o2, %o4
0N/A mov HVIO_IOMMU_GETMAP, %o5
0N/A ta FAST_TRAP
0N/A brnz %o0, 1f
0N/A nop
0N/A stx %o2, [%o3]
0N/A st %o1, [%o4]
0N/A1:
0N/A retl
0N/A nop
0N/A SET_SIZE(hvio_iommu_getmap)
0N/A
0N/A /*
0N/A * arg0 - devhandle
0N/A * arg1 - r_addr
0N/A * arg2 - io_attributes
0N/A *
0N/A *
0N/A * ret0 - status
0N/A * ret1 - io_addr
0N/A */
0N/A ENTRY(hvio_iommu_getbypass)
0N/A mov HVIO_IOMMU_GETBYPASS, %o5
0N/A ta FAST_TRAP
0N/A brz,a %o0, 1f
0N/A stx %o1, [%o3]
0N/A1: retl
0N/A nop
0N/A SET_SIZE(hvio_iommu_getbypass)
0N/A
0N/A /*
0N/A * arg0 - devhandle
0N/A * arg1 - r_addr
0N/A * arg2 - size
0N/A *
0N/A * ret1 - error_flag
0N/A * ret2 - data
0N/A */
0N/A ENTRY(hvio_peek)
0N/A mov HVIO_PEEK, %o5
0N/A ta FAST_TRAP
0N/A brnz %o0, 1f
0N/A nop
0N/A stx %o2, [%o4]
0N/A st %o1, [%o3]
0N/A1:
0N/A retl
0N/A nop
0N/A SET_SIZE(hvio_peek)
0N/A
0N/A /*
0N/A * arg0 - devhandle
0N/A * arg1 - r_addr
0N/A * arg2 - sizes
0N/A * arg3 - data
0N/A * arg4 - r_addr2
0N/A *
0N/A * ret1 - error_flag
0N/A */
0N/A ENTRY(hvio_poke)
0N/A save %sp, -SA(MINFRAME64), %sp
0N/A mov %i0, %o0
0N/A mov %i1, %o1
304N/A mov %i2, %o2
0N/A mov %i3, %o3
0N/A mov %i4, %o4
0N/A mov HVIO_POKE, %o5
0N/A ta FAST_TRAP
0N/A brnz %o0, 1f
0N/A mov %o0, %i0
0N/A stuw %o1, [%i5]
0N/A1:
304N/A ret
0N/A restore
0N/A SET_SIZE(hvio_poke)
0N/A
0N/A /*
0N/A * arg0 - devhandle
0N/A * arg1 - r_addr
0N/A * arg2 - num_bytes
0N/A * arg3 - io_sync_direction
0N/A *
0N/A * ret0 - status
0N/A * ret1 - bytes_synched
0N/A */
0N/A ENTRY(hvio_dma_sync)
0N/A mov HVIO_DMA_SYNC, %o5
0N/A ta FAST_TRAP
0N/A brz,a %o0, 1f
0N/A stx %o1, [%o4]
0N/A1: retl
0N/A nop
0N/A SET_SIZE(hvio_dma_sync)
0N/A
0N/A /*
0N/A * arg0 - devhandle
0N/A * arg1 - msiq_id
0N/A * arg2 - r_addr
0N/A * arg3 - nentries
0N/A *
0N/A * ret0 - status
0N/A */
0N/A ENTRY(hvio_msiq_conf)
0N/A mov HVIO_MSIQ_CONF, %o5
0N/A ta FAST_TRAP
0N/A retl
0N/A nop
0N/A SET_SIZE(hvio_msiq_conf)
0N/A
0N/A /*
0N/A * arg0 - devhandle
0N/A * arg1 - msiq_id
0N/A *
0N/A * ret0 - status
0N/A * ret1 - r_addr
0N/A * ret1 - nentries
0N/A */
0N/A ENTRY(hvio_msiq_info)
0N/A mov %o2, %o4
0N/A mov HVIO_MSIQ_INFO, %o5
0N/A ta FAST_TRAP
0N/A brnz %o0, 1f
0N/A nop
0N/A stx %o1, [%o4]
0N/A stuw %o2, [%o3]
0N/A1: retl
0N/A nop
0N/A SET_SIZE(hvio_msiq_info)
0N/A
0N/A /*
304N/A * arg0 - devhandle
0N/A * arg1 - msiq_id
0N/A *
304N/A * ret0 - status
0N/A * ret1 - msiq_valid_state
304N/A */
304N/A ENTRY(hvio_msiq_getvalid)
304N/A mov HVIO_MSIQ_GETVALID, %o5
304N/A ta FAST_TRAP
0N/A brz,a %o0, 1f
0N/A stuw %o1, [%o2]
304N/A1: retl
304N/A nop
304N/A SET_SIZE(hvio_msiq_getvalid)
304N/A
304N/A /*
304N/A * arg0 - devhandle
304N/A * arg1 - msiq_id
304N/A * arg2 - msiq_valid_state
304N/A *
304N/A * ret0 - status
304N/A */
304N/A ENTRY(hvio_msiq_setvalid)
304N/A mov HVIO_MSIQ_SETVALID, %o5
304N/A ta FAST_TRAP
304N/A retl
304N/A nop
304N/A SET_SIZE(hvio_msiq_setvalid)
304N/A
304N/A /*
304N/A * arg0 - devhandle
304N/A * arg1 - msiq_id
304N/A *
304N/A * ret0 - status
304N/A * ret1 - msiq_state
304N/A */
304N/A ENTRY(hvio_msiq_getstate)
304N/A mov HVIO_MSIQ_GETSTATE, %o5
304N/A ta FAST_TRAP
304N/A brz,a %o0, 1f
304N/A stuw %o1, [%o2]
304N/A1: retl
304N/A nop
304N/A SET_SIZE(hvio_msiq_getstate)
304N/A
304N/A /*
304N/A * arg0 - devhandle
304N/A * arg1 - msiq_id
304N/A * arg2 - msiq_state
304N/A *
304N/A * ret0 - status
304N/A */
304N/A ENTRY(hvio_msiq_setstate)
304N/A mov HVIO_MSIQ_SETSTATE, %o5
304N/A ta FAST_TRAP
304N/A retl
304N/A nop
304N/A SET_SIZE(hvio_msiq_setstate)
304N/A
304N/A /*
304N/A * arg0 - devhandle
304N/A * arg1 - msiq_id
304N/A *
304N/A * ret0 - status
304N/A * ret1 - msiq_head
304N/A */
304N/A ENTRY(hvio_msiq_gethead)
304N/A mov HVIO_MSIQ_GETHEAD, %o5
304N/A ta FAST_TRAP
304N/A brz,a %o0, 1f
304N/A stx %o1, [%o2]
304N/A1: retl
304N/A nop
304N/A SET_SIZE(hvio_msiq_gethead)
304N/A
304N/A /*
304N/A * arg0 - devhandle
304N/A * arg1 - msiq_id
304N/A * arg2 - msiq_head
304N/A *
304N/A * ret0 - status
304N/A */
304N/A ENTRY(hvio_msiq_sethead)
304N/A mov HVIO_MSIQ_SETHEAD, %o5
304N/A ta FAST_TRAP
304N/A retl
304N/A nop
304N/A SET_SIZE(hvio_msiq_sethead)
304N/A
304N/A /*
304N/A * arg0 - devhandle
304N/A * arg1 - msiq_id
304N/A *
304N/A * ret0 - status
304N/A * ret1 - msiq_tail
304N/A */
304N/A ENTRY(hvio_msiq_gettail)
304N/A mov HVIO_MSIQ_GETTAIL, %o5
304N/A ta FAST_TRAP
304N/A brz,a %o0, 1f
304N/A stx %o1, [%o2]
304N/A1: retl
304N/A nop
304N/A SET_SIZE(hvio_msiq_gettail)
304N/A
304N/A /*
304N/A * arg0 - devhandle
304N/A * arg1 - msi_num
304N/A *
304N/A * ret0 - status
304N/A * ret1 - msiq_id
304N/A */
304N/A ENTRY(hvio_msi_getmsiq)
304N/A mov HVIO_MSI_GETMSIQ, %o5
304N/A ta FAST_TRAP
304N/A brz,a %o0, 1f
304N/A stuw %o1, [%o2]
304N/A1: retl
304N/A nop
304N/A SET_SIZE(hvio_msi_getmsiq)
304N/A
304N/A /*
304N/A * arg0 - devhandle
304N/A * arg1 - msi_num
304N/A * arg2 - msiq_id
304N/A * arg2 - msitype
304N/A *
304N/A * ret0 - status
304N/A */
304N/A ENTRY(hvio_msi_setmsiq)
304N/A mov HVIO_MSI_SETMSIQ, %o5
304N/A ta FAST_TRAP
304N/A retl
304N/A nop
304N/A SET_SIZE(hvio_msi_setmsiq)
304N/A
304N/A /*
304N/A * arg0 - devhandle
304N/A * arg1 - msi_num
304N/A *
304N/A * ret0 - status
304N/A * ret1 - msi_valid_state
304N/A */
304N/A ENTRY(hvio_msi_getvalid)
304N/A mov HVIO_MSI_GETVALID, %o5
304N/A ta FAST_TRAP
304N/A brz,a %o0, 1f
304N/A stuw %o1, [%o2]
304N/A1: retl
304N/A nop
304N/A SET_SIZE(hvio_msi_getvalid)
304N/A
304N/A /*
304N/A * arg0 - devhandle
304N/A * arg1 - msi_num
304N/A * arg2 - msi_valid_state
304N/A *
304N/A * ret0 - status
304N/A */
304N/A ENTRY(hvio_msi_setvalid)
304N/A mov HVIO_MSI_SETVALID, %o5
304N/A ta FAST_TRAP
304N/A retl
304N/A nop
304N/A SET_SIZE(hvio_msi_setvalid)
304N/A
304N/A /*
304N/A * arg0 - devhandle
304N/A * arg1 - msi_num
304N/A *
304N/A * ret0 - status
0N/A * ret1 - msi_state
0N/A */
0N/A ENTRY(hvio_msi_getstate)
0N/A mov HVIO_MSI_GETSTATE, %o5
0N/A ta FAST_TRAP
0N/A brz,a %o0, 1f
0N/A stuw %o1, [%o2]
0N/A1: retl
0N/A nop
304N/A SET_SIZE(hvio_msi_getstate)
304N/A
304N/A /*
304N/A * arg0 - devhandle
304N/A * arg1 - msi_num
304N/A * arg2 - msi_state
304N/A *
304N/A * ret0 - status
304N/A */
304N/A ENTRY(hvio_msi_setstate)
304N/A mov HVIO_MSI_SETSTATE, %o5
304N/A ta FAST_TRAP
304N/A retl
304N/A nop
304N/A SET_SIZE(hvio_msi_setstate)
304N/A
304N/A /*
304N/A * arg0 - devhandle
304N/A * arg1 - msg_type
304N/A *
304N/A * ret0 - status
304N/A * ret1 - msiq_id
304N/A */
304N/A ENTRY(hvio_msg_getmsiq)
304N/A mov HVIO_MSG_GETMSIQ, %o5
304N/A ta FAST_TRAP
304N/A brz,a %o0, 1f
304N/A stuw %o1, [%o2]
304N/A1: retl
304N/A nop
304N/A SET_SIZE(hvio_msg_getmsiq)
304N/A
304N/A /*
304N/A * arg0 - devhandle
304N/A * arg1 - msg_type
304N/A * arg2 - msiq_id
304N/A *
304N/A * ret0 - status
304N/A */
304N/A ENTRY(hvio_msg_setmsiq)
304N/A mov HVIO_MSG_SETMSIQ, %o5
304N/A ta FAST_TRAP
304N/A retl
304N/A nop
304N/A SET_SIZE(hvio_msg_setmsiq)
304N/A
0N/A /*
0N/A * arg0 - devhandle
0N/A * arg1 - msg_type
304N/A *
304N/A * ret0 - status
304N/A * ret1 - msg_valid_state
304N/A */
304N/A ENTRY(hvio_msg_getvalid)
304N/A mov HVIO_MSG_GETVALID, %o5
0N/A ta FAST_TRAP
304N/A brz,a %o0, 1f
0N/A stuw %o1, [%o2]
0N/A1: retl
0N/A nop
304N/A SET_SIZE(hvio_msg_getvalid)
304N/A
304N/A /*
304N/A * arg0 - devhandle
304N/A * arg1 - msg_type
304N/A * arg2 - msg_valid_state
304N/A *
0N/A * ret0 - status
0N/A */
0N/A ENTRY(hvio_msg_setvalid)
0N/A mov HVIO_MSG_SETVALID, %o5
0N/A ta FAST_TRAP
304N/A retl
304N/A nop
304N/A SET_SIZE(hvio_msg_setvalid)
304N/A
304N/A#define SHIFT_REGS mov %o1,%o0; mov %o2,%o1; mov %o3,%o2; mov %o4,%o3
304N/A
304N/A! px_phys_acc_4v: Do physical address read.
304N/A!
304N/A! After SHIFT_REGS:
304N/A! %o0 is "from" address
304N/A! %o1 is "to" address
304N/A!
304N/A! Assumes 8 byte data and that alignment is correct.
304N/A!
304N/A! Always returns success (0) in %o0
304N/A
304N/A ! px_phys_acc_4v must not be split across pages.
304N/A !
304N/A ! ATTN: Be sure that the alignment value is larger than the size of
304N/A ! the px_phys_acc_4v function.
304N/A !
304N/A .align 0x40
304N/A
304N/A ENTRY(px_phys_acc_4v)
304N/A
0N/A SHIFT_REGS
0N/A ldx [%o0], %g1
0N/A stx %g1, [%o1]
0N/A membar #Sync ! Make sure the loads take
304N/A mov %g0, %o0
304N/A done
304N/A SET_SIZE(px_phys_acc_4v)
304N/A
304N/A#endif /* lint || __lint */
304N/A