px_err.h revision bf8fc2340620695a402331e5da7c7db43264174d
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * CDDL HEADER START
f8d2de6bd2421da1926f3daa456d161670decdf7jchu *
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * The contents of this file are subject to the terms of the
bf8fc2340620695a402331e5da7c7db43264174det * Common Development and Distribution License (the "License").
bf8fc2340620695a402331e5da7c7db43264174det * You may not use this file except in compliance with the License.
f8d2de6bd2421da1926f3daa456d161670decdf7jchu *
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * or http://www.opensolaris.org/os/licensing.
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * See the License for the specific language governing permissions
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * and limitations under the License.
f8d2de6bd2421da1926f3daa456d161670decdf7jchu *
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * When distributing Covered Code, include this CDDL HEADER in each
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * If applicable, add the following below this CDDL HEADER, with the
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * fields enclosed by brackets "[]" replaced with your own identifying
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * information: Portions Copyright [yyyy] [name of copyright owner]
f8d2de6bd2421da1926f3daa456d161670decdf7jchu *
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * CDDL HEADER END
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/*
bf8fc2340620695a402331e5da7c7db43264174det * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * Use is subject to license terms.
f8d2de6bd2421da1926f3daa456d161670decdf7jchu */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#ifndef _SYS_PX_ERR_H
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define _SYS_PX_ERR_H
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#pragma ident "%Z%%M% %I% %E% SMI"
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#ifdef __cplusplus
f8d2de6bd2421da1926f3daa456d161670decdf7jchuextern "C" {
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#endif
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* error packet definitions */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Block Definitions */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define BLOCK_RSVD 0x0
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define BLOCK_HOSTBUS 0x1
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define BLOCK_MMU 0x2
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define BLOCK_INTR 0x3
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define BLOCK_PCIE 0x4
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define BLOCK_UNKNOWN 0xe
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Op definitions for HOSTBUS */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define OP_RESERVED 0x0
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define OP_PIO 0x1
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define OP_DMA 0x2
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define OP_UNKNOWN 0xe
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Op definitions for MMU */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define OP_RESERVED 0x0
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define OP_XLAT 0x1
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define OP_BYPASS 0x2
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define OP_TBW 0x3
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define OP_UNKNOWN 0xe
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Op definitions for INTR */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define OP_RESERVED 0x0
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define OP_MSI32 0x1
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define OP_MSI64 0x2
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define OP_MSIQ 0x3
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define OP_PCIEMSG 0x4
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define OP_UNKNOWN 0xe
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Phase definitons */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PH_RESERVED 0x0
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PH_ADDR 0x1
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PH_DATA 0x2
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PH_UNKNOWN 0xe
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define PH_IRR 0xf
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Condition definitions for ADDR Phase */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define CND_RESERVED 0x0
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define CND_ILL 0x1
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define CND_UNMAP 0x2
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define CND_UNKNOWN 0xe
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define CND_IRR 0xf
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Condition definitions for DATA Phase */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define CND_RESERVED 0x0
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define CND_ILL 0x1
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define CND_INT 0x3
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define CND_UE 0x4
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define CND_UNKNOWN 0xe
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define CND_IRR 0xf
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Condition definitions for MMU Block ADDR phase */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define CND_PROT 0x5
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define CND_INV 0x6
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Condition definitions for INTR Block MSIQ Op Data phase */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define CND_OV 0x5
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Condition definitions for Unkown phase */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define CND_RESERVED 0x0
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define CND_ILL 0x1
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define CND_TO 0x5
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define CND_UNKNOWN 0xe
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define CND_IRR 0xf
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Dir definitions for HOSTBUS & MMU */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define DIR_RESERVED 0x0
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define DIR_READ 0x1
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define DIR_WRITE 0x2
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define DIR_RDWR 0x3
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define DIR_INGRESS 0x4
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define DIR_EGRESS 0x5
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define DIR_LINK 0x6
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define DIR_UNKNOWN 0xe
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#define DIR_IRR 0xf
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
bf8fc2340620695a402331e5da7c7db43264174det#define PX_FM_RC_UNRECOG "fire.epkt"
bf8fc2340620695a402331e5da7c7db43264174det#define EPKT_SYSINO "sysino"
bf8fc2340620695a402331e5da7c7db43264174det#define EPKT_EHDL "ehdl"
bf8fc2340620695a402331e5da7c7db43264174det#define EPKT_STICK "stick"
bf8fc2340620695a402331e5da7c7db43264174det#define EPKT_RC_DESCR "rc_descr"
bf8fc2340620695a402331e5da7c7db43264174det#define EPKT_PEC_DESCR "pec_descr"
bf8fc2340620695a402331e5da7c7db43264174det
f8d2de6bd2421da1926f3daa456d161670decdf7jchutypedef struct root_complex {
f8d2de6bd2421da1926f3daa456d161670decdf7jchu uint64_t sysino;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu uint64_t ehdl;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu uint64_t stick;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu struct {
f8d2de6bd2421da1926f3daa456d161670decdf7jchu uint32_t block : 4,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu op : 4,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu phase : 4,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu cond : 4,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu dir : 4,
bf8fc2340620695a402331e5da7c7db43264174det STOP : 1,
bf8fc2340620695a402331e5da7c7db43264174det : 6,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu H : 1,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu R : 1,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu D : 1,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu M : 1,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu S : 1;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu } rc_descr;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu uint32_t size;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu uint64_t addr;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu uint64_t hdr[2];
f8d2de6bd2421da1926f3daa456d161670decdf7jchu uint64_t reserved;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu} px_rc_err_t;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchutypedef struct pec_block_err {
f8d2de6bd2421da1926f3daa456d161670decdf7jchu uint64_t sysino;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu uint64_t ehdl;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu uint64_t stick;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu struct {
f8d2de6bd2421da1926f3daa456d161670decdf7jchu uint32_t block : 4,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu rsvd1 : 12,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu dir : 4,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu : 3,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu Z : 1,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu S : 1,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu R : 1,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu I : 1,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu H : 1,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu C : 1,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu U : 1,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu E : 1,
f8d2de6bd2421da1926f3daa456d161670decdf7jchu P : 1;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu } pec_descr;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu uint16_t pci_err_status;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu uint16_t pcie_err_status;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu uint32_t ce_reg_status;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu uint32_t ue_reg_status;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu uint64_t hdr[2];
f8d2de6bd2421da1926f3daa456d161670decdf7jchu uint32_t err_src_reg;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu uint32_t root_err_status;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu} px_pec_err_t;
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#ifdef __cplusplus
f8d2de6bd2421da1926f3daa456d161670decdf7jchu}
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#endif
f8d2de6bd2421da1926f3daa456d161670decdf7jchu
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#endif /* _SYS_PX_ERR_H */