px_err.h revision bf8fc2340620695a402331e5da7c7db43264174d
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * CDDL HEADER START
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f8d2de6bd2421da1926f3daa456d161670decdf7jchu * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * See the License for the specific language governing permissions
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bf8fc2340620695a402331e5da7c7db43264174det * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * Use is subject to license terms.
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#pragma ident "%Z%%M% %I% %E% SMI"
f8d2de6bd2421da1926f3daa456d161670decdf7jchuextern "C" {
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* error packet definitions */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Block Definitions */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Op definitions for HOSTBUS */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Op definitions for MMU */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Op definitions for INTR */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Phase definitons */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Condition definitions for ADDR Phase */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Condition definitions for DATA Phase */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Condition definitions for MMU Block ADDR phase */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Condition definitions for INTR Block MSIQ Op Data phase */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Condition definitions for Unkown phase */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Dir definitions for HOSTBUS & MMU */
f8d2de6bd2421da1926f3daa456d161670decdf7jchutypedef struct root_complex {
f8d2de6bd2421da1926f3daa456d161670decdf7jchutypedef struct pec_block_err {
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#endif /* _SYS_PX_ERR_H */