f8d2de6bd2421da1926f3daa456d161670decdf7jchu * CDDL HEADER START
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * The contents of this file are subject to the terms of the
bf8fc2340620695a402331e5da7c7db43264174det * Common Development and Distribution License (the "License").
bf8fc2340620695a402331e5da7c7db43264174det * You may not use this file except in compliance with the License.
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * See the License for the specific language governing permissions
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * and limitations under the License.
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * When distributing Covered Code, include this CDDL HEADER in each
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * If applicable, add the following below this CDDL HEADER, with the
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * fields enclosed by brackets "[]" replaced with your own identifying
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * information: Portions Copyright [yyyy] [name of copyright owner]
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * CDDL HEADER END
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
f8d2de6bd2421da1926f3daa456d161670decdf7jchu * Use is subject to license terms.
f8d2de6bd2421da1926f3daa456d161670decdf7jchuextern "C" {
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* error packet definitions */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Block Definitions */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Op definitions for HOSTBUS */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Op definitions for MMU */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Op definitions for INTR */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu/* Op definitions for PORT */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Phase definitons */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu/* Phase definitions for PORT/Link */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu/* Condition definitions for any major Block/Op/Phase */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu/* Additional condition definitions for INTR Block MSIQ phase */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu/* Additional condition definitions for MMU|INTR Block ADDR phase */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu/* Additional condition definitions for DATA phase */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu/* Additional condition definitions for Port Link phase */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu/* Dir definitions for HOSTBUS & MMU */
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu#endif /* _ESC */
f8d2de6bd2421da1926f3daa456d161670decdf7jchu#endif /* _SYS_PX_ERR_H */