nxge_ndd.c revision 4496171313bed39e96f21bc2f9faf2868e267ae3
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
extern uint64_t npi_debug_level;
#define NXGE_PARAM_CLASS_RWS NXGE_PARAM_RWS | \
#define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL
#define SET_RX_INTR_TIME_DISABLE 0
#define SET_RX_INTR_TIME_ENABLE 1
#define SET_RX_INTR_PKTS 2
#define BASE_ANY 0
#define BASE_BINARY 2
#define BASE_HEX 16
#define BASE_DECIMAL 10
#define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL
#define ALL_FF_32 0xFFFFFFFFUL
#define NXGE_NDD_INFODUMP_BUFF_8K 8192
#define NXGE_NDD_INFODUMP_BUFF_16K 0x2000
#define NXGE_NDD_INFODUMP_BUFF_64K 0x8000
}
static void nxge_set_dev_params(p_nxge_t);
static int nxge_param_set_ether_usr(p_nxge_t,
char *, caddr_t);
static int nxge_param_set_ip_usr(p_nxge_t,
char *, caddr_t);
static int nxge_param_set_ip_opt(p_nxge_t,
char *, caddr_t);
static int nxge_param_set_vlan_rdcgrp(p_nxge_t,
char *, caddr_t);
static int nxge_param_set_mac_rdcgrp(p_nxge_t,
char *, caddr_t);
static int nxge_param_fflp_hash_init(p_nxge_t,
char *, caddr_t);
static int
char *, caddr_t);
static int nxge_param_set_npi_debug_flag(p_nxge_t,
char *, caddr_t);
/*
* Global array of Neptune changable parameters.
* This array is initialized to correspond to the default
* Neptune 4 port configuration. This array would be copied
* into each port's parameter structure and modifed per
* fcode and nxge.conf configuration. Later, the parameters are
* exported to ndd to display and run-time configuration (at least
* some of them).
*
*/
static nxge_param_t nxge_param_arr[] = {
/* min max value old hw-name conf-name */
0, 999, 1000, 0,
"instance", "instance"},
0, 999, 1000, 0,
"main-instance", "main_instance"},
0, 3, 0, 0,
"function-number", "function_number"},
/* Partition Id */
0, 8, 0, 0,
"partition-id", "partition_id"},
/* Read Write Permission Mode */
0, 2, 0, 0,
"read-write-mode", "read_write_mode"},
/* hw cfg types */
"niu-cfg-type", "niu_cfg_type"},
/* control the TXDMA config of the Port controlled by tx-quick-cfg */
"tx-qcfg-type", "tx_qcfg_type"},
/* control the RXDMA config of the Port controlled by rx-quick-cfg */
"rx-qcfg-type", "rx_qcfg_type"},
0, 1, 0, 0,
"master-cfg-enable", "master_cfg_enable"},
0, 1, 0, 0,
"master-cfg-value", "master_cfg_value"},
0, 1, 1, 1,
"adv-autoneg-cap", "adv_autoneg_cap"},
0, 1, 1, 1,
"adv-10gfdx-cap", "adv_10gfdx_cap"},
0, 1, 0, 0,
"adv-10ghdx-cap", "adv_10ghdx_cap"},
0, 1, 1, 1,
"adv-1000fdx-cap", "adv_1000fdx_cap"},
0, 1, 0, 0,
"adv-1000hdx-cap", "adv_1000hdx_cap"},
0, 1, 0, 0,
"adv-100T4-cap", "adv_100T4_cap" },
0, 1, 1, 1,
"adv-100fdx-cap", "adv_100fdx_cap"},
0, 1, 0, 0,
"adv-100hdx-cap", "adv_100hdx_cap"},
0, 1, 1, 1,
"adv-10fdx-cap", "adv_10fdx_cap" },
0, 1, 0, 0,
"adv-10hdx-cap", "adv_10hdx_cap" },
0, 1, 0, 0,
"adv-asmpause-cap", "adv_asmpause_cap"},
0, 1, 0, 0,
"adv-pause-cap", "adv_pause_cap"},
0, 1, 0, 0,
"use-int-xcvr", "use_int_xcvr"},
0, 1, 1, 1,
"enable-ipg0", "enable_ipg0"},
0, 255, 8, 8,
"ipg0", "ipg0"},
0, 255, 8, 8,
"ipg1", "ipg1"},
0, 255, 4, 4,
"ipg2", "ipg2"},
0, 1, 0, 0,
"accept-jumbo", "accept_jumbo"},
/* Transmit DMA channels */
0, 3, 0, 0,
"tx-dma-weight", "tx_dma_weight"},
0, 31, 0, 0,
"tx-dma-channels-begin", "tx_dma_channels_begin"},
0, 32, 0, 0,
"tx-dma-channels", "tx_dma_channels"},
0, 32, 0, 0,
"tx-dma-info", "tx_dma_info"},
/* Receive DMA channels */
0, 31, 0, 0,
"rx-dma-channels-begin", "rx_dma_channels_begin"},
0, 32, 0, 0,
"rx-dma-channels", "rx_dma_channels"},
0, 65535, PT_DRR_WT_DEFAULT_10G, 0,
"rx-drr-weight", "rx_drr_weight" },
0, 1, 1, 0,
"rx-full-header", "rx_full_header"},
0, 32, 0, 0,
"rx-dma-info", "rx_dma_info"},
"rx-rbr-size", "rx_rbr_size"},
"rx-rcr-size", "rx_rcr_size"},
0, 15, 0, 0,
"default-port-rdc", "default_port_rdc"},
0, 31, 0, 0,
"rxdma-intr-time", "rxdma_intr_time"},
0, 31, 0, 0,
"rxdma-intr-pkts", "rxdma_intr_pkts"},
0, 8, 0, 0,
"rx-rdc-grps-begin", "rx_rdc_grps_begin"},
0, 8, 0, 0,
"rx-rdc-grps", "rx_rdc_grps"},
0, 15, 0, 0,
"default-grp0-rdc", "default_grp0_rdc"},
0, 15, 2, 0,
"default-grp1-rdc", "default_grp1_rdc"},
0, 15, 4, 0,
"default-grp2-rdc", "default_grp2_rdc"},
0, 15, 6, 0,
"default-grp3-rdc", "default_grp3_rdc"},
0, 15, 8, 0,
"default-grp4-rdc", "default_grp4_rdc"},
0, 15, 10, 0,
"default-grp5-rdc", "default_grp5_rdc"},
0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"},
0, 15, 14, 0,
"default-grp7-rdc", "default_grp7_rdc"},
0, 8, 0, 0,
"rdc-groups-info", "rdc_groups_info"},
/* Logical device groups */
0, 63, 0, 0,
"start-ldg", "start_ldg" },
0, 64, 0, 0,
"max-ldg", "max_ldg" },
/* MAC table information */
0, 31, 0, 0,
"mac-2rdc-grp", "mac_2rdc_grp"},
/* VLAN table information */
0, 31, 0, 0,
"vlan-2rdc-grp", "vlan_2rdc_grp"},
0, 0x0ffff, 0x0ffff, 0,
"fcram-part-cfg", "fcram_part_cfg"},
0, 0x10, 0xa, 0,
"fcram-access-ratio", "fcram_access_ratio"},
0, 0x10, 0xa, 0,
"tcam-access-ratio", "tcam_access_ratio"},
0, 0x1, 0x0, 0,
"tcam-enable", "tcam_enable"},
0, 0x01, 0x0, 0,
"hash-lookup-enable", "hash_lookup_enable"},
0, 0x01, 0x01, 0,
"llc-snap-enable", "llc_snap_enable"},
"h1-init-value", "h1_init_value"},
0, 0x0ffff, 0x0ffff, 0,
"h2-init-value", "h2_init_value"},
0, ALL_FF_32, 0x0, 0,
"class-cfg-ether-usr1", "class_cfg_ether_usr1"},
0, ALL_FF_32, 0x0, 0,
"class-cfg-ether-usr2", "class_cfg_ether_usr2"},
0, ALL_FF_32, 0x0, 0,
"class-cfg-ip-usr4", "class_cfg_ip_usr4"},
0, ALL_FF_32, 0x0, 0,
"class-cfg-ip-usr5", "class_cfg_ip_usr5"},
0, ALL_FF_32, 0x0, 0,
"class-cfg-ip-usr6", "class_cfg_ip_usr6"},
0, ALL_FF_32, 0x0, 0,
"class-cfg-ip-usr7", "class_cfg_ip_usr7"},
0, ALL_FF_32, 0x0, 0,
"class-opt-ip-usr4", "class_opt_ip_usr4"},
0, ALL_FF_32, 0x0, 0,
"class-opt-ip-usr5", "class_opt_ip_usr5"},
0, ALL_FF_32, 0x0, 0,
"class-opt-ip-usr6", "class_opt_ip_usr6"},
0, ALL_FF_32, 0x0, 0,
"class-opt-ip-usr7", "class_opt_ip_usr7"},
0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
"class-opt-ipv4-tcp", "class_opt_ipv4_tcp"},
0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
"class-opt-ipv4-udp", "class_opt_ipv4_udp"},
0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
"class-opt-ipv4-ah", "class_opt_ipv4_ah"},
0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
"class-opt-ipv4-sctp", "class_opt_ipv4_sctp"},
0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
"class-opt-ipv6-tcp", "class_opt_ipv6_tcp"},
0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
"class-opt-ipv6-udp", "class_opt_ipv6_udp"},
0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
"class-opt-ipv6-ah", "class_opt_ipv6_ah"},
0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0,
"class-opt-ipv6-sctp", "class_opt_ipv6_sctp"},
"nxge-debug-flag", "nxge_debug_flag"},
"npi-debug-flag", "npi_debug_flag"},
0, 0x0fffffff, 0x0fffffff, 0,
"dump-tdc", "dump_tdc"},
0, 0x0fffffff, 0x0fffffff, 0,
"dump-rdc", "dump_rdc"},
0, 0x0fffffff, 0x0fffffff, 0,
"dump-mac-regs", "dump_mac_regs"},
0, 0x0fffffff, 0x0fffffff, 0,
"dump-ipp-regs", "dump_ipp_regs"},
0, 0x0fffffff, 0x0fffffff, 0,
"dump-fflp-regs", "dump_fflp_regs"},
0, 0x0fffffff, 0x0fffffff, 0,
"dump-vlan-table", "dump_vlan_table"},
0, 0x0fffffff, 0x0fffffff, 0,
"dump-rdc-table", "dump_rdc_table"},
0, 0x0fffffff, 0x0fffffff, 0,
"dump-ptrs", "dump_ptrs"},
0, 0x0fffffff, 0x0fffffff, 0, "end", "end" },
};
extern void *nxge_list;
void
{
int i, j;
for (i = 0; i < param_count; i++) {
continue;
continue;
param_arr[i].fcode_name,
(int **)&int_prop_val,
== DDI_PROP_SUCCESS) {
for (j = 0; j < prop_len; j++) {
cfg_value[j] = int_prop_val[j];
}
}
continue;
}
param_arr[i].fcode_name,
(int **)&int_prop_val,
&prop_len) == DDI_PROP_SUCCESS) {
#ifdef NXGE_DEBUG_ERROR
else {
"nxge%d: 'prom' file"
" parameter error\n",
"Parameter keyword '%s'"
" is outside valid range\n",
}
#endif
}
(int **)&int_prop_val,
&prop_len) == DDI_PROP_SUCCESS) {
#ifdef NXGE_DEBUG_ERROR
else {
"nxge%d: 'conf' file"
" parameter error\n",
"Parameter keyword '%s'"
"is outside valid range\n",
}
#endif
}
}
}
static int
{
int channel;
char *prop_name;
char *end;
" nxge_private_param_register %s",
return (B_TRUE);
return (B_TRUE);
prop_name += name_chars;
/* now check if this rdcgrp is in config */
}
return (B_TRUE);
}
return (B_FALSE);
}
prop_name += name_chars;
/* now check if this rdc is in config */
" nxge_private_param_register: %d",
channel));
}
return (B_FALSE);
}
return (status);
}
void
{
int i;
/*
* Make sure the param_instance is set to a valid device instance.
*/
for (i = 0; i < nxgep->param_count; i++) {
¶m_arr[i]) ==
B_FALSE)) {
}
}
if ((set_pfi) &&
}
break;
}
}
}
void
{
int i, alloc_size;
/*
* Make sure the param_instance is set to a valid device instance.
*/
sizeof (nxge_param_arr), KM_SLEEP);
}
for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) {
param_arr[i] = nxge_param_arr[i];
}
}
nxgep->param_count));
}
void
{
int i;
/*
* Make sure the param_instance is set to a valid device instance.
*/
break;
}
}
if (nxgep->param_list)
for (i = 0; i < nxgep->param_count; i++)
}
}
/*
* Extracts the value from the 'nxge' parameter array and prints the
* parameter value. cp points to the required parameter.
*/
/* ARGSUSED */
int
{
else
return (0);
}
/* ARGSUSED */
static int
{
return (0);
}
/* ARGSUSED */
int
{
int tdc;
(void) mi_mpprintf(mp,
"TXDMA Information for Port\t %d \n",
return (0);
}
"TDC\t HW TDC\t\n");
buf_len, "%d\t %d\n",
}
return (0);
}
/* ARGSUSED */
int
{
int rdc;
(void) mi_mpprintf(mp,
"RXDMA Information for Port\t %d \n",
/* The following may work even if we cannot get a large buf. */
return (0);
}
"Total RDCs\t %d\n",
"RDC\t HW RDC\t Timeout\t Packets RBR ptr \t"
"chunks\t RCR ptr\n");
" %d\t %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n",
}
return (0);
}
/* ARGSUSED */
int
{
int i, rdc_grp;
"==> nxge_param_get_rxdma_rdcgrp_info"));
(void) mi_mpprintf(mp,
"RXDMA RDC Group Information for Port\t %d \n",
/* The following may work even if we cannot get a large buf. */
return (0);
}
"Total RDC Groups\t %d \n"
"start RDC group\t %d\n",
rdc_grp++, i++) {
"\nRDC Group Info for Group [%d] %d\n"
"RDC Count %d\tstart RDC %d\n"
"RDC Group Population Information"
" (offsets 0 - 15)\n",
buf_len, "\n");
}
buf_len, "\n");
buf_len, " %2d ",
}
buf_len, "\n");
}
"<== nxge_param_get_rxdma_rdcgrp_info"));
return (0);
}
int
{
if (!tmp)
return (ENOMEM);
}
return (0);
}
/*
* Sets the ge parameter to the value in the nxge_param_register using
* nxge_nd_load().
*/
/* ARGSUSED */
int
{
char *end;
return (EINVAL);
}
return (0);
}
/*
* Sets the ge parameter to the value in the nxge_param_register using
* nxge_nd_load().
*/
/* ARGSUSED */
int
{
return (0);
}
/*
* Sets the ge parameter to the value in the nxge_param_register using
* nxge_nd_load().
*/
/* ARGSUSED */
int
{
char *end;
int status = 0;
return (EINVAL);
}
}
if (!nxge_param_link_update(nxgep)) {
" false ret from nxge_param_link_update"));
}
return (status);
}
/* ARGSUSED */
static int
{
int status = 0;
/* setup value */
switch (type) {
case SET_RX_INTR_TIME_DISABLE:
value, 0);
break;
case SET_RX_INTR_TIME_ENABLE:
value, 1);
break;
case SET_RX_INTR_PKTS:
value);
break;
default:
status = NXGE_ERROR;
break;
}
return (status);
}
/* ARGSUSED */
static int
{
char *end;
/* now do decoding */
/*
* format is
* bit[30]= enable
* bit[29]= remove
* bits[23-16] = rdc
* bits[15-0] = blanking parameter
*
*/
}
} else {
return (EINVAL);
}
return (EINVAL);
}
return (0);
}
/* ARGSUSED */
static int
{
char *end;
/* now do decoding */
/*
* format is
* bit[30]= enable
* bit[29]= remove
* bits[23-16] = rdc
* bits[15-0] = blanking parameter
*
*/
" nxge_param_rx_intr_time value %x",
cfg_value));
" nxge_param_rx_intr_time %x %x",
}
} else {
return (EINVAL);
}
else
return (EINVAL);
}
return (0);
}
/* ARGSUSED */
static int
{
char *end;
/* now do decoding */
/* */
" cfg_value %x id %x map_to %x",
" nxge_param_set_mac_rdcgrp mapping"
" id %d grp %d",
}
} else {
return (EINVAL);
}
return (EINVAL);
}
return (0);
}
/* ARGSUSED */
static int
{
char *end;
int i, inc = 0, cfg_position;
/* now do decoding */
/* */
if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) {
/*
* for now, we process only upto max
* NXGE_PARAM_ARRAY_INIT_SIZE parameters
* In the future, we may want to expand
* the storage array and continue
*/
return (EINVAL);
}
" nxge_param_set_vlan_rdcgrp mapping"
" id %d grp %d",
/* search to see if this vlan id is already configured */
for (i = 0; i < cfgd_vlans; i++) {
cfg_position = i;
break;
}
}
if (cfgd_vlans == 0) {
cfg_position = 0;
inc++;
}
if (i == cfgd_vlans) {
cfg_position = i;
inc++;
}
" set_vlan_rdcgrp mapping"
" i %d cfgd_vlans %llx position %d ",
i, cfgd_vlans, cfg_position));
if (inc) {
cfgd_vlans++;
}
" after: param_set_vlan_rdcgrp "
" cfg_vlans %llx position %d \n",
}
} else {
return (EINVAL);
}
return (EINVAL);
}
return (0);
}
/* ARGSUSED */
static int
{
int i;
uint64_t cfgd_vlans = 0;
(void) mi_mpprintf(mp,
"VLAN RDC Mapping Information for Port\t %d \n",
return (0);
}
i = (int)cfgd_vlans;
"Configured VLANs %d\n"
" Prefernce\n", i);
for (i = 0; i < cfgd_vlans; i++) {
" %d\t\t %d/%d\t\t %d\n",
}
}
return (0);
}
/* ARGSUSED */
static int
{
int i;
(void) mi_mpprintf(mp,
" MAC ADDR RDC Mapping Information for Port\t %d\n",
return (0);
}
" Prefernce\n");
if (mac_host_info[i].flag) {
" %d\t %d/%d\t\t %d\n",
i,
mac_host_info[i].rdctbl,
mac_host_info[i].rdctbl -
mac_host_info[i].mpr_npr);
}
}
"Done Info Dumping \n");
return (0);
}
/* ARGSUSED */
static int
{
char *end;
}
else
return (EINVAL);
}
return (0);
}
/* ARGSUSED */
static int
{
char *end;
}
else
return (EINVAL);
}
return (0);
}
/* ARGSUSED */
static int
{
char *end;
}
else
return (EINVAL);
}
return (0);
}
/* ARGSUSED */
static int
{
char *end;
return (EINVAL);
}
}
/* do the actual hw setup */
#ifdef lint
#endif
}
return (status);
}
/* ARGSUSED */
static int
{
char *end;
return (EINVAL);
}
}
/* do the actual hw setup with cfg_value. */
}
return (status);
}
static int
{
int i;
for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) {
return (i);
}
return (-1);
}
/* ARGSUSED */
static int
{
char *end;
return (EINVAL);
}
}
/* do the actual hw setup */
if (class == -1)
return (EINVAL);
return (EINVAL);
}
return (0);
}
/* ARGSUSED */
static int
{
/* do the actual hw setup */
if (class == -1)
return (EINVAL);
cfg_value = 0;
return (EINVAL);
"nxge_param_get_ip_opt_get %x ", cfg_value));
return (0);
}
/* ARGSUSED */
static int
{
char *end;
return (EINVAL);
}
" nxge_param_fflp_hash_init value %x",
cfg_value));
}
char *h_name;
/* do the actual hw setup */
h_name++;
switch (class) {
case 1:
break;
case 2:
break;
default:
" nxge_param_fflp_hash_init"
" %s Wrong hash var %d",
return (EINVAL);
}
return (EINVAL);
}
return (0);
}
/* ARGSUSED */
static int
{
char *end;
int rdc_grp;
return (EINVAL);
}
return (EINVAL);
}
}
char *grp_name;
" nxge_param_set_grp_rdc"
" %d read %d actual %d outof range",
return (EINVAL);
}
real_rdc);
return (EINVAL);
}
return (0);
}
/* ARGSUSED */
static int
{
char *end;
return (EINVAL);
}
return (EINVAL);
}
return (EINVAL);
}
return (0);
}
/* ARGSUSED */
static int
{
char *end;
" nxge_param_set_nxge_debug_flag"
" outof range %llx", cfg_value));
return (EINVAL);
}
}
}
return (status);
}
/* ARGSUSED */
static int
{
int status = 0;
else
return (status);
}
/* ARGSUSED */
static int
{
char *end;
" outof range %llx", cfg_value));
return (EINVAL);
}
}
}
return (status);
}
/* ARGSUSED */
/* ARGSUSED */
static int
{
return (0);
}
/* ARGSUSED */
static int
{
return (0);
}
/* ARGSUSED */
static int
{
return (0);
}
/* ARGSUSED */
static int
{
return (0);
}
/* ARGSUSED */
static int
{
return (0);
}
/* ARGSUSED */
static int
{
return (0);
}
/* ARGSUSED */
static int
{
table);
}
return (0);
}
typedef struct block_info {
char *name;
} block_info_t;
block_info_t reg_block[] = {
{"PIO", PIO},
{"FZC_PIO", FZC_PIO},
{"FZC_XMAC", FZC_MAC},
{"FZC_IPP", FZC_IPP},
{"FFLP", FFLP},
{"FZC_FFLP", FZC_FFLP},
{"PIO_VADDR", PIO_VADDR},
{"ZCP", ZCP},
{"FZC_ZCP", FZC_ZCP},
{"DMC", DMC},
{"FZC_DMC", FZC_DMC},
{"TXC", TXC},
{"FZC_TXC", FZC_TXC},
{"PIO_LDSV", PIO_LDSV},
{"PIO_LDGIM", PIO_LDGIM},
{"PIO_IMASK0", PIO_IMASK0},
{"PIO_IMASK1", PIO_IMASK1},
{"FZC_PROM", FZC_PROM},
{"END", ALL_FF_32},
};
/* ARGSUSED */
static int
{
(void) mi_mpprintf(mp,
"ptr information for Port\t %d \n",
/* The following may work even if we cannot get a large buf. */
return (0);
}
"nxgep (nxge_t) $%p\n"
"dev_regs (dev_regs_t) $%p\n",
/* do register pointers */
"reg base (npi_reg_ptr_t) $%p\t "
"pci reg (npi_reg_ptr_t) $%p\n",
"\nBlock \t Offset \n");
block = 0;
"%9s\t 0x%llx\n",
base));
block++;
}
"\nRDC\t rcrp (rx_rcr_ring_t)\t "
"rbrp (rx_rbr_ring_t)\n");
" %d\t $%p\t\t $%p\n",
}
"\nTDC\t tdcp (tx_ring_t)\n");
" %d\t $%p\n",
}
"\n\n");
return (0);
}
/*
* Load 'name' into the named dispatch table pointed to by 'ndp'.
* 'ndp' should be the address of a char pointer cell. If the table
* does not exist (*ndp == 0), a new table is allocated and 'ndp'
* is stuffed. If there is not enough space in the table for a new
* entry, more space is allocated.
*/
{
if (!pparam)
return (B_FALSE);
== NULL)
return (B_FALSE);
}
goto fill_it;
}
}
return (B_FALSE);
} else {
nd->nd_free_count--;
}
}
noop;
nd->nd_free_count--;
return (B_TRUE);
}
/*
* Free the table pointed to by 'pparam'
*/
void
{
}
}
int
{
int err;
char *valp;
if (!param) {
return (B_FALSE);
}
return (B_FALSE);
}
/*
* NOTE - logic throughout nd_xxx assumes single data block for ioctl.
* However, existing code sends in some big buffers.
*/
}
if (*valp == '-')
*valp = '_';
}
return (B_FALSE);
break;
}
while (*valp++)
noop;
case ND_GET:
/*
* (temporary) hack: "*valp" is size of user buffer for
* copyout. If result of action routine is too big, free
* excess and return ioc_rval as buffer size needed.
* Return as many mblocks as will fit, free the rest. For
* backward compatibility, assume size of original ioctl
* buffer if "*valp" bad or not given.
*/
if (valp)
/*
*/
while (mp2) {
}
if (!err) {
/* Tack on the null */
if (!err) {
if (excess > 0) {
if (!err)
else
size_out = 0;
}
} else
size_out = 0;
}
break;
case ND_SET:
if (valp) {
if (nde->nde_set_pfi) {
}
}
break;
default:
break;
}
return (B_TRUE);
}
/* ARGSUSED */
int
{
char *rwtag;
int status = 0;
if (!nd)
return (ENOENT);
if (get_ok) {
if (set_ok)
rwtag = "read and write";
else
rwtag = "read only";
} else if (set_ok)
rwtag = "write only";
else {
continue;
}
param_len += 4;
}
return (status);
}
/* ARGSUSED */
int
{
return (EACCES);
}
/* ARGSUSED */
int
{
return (EACCES);
}
void
{
int cmd;
switch (cmd) {
default:
"nxge_param_ioctl: bad cmd 0x%0x", cmd));
break;
case ND_GET:
case ND_SET:
"nxge_param_ioctl: cmd 0x%0x", cmd));
"false ret from nxge_nd_getset"));
break;
}
break;
}
if (status) {
} else {
}
}
/* ARGSUSED */
static boolean_t
{
int instance;
for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) {
}
if (update_xcvr) {
for (i = param_autoneg; i < param_enable_ipg0; i++) {
update_xcvr |=
}
if (update_xcvr) {
(void) nxge_link_init(nxgep);
(void) nxge_mac_init(nxgep);
}
} else {
" no link capabilities.", instance);
for (i = param_anar_1000fdx; i < param_anar_asmpause; i++)
}
if (update_dev) {
(void) nxge_rx_mac_disable(nxgep);
(void) nxge_tx_mac_disable(nxgep);
(void) nxge_set_dev_params(nxgep);
(void) nxge_tx_mac_enable(nxgep);
(void) nxge_rx_mac_enable(nxgep);
}
"<== nxge_param_link_update status = 0x%08x", status));
return (status);
}
/* ARGSUSED */
static void
{
/* Reinitialize any instance specific parameters. */
}