nxge_hw.c revision 14ea4bb737263733ad80a36b4f73f681c30a6b45
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* Tunable Receive Completion Ring Configuration B parameters.
*/
extern uint32_t nxge_rx_mode;
extern uint32_t nxge_jumbo_mtu;
extern boolean_t nxge_jumbo_enable;
void
{
(void) nxge_intr_hw_disable(nxgep);
(void) nxge_link_init(nxgep);
}
(void) nxge_mac_init(nxgep);
(void) nxge_intr_hw_enable(nxgep);
}
void
{
/*
* Set up initial hardware parameters required such as mac mtu size.
*/
}
"==> nxge_hw_id_init: maxframesize %d",
}
void
{
return;
}
"nxge_hw_init_niu_common"
" already done for dip $%p function %d exiting",
nxgep->function_num));
return;
}
" Started for device id %x with function %d",
nxgep->function_num));
" Done for device id %x with function %d",
nxgep->function_num));
}
{
/* DDI interface returns second arg as NULL (n2 niumx driver) !!! */
}
"<== nxge_intr: not initialized 0x%x",
serviced));
return (serviced);
}
ldgvp));
}
if (ldvp) {
}
"ldgvp $%p ldvp $%p ldgp $%p",
"ldgvp $%p ldvp $%p ldgp $%p",
return (DDI_INTR_UNCLAIMED);
}
/*
* This interrupt handler will have to go through
* all the logical devices to find out which
* logical device interrupts us and then call
* its handler to process the events.
*/
/* Get this group's flag bits. */
if (rs) {
continue;
}
continue;
}
"vector0 0x%llx vector1 0x%llx vector2 0x%llx",
/*
* Call device's handler if flag bits are on.
*/
if (((ldv < NXGE_MAC_LD_START) &&
(ldv >= NXGE_MAC_LD_START &&
(void) (t_ldvp->ldv_intr_handler)(
"==> nxge_intr: "
"calling device %d #ldvs %d #intrs %d",
}
}
}
/* rearm group interrupts */
if (t_ldgp->interrupted) {
}
}
serviced));
return (serviced);
}
{
return (serviced);
}
}
}
"==> nxge_syserr_intr: arg2 $%p arg1 $%p",
"<== nxge_syserrintr(no logical group): "
"arg2 $%p arg1 $%p",
return (DDI_INTR_UNCLAIMED);
}
/*
* Get the logical device state if the function uses interrupt.
*/
}
/* This interrupt handler is for system error interrupts. */
"==> nxge_syserr_intr: device error 0x%016llx",
/* SMX */
"==> nxge_syserr_intr: device error - SMX"));
"==> nxge_syserr_intr: device error - MAC"));
/*
* There is nothing to be done here. All MAC errors
* go to per MAC port interrupt. MIF interrupt is
* the only MAC sub-block that can generate status
* here. MIF status reported will be ignored here.
* It is checked by per port timer instead.
*/
"==> nxge_syserr_intr: device error - IPP"));
(void) nxge_ipp_handle_sys_errors(nxgep);
/* ZCP */
"==> nxge_syserr_intr: device error - ZCP"));
(void) nxge_zcp_handle_sys_errors(nxgep);
/* TDMC */
"==> nxge_syserr_intr: device error - TDMC"));
/*
* There is no TDMC system errors defined in the PRM.
* All TDMC channel specific errors are reported on
* a per channel basis.
*/
/* RDMC */
"==> nxge_syserr_intr: device error - RDMC"));
(void) nxge_rxdma_handle_sys_errors(nxgep);
"==> nxge_syserr_intr: device error - TXC"));
(void) nxge_txc_handle_sys_errors(nxgep);
/* PCI-E */
"==> nxge_syserr_intr: device error - PCI-E"));
/* META1 */
"==> nxge_syserr_intr: device error - META1"));
/* META2 */
"==> nxge_syserr_intr: device error - META2"));
/* FFLP */
"==> nxge_syserr_intr: device error - FFLP"));
(void) nxge_fflp_handle_sys_errors(nxgep);
}
}
return (serviced);
}
void
{
}
void
{
}
void
{
int i;
"<== nxge_rx_hw_blank (not enabled)"));
return;
}
return;
}
(void) npi_rxdma_cfg_rdc_rcr_timeout(handle,
}
}
}
void
{
(void) nxge_tx_mac_disable(nxgep);
(void) nxge_rx_mac_disable(nxgep);
}
void
{
int cmd;
return;
}
switch (cmd) {
default:
return;
case NXGE_GET_MII:
break;
case NXGE_PUT_MII:
break;
case NXGE_GET64:
break;
case NXGE_PUT64:
break;
case NXGE_PUT_TCAM:
break;
case NXGE_GET_TCAM:
break;
case NXGE_TX_REGS_DUMP:
break;
case NXGE_RX_REGS_DUMP:
break;
case NXGE_VIR_INT_REGS_DUMP:
case NXGE_INT_REGS_DUMP:
break;
case NXGE_RTRACE:
break;
}
}
void
{
int i;
}
case LB_GET_MODE:
} else
break;
case LB_SET_MODE:
break;
}
} else {
}
break;
case LB_GET_INFO_SIZE:
size += sizeof (lb_external10g);
size += sizeof (lb_serdes10g);
}
size += sizeof (lb_external1000);
size += sizeof (lb_mac1000);
size += sizeof (lb_phy1000);
}
size += sizeof (lb_external100);
size += sizeof (lb_external10);
size += sizeof (lb_serdes1000);
"NXGE_GET_LB_INFO command: size %d", size));
} else
break;
case LB_GET_INFO:
size += sizeof (lb_external10g);
size += sizeof (lb_serdes10g);
}
size += sizeof (lb_external1000);
size += sizeof (lb_mac1000);
size += sizeof (lb_phy1000);
}
size += sizeof (lb_external100);
size += sizeof (lb_external10);
size += sizeof (lb_serdes1000);
"NXGE_GET_LB_INFO command: size %d", size));
i = 0;
lb_props[i++] = lb_serdes10g;
lb_props[i++] = lb_external10g;
}
lb_props[i++] = lb_external1000;
lb_props[i++] = lb_external100;
lb_props[i++] = lb_external10;
lb_props[i++] = lb_mac1000;
lb_props[i++] = lb_phy1000;
lb_props[i++] = lb_serdes1000;
} else
} else {
}
break;
}
}
/*
* DMA channel interfaces to access various channel specific
* hardware functions.
*/
void
{
/*
* Channel is assumed to be from 0 to
* the maximum DMA channel #.
* If we use the virtual DMA CSR address space
* from the config space (in PCI case), then the
* following code need to be use different offset
* computation macro.
*/
}
{
/*
* Channel is assumed to be from 0 to
* the maximum DMA channel #.
* If we use the virtual DMA CSR address space
* from the config space (in PCI case), then the
* following code need to be use different offset
* computation macro.
*/
}
void
{
}
void
{
"reg = 0x%016llX index = 0x%08X value = 0x%08X",
}
/*ARGSUSED*/
{
"!nxge%d: Loopback mode already set (lb_mode %d).\n",
goto nxge_set_lb_exit;
}
lb_info = &lb_external10;
lb_info = &lb_phy1000;
lb_info = &lb_serdes10g;
lb_info = &lb_serdes1000;
lb_info = &lb_mac1000;
else {
"!nxge%d: Loopback mode not supported(mode %d).\n",
goto nxge_set_lb_exit;
}
if (lb_mode == nxge_lb_normal) {
if (nxge_lb_dbg) {
"!nxge%d: Returning to normal operation",
}
goto nxge_set_lb_exit;
}
if (nxge_lb_dbg)
"!nxge%d: Adapter now in %s loopback mode",
}
(void) nxge_xcvr_find(nxgep);
(void) nxge_link_init(nxgep);
}
== nxge_lb_mac1000) ||
} else {
}
}
"<== nxge_set_lb status = 0x%08x", status));
return (status);
}
void
{
(void) nxge_xcvr_find(nxgep);
(void) nxge_link_init(nxgep);
}
void
{
}
void
{
"reg = 0x%08X index = 0x%08X value = 0x%08X",
}
void
{
nxgep->nxge_timerid = 0;
goto nxge_check_hw_state_exit;
}
"NULL ldgvp (interrupt not ready)."));
goto nxge_check_hw_state_exit;
}
"ldgvp $%p t_ldvp $%p use_timer flag %d",
goto nxge_check_hw_state_exit;
}
}
}
/*ARGSUSED*/
static void
{
uint32_t i, j;
size = 1024;
"malformed M_IOCTL MBLKL = %d size = %d",
return;
}
for (i = 0, j = base_entry; i < num_entries; i++, j++) {
}
}