nxge_fzc.c revision 4496171313bed39e96f21bc2f9faf2868e267ae3
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <nxge_impl.h>
#include <npi_mac.h>
#include <npi_rxdma.h>
#if defined(sun4v) && defined(NIU_LP_WORKAROUND)
static int nxge_herr2kerr(uint64_t);
#endif
/*
* The following interfaces are controlled by the
* function control registers. Some global registers
* are to be initialized by only byt one of the 2/4 functions.
* Use the test and set register.
*/
/*ARGSUSED*/
{
!= NPI_SUCCESS) {
return (NXGE_ERROR | rs);
}
return (NXGE_OK);
}
{
/*
* In multi-partitioning, the partition manager
* who owns function zero should set this multi-partition
* control bit.
*/
return (NXGE_ERROR);
}
"<== nxge_set_fzc_multi_part_ctl"));
return (NXGE_ERROR | rs);
}
return (NXGE_OK);
}
{
"<== nxge_set_fzc_multi_part_ctl"));
return (NXGE_ERROR | rs);
}
return (NXGE_OK);
}
/*
* System interrupt registers that are under function zero
* management.
*/
{
/* Configure the initial timer resolution */
return (status);
}
case NEPTUNE:
case NEPTUNE_2:
/*
* Set up the logical device group's logical devices that
* the group owns.
*/
!= NXGE_OK) {
break;
}
/* Configure the system interrupt data */
break;
}
break;
}
return (status);
}
{
int i, j;
return (NXGE_ERROR);
}
return (NXGE_ERROR);
}
"==> nxge_fzc_intr_ldg_num_set "
"<== nxge_f(Neptune): # ldv %d "
ldvp->ldg_assigned);
if (rs != NPI_SUCCESS) {
"<== nxge_fzc_intr_ldg_num_set failed "
" rs 0x%x ldv %d ldg %d",
return (NXGE_ERROR | rs);
}
"<== nxge_fzc_intr_ldg_num_set OK "
" ldv %d ldg %d",
}
}
return (NXGE_OK);
}
{
return (NXGE_ERROR);
}
return (NXGE_ERROR | rs);
}
return (NXGE_OK);
}
{
int i;
"<== nxge_fzc_intr_sid_set: no ldg"));
return (NXGE_ERROR);
}
"==> nxge_fzc_intr_sid_set(%d): func %d group %d "
"vector %d",
if (rs != NPI_SUCCESS) {
"<== nxge_fzc_intr_sid_set:failed 0x%x",
rs));
return (NXGE_ERROR | rs);
}
}
return (NXGE_OK);
}
/*
* Receive DMA registers that are under function zero
* management.
*/
/*ARGSUSED*/
{
case NEPTUNE:
case NEPTUNE_2:
default:
/* Initialize the RXDMA logical pages */
rbr_p);
return (status);
}
break;
#ifndef NIU_HV_WORKAROUND
case N2_NIU:
#if defined(sun4v) && defined(NIU_LP_WORKAROUND)
"==> nxge_init_fzc_rxdma_channel: N2_NIU - call HV "
"set up logical pages"));
/* Initialize the RXDMA logical pages */
rbr_p);
return (status);
}
#endif
break;
#else
case N2_NIU:
"==> nxge_init_fzc_rxdma_channel: N2_NIU - NEED to "
"set up logical pages"));
/* Initialize the RXDMA logical pages */
rbr_p);
return (status);
}
break;
#endif
}
/* Configure RED parameters */
return (status);
}
/*ARGSUSED*/
{
"==> nxge_init_fzc_rxdma_channel_pages"));
/*
* Initialize logical page 1.
*/
(p_dma_log_page_t)&cfg);
if (rs != NPI_SUCCESS) {
return (NXGE_ERROR | rs);
}
/*
* Initialize logical page 2.
*/
if (rs != NPI_SUCCESS) {
return (NXGE_ERROR | rs);
}
/* Initialize the page handle */
if (rs != NPI_SUCCESS) {
return (NXGE_ERROR | rs);
}
"<== nxge_init_fzc_rxdma_channel_pages"));
return (NXGE_OK);
}
/*ARGSUSED*/
{
"==> nxge_init_fzc_rxdma_channel_red(thre_sync %d(%x))",
if (rs != NPI_SUCCESS) {
return (NXGE_ERROR | rs);
}
"<== nxge_init_fzc_rxdma_channel_red"));
return (NXGE_OK);
}
/*ARGSUSED*/
{
"==> nxge_init_fzc_txdma_channel"));
case NEPTUNE:
case NEPTUNE_2:
default:
/* Initialize the TXDMA logical pages */
break;
#ifndef NIU_HV_WORKAROUND
case N2_NIU:
#if defined(sun4v) && defined(NIU_LP_WORKAROUND)
"==> nxge_init_fzc_txdma_channel "
"N2_NIU: call HV to set up txdma logical pages"));
return (status);
}
#endif
break;
#else
case N2_NIU:
"==> nxge_init_fzc_txdma_channel "
"N2_NIU: NEED to set up txdma logical pages"));
/* Initialize the TXDMA logical pages */
break;
#endif
}
/*
* Configure Transmit DRR Weight parameters
* (It actually programs the TXC max burst register).
*/
"<== nxge_init_fzc_txdma_channel"));
return (status);
}
{
(void) nxge_init_fzc_rx_common(nxgep);
return (status);
}
{
"==> nxge_init_fzc_rx_common null ptr"));
return (NXGE_ERROR);
}
/*
* Configure the rxdma clock divider
* This is the granularity counter based on
* the hardware system clock (i.e. 300 Mhz) and
* it is running around 3 nanoseconds.
* So, set the clock divider counter to 1000 to get
* microsecond granularity.
* For example, for a 3 microsecond timeout, the timeout
* will be set to 1.
*/
if (rs != NPI_SUCCESS)
return (NXGE_ERROR | rs);
#if defined(__i386)
if (rs != NPI_SUCCESS)
return (NXGE_ERROR | rs);
if (rs != NPI_SUCCESS)
return (NXGE_ERROR | rs);
#endif
/*
* Enable WRED and program an initial value.
* Use time to set the initial random number.
*/
if (rs != NPI_SUCCESS)
return (NXGE_ERROR | rs);
/* Initialize the RDC tables for each group */
/* Ethernet Timeout Counter (?) */
"<== nxge_init_fzc_rx_common:status 0x%08x", status));
return (status);
}
{
int ngrps;
int i;
if (rs != NPI_SUCCESS) {
break;
}
}
return (status);
}
{
int i;
/*
* Initialize the port scheduler DRR weight.
* npi_rxdma_cfg_port_ddr_weight();
*/
if (rs != NPI_SUCCESS) {
return (NXGE_ERROR | rs);
}
}
}
/* Program the default RDC of a port */
if (rs != NPI_SUCCESS) {
return (NXGE_ERROR | rs);
}
/*
* Configure the MAC host info table with RDC tables
*/
}
if (rs != NPI_SUCCESS)
return (NXGE_ERROR | rs);
}
"<== nxge_init_fzc_rxdma_port rs 0x%08x", rs));
return (NXGE_OK);
}
{
if (rs & NPI_FAILURE)
return (NXGE_ERROR | rs);
return (NXGE_OK);
}
{
"==> nxge_init_fzc_txdma_channel_pages"));
#ifndef NIU_HV_WORKAROUND
"<== nxge_init_fzc_txdma_channel_pages: "
"N2_NIU: no need to set txdma logical pages"));
return (NXGE_OK);
}
#else
"<== nxge_init_fzc_txdma_channel_pages: "
"N2_NIU: NEED to set txdma logical pages"));
}
#endif
/*
* Initialize logical page 1.
*/
(p_dma_log_page_t)&cfg);
if (rs != NPI_SUCCESS) {
return (NXGE_ERROR | rs);
}
/*
* Initialize logical page 2.
*/
if (rs != NPI_SUCCESS) {
return (NXGE_ERROR | rs);
}
/* Initialize the page handle */
if (rs == NPI_SUCCESS) {
return (NXGE_OK);
} else {
return (NXGE_ERROR | rs);
}
}
{
if (rs == NPI_SUCCESS) {
return (NXGE_OK);
} else {
return (NXGE_ERROR | rs);
}
}
{
if (rs == NPI_SUCCESS) {
return (NXGE_OK);
} else {
return (NXGE_ERROR | rs);
}
}
#if defined(sun4v) && defined(NIU_LP_WORKAROUND)
{
int err;
#ifdef DEBUG
#endif
"==> nxge_init_hv_fzc_txdma_channel_pages"));
return (NXGE_OK);
}
/*
* Initialize logical page 1 for data buffers.
*/
(uint64_t)0,
if (err != 0) {
"<== nxge_init_hv_fzc_txdma_channel_pages: channel %d "
"error status 0x%x "
"(page 0 data buf) hverr 0x%llx "
"ioaddr_pp $%p "
"size 0x%llx ",
err,
return (NXGE_ERROR | err);
}
#ifdef DEBUG
(uint64_t)0,
&ra,
&size);
"==> nxge_init_hv_fzc_txdma_channel_pages: channel %d "
"ok status 0x%x "
"(page 0 data buf) hverr 0x%llx "
"set ioaddr_pp $%p "
"set size 0x%llx "
"get ra ioaddr_pp $%p "
"get size 0x%llx ",
err,
ra,
size));
#endif
"==> nxge_init_hv_fzc_txdma_channel_pages: channel %d "
"(page 0 data buf) hverr 0x%llx "
"ioaddr_pp $%p "
"size 0x%llx ",
/*
* Initialize logical page 2 for control buffers.
*/
(uint64_t)1,
"==> nxge_init_hv_fzc_txdma_channel_pages: channel %d"
"ok status 0x%x "
"(page 1 cntl buf) hverr 0x%llx "
"ioaddr_pp $%p "
"size 0x%llx ",
err,
if (err != 0) {
"<== nxge_init_hv_fzc_txdma_channel_pages: channel %d"
"error status 0x%x "
"(page 1 cntl buf) hverr 0x%llx "
"ioaddr_pp $%p "
"size 0x%llx ",
err,
return (NXGE_ERROR | err);
}
#ifdef DEBUG
(uint64_t)1,
&ra,
&size);
"==> nxge_init_hv_fzc_txdma_channel_pages: channel %d "
"(page 1 cntl buf) hverr 0x%llx "
"set ioaddr_pp $%p "
"set size 0x%llx "
"get ra ioaddr_pp $%p "
"get size 0x%llx ",
ra,
size));
#endif
"<== nxge_init_hv_fzc_txdma_channel_pages"));
return (NXGE_OK);
}
/*ARGSUSED*/
{
int err;
#ifdef DEBUG
#endif
"==> nxge_init_hv_fzc_rxdma_channel_pages"));
return (NXGE_OK);
}
/* Initialize data buffers for page 0 */
(uint64_t)0,
if (err != 0) {
"<== nxge_init_hv_fzc_rxdma_channel_pages: channel %d"
"error status 0x%x "
"(page 0 data buf) hverr 0x%llx "
"ioaddr_pp $%p "
"size 0x%llx ",
err,
return (NXGE_ERROR | err);
}
#ifdef DEBUG
(uint64_t)0,
&ra,
&size);
"==> nxge_init_hv_fzc_rxdma_channel_pages: channel %d "
"ok status 0x%x "
"(page 0 data buf) hverr 0x%llx "
"set databuf ioaddr_pp $%p "
"set databuf size 0x%llx "
"get databuf ra ioaddr_pp %p "
"get databuf size 0x%llx",
err,
ra,
size));
#endif
/* Initialize control buffers for logical page 1. */
(uint64_t)1,
if (err != 0) {
"<== nxge_init_hv_fzc_rxdma_channel_pages: channel %d"
"error status 0x%x "
"(page 1 cntl buf) hverr 0x%llx "
"ioaddr_pp $%p "
"size 0x%llx ",
err,
return (NXGE_ERROR | err);
}
#ifdef DEBUG
(uint64_t)1,
&ra,
&size);
"==> nxge_init_hv_fzc_rxdma_channel_pages: channel %d "
"error status 0x%x "
"(page 1 cntl buf) hverr 0x%llx "
"set cntl ioaddr_pp $%p "
"set cntl size 0x%llx "
"get cntl ioaddr_pp $%p "
"get cntl size 0x%llx ",
err,
ra,
size));
#endif
"<== nxge_init_hv_fzc_rxdma_channel_pages"));
return (NXGE_OK);
}
/*
* Map hypervisor error code to errno. Only
* H_ENORADDR, H_EBADALIGN and H_EINVAL are meaningful
* for niu driver. Any other error codes are mapped to EINVAL.
*/
static int
{
int s_errcode;
switch (hv_errcode) {
case H_ENORADDR:
case H_EBADALIGN:
break;
case H_EOK:
s_errcode = 0;
break;
default:
break;
}
return (s_errcode);
}
#endif /* sun4v and NIU_LP_WORKAROUND */