npi_rxdma.h revision 4496171313bed39e96f21bc2f9faf2868e267ae3
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _NPI_RXDMA_H
#define _NPI_RXDMA_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
#include <npi.h>
#include "nxge_defs.h"
#include "nxge_hw.h"
#include <nxge_rxdma_hw.h>
/*
* Register offset (0x200 bytes for each channel) for receive ring registers.
*/
#define NXGE_RXDMA_OFFSET(x, v, channel) (x + \
(!v ? DMC_OFFSET(channel) : \
#define REG_RDC_TABLE_OFFSET(table) \
}
channel)))
}
/*
* RX NPI error codes
*/
#define RXDMA_ID_SHIFT(n) (n << NPI_PORT_CHAN_SHIFT)
#define NPI_RXDMA_ERROR RXDMA_ER_ST
#define NPI_RXDMA_CHANNEL_INVALID(n) (RXDMA_ID_SHIFT(n) | \
#define NPI_RXDMA_OPCODE_INVALID(n) (RXDMA_ID_SHIFT(n) | \
#define RXDMA_CHANNEL_VALID(rdc) \
((rdc < NXGE_MAX_RDCS))
#define RXDMA_PORT_VALID(port) \
((port < MAX_PORTS_PER_NXGE))
#define RXDMA_TABLE_VALID(table) \
((table < NXGE_MAX_RDC_GROUPS))
#define RXDMA_PAGE_VALID(page) \
#define RXDMA_BUFF_OFFSET_VALID(offset) \
((offset == SW_OFFSET_NO_OFFSET) || \
(offset == SW_OFFSET_64) || \
(offset == SW_OFFSET_128))
/*
* RXDMA NPI defined control types.
*/
typedef enum _rxdma_cs_cntl_e {
RXDMA_CS_CLEAR_ALL = 0x1,
RXDMA_MEX_SET = 0x2,
RXDMA_RCRTO_CLEAR = 0x8,
RXDMA_PT_DROP_PKT_CLEAR = 0x10,
RXDMA_WRED_DROP_CLEAR = 0x20,
RXDMA_RCR_SFULL_CLEAR = 0x40,
RXDMA_RCR_FULL_CLEAR = 0x80,
RXDMA_RBR_PRE_EMPTY_CLEAR = 0x100,
RXDMA_RBR_EMPTY_CLEAR = 0x200
/*
* RXDMA NPI defined event masks (mapped to the hardware defined masks).
*/
typedef enum _rxdma_ent_msk_cfg_e {
typedef union _addr44 {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} addr44_t;
/*
* npi_rxdma_cfg_default_port_rdc()
* Set the default rdc for the port
*
* Inputs:
* handle: register handle interpreted by the underlying OS
* portnm: Physical Port Number
* rdc: RX DMA Channel number
*
* Return:
* NPI_SUCCESS
* NPI_RXDMA_RDC_INVALID
* NPI_RXDMA_PORT_INVALID
*
*/
/*
* npi_rxdma_cfg_rdc_table()
*
* Inputs:
* handle: register handle interpreted by the underlying OS
* table: RDC Group Number
* rdc[]: Array of RX DMA Channels
*
* Return:
* NPI_SUCCESS
* NPI_RXDMA_TABLE_INVALID
*
*/
uint8_t);
/*
* npi_rxdma_32bitmode_enable()
* Enable 32 bit mode
*
* Inputs:
* handle: register handle interpreted by the underlying OS
*
* Return:
* NPI_SUCCESS
* NPI_FAILURE
* NPI_HW_ERR
*
*/
/*
* npi_rxdma_32bitmode_disable()
* disable 32 bit mode
*
* Inputs:
* handle: register handle interpreted by the underlying OS
*
* Return:
* NPI_SUCCESS
* NPI_FAILURE
* NPI_HW_ERR
*
*/
/*
* npi_rxdma_cfg_ram_access_enable()
* Enable PIO access to shadow and prefetch memory.
* In the case of DMA errors, software may need to
* initialize the shadow and prefetch memories to
* sane value (may be clear it) before re-enabling
* the DMA channel.
*
* Inputs:
* handle: register handle interpreted by the underlying OS
*
* Return:
* NPI_SUCCESS
* NPI_FAILURE
* NPI_HW_ERR
*
*/
/*
* npi_rxdma_cfg_ram_access_disable()
* Disable PIO access to shadow and prefetch memory.
* This is the normal operation mode.
*
* Inputs:
* handle: register handle interpreted by the underlying OS
*
* Return:
* NPI_SUCCESS
* NPI_FAILURE
* NPI_HW_ERR
*
*/
/*
* npi_rxdma_cfg_clock_div_set()
* init the clock division, used for RX timers
* This determines the granularity of RX DMA countdown timers
* It depends on the system clock. For example if the system
* clock is 300 MHz, a value of 30000 will yield a granularity
* of 100usec.
*
* Inputs:
* handle: register handle interpreted by the underlying OS
* count: System clock divider
*
* Return:
* NPI_SUCCESS
* NPI_FAILURE
* NPI_SW_ERR
* NPI_HW_ERR
*
*/
/*
* npi_rxdma_cfg_red_rand_init()
* init the WRED Discard
* By default, it is enabled
*
* Inputs:
* handle: register handle interpreted by the underlying OS
* init_value: WRED init value
*
* Return:
* NPI_SUCCESS
* NPI_FAILURE
* NPI_SW_ERR
* NPI_HW_ERR
*
*/
/*
* npi_rxdma_cfg_wred_disable()
* init the WRED Discard
* By default, it is enabled
*
* Inputs:
* handle: register handle interpreted by the underlying OS
*
* Return:
* NPI_SUCCESS
* NPI_FAILURE
* NPI_SW_ERR
* NPI_HW_ERR
*
*/
/*
* npi_rxdma_cfg_wred_param()
* COnfigure per rxdma channel WRED parameters
* By default, it is enabled
*
* Inputs:
* handle: register handle interpreted by the underlying OS
* rdc: RX DMA Channel number
* wred_params: WRED configuration parameters
*
* Return:
* NPI_SUCCESS
* NPI_FAILURE
* NPI_SW_ERR
* NPI_HW_ERR
*
*/
rdc_red_para_t *);
/*
* npi_rxdma_port_ddr_weight
* Set the DDR weight for a port.
*
* Inputs:
* handle: register handle interpreted by the underlying OS
* portnm: Physical Port Number
* weight: Port relative weight (in approx. bytes)
* Default values are:
* 0x400 (port 0 and 1) corresponding to 10 standard
* size (1500 bytes) Frames
* 0x66 (port 2 and 3) corresponding to 10% 10Gig ports
*
* Return:
* NPI_SUCCESS
* NPI_FAILURE
* NPI_HW_ERR
* NPI_SW_ERR
*
*/
/*
* npi_rxdma_port_usage_get()
* Gets the port usage, in terms of 16 byte blocks
*
* NOTE: The register count is cleared upon reading.
*
* Inputs:
* handle: register handle interpreted by the underlying OS
* portnm: Physical Port Number
* blocks: ptr to save current count.
*
* Return:
* NPI_SUCCESS
* NPI_FAILURE
* NPI_HW_ERR
* NPI_SW_ERR
*
*/
/*
* npi_rxdma_cfg_logical_page()
* Configure per rxdma channel Logical page
*
* To disable the logical page, set valid = 0;
*
* Inputs:
* handle: register handle interpreted by the underlying OS
* rdc: RX DMA Channel number
* page_params: Logical Page configuration parameters
*
* Return:
* NPI_SUCCESS
* NPI_FAILURE
* NPI_SW_ERR
* NPI_HW_ERR
*
*/
dma_log_page_t *);
/*
* npi_rxdma_cfg_logical_page_handle()
* Configure per rxdma channel Logical page handle
*
*
* Inputs:
* handle: register handle interpreted by the underlying OS
* rdc: RX DMA Channel number
* pg_handle: Logical Page handle
*
* Return:
* NPI_SUCCESS
* NPI_FAILURE
* NPI_SW_ERR
* NPI_HW_ERR
*
*/
uint64_t);
typedef enum _bsize {
SIZE_0B = 0x0,
} bsize_t;
/*
* npi_rxdma_cfg_rdc_ring()
* Configure The RDC channel Rcv Buffer Ring
*
* Inputs:
* rdc: RX DMA Channel number
* rdc_params: RDC configuration parameters
*
* Return:
* NPI_SUCCESS
* NPI_FAILURE
* NPI_SW_ERR
* NPI_HW_ERR
*
*/
typedef struct _rdc_desc_cfg_t {
rdc_desc_cfg_t *);
/*
* npi_rxdma_rdc_rcr_flush
* Forces RX completion ring update
*
* Inputs:
* rdc: RX DMA Channel number
*
* Return:
*
*/
(RCR_FLSH_SET << RCR_FLSH_SHIFT))
/*
* npi_rxdma_rdc_rcr_read_update
* Update the number of rcr packets and buffers processed
*
* Inputs:
* channel: RX DMA Channel number
* num_pkts: Number of pkts processed by SW.
* A packet could constitute multiple
* buffers, in case jumbo packets.
* num_bufs: Number of buffer processed by SW.
*
* Return:
* NPI_FAILURE -
* NPI_RXDMA_OPCODE_INVALID -
* NPI_RXDMA_CHANNEL_INVALID -
*
*/
/*
* npi_rxdma_rdc_rcr_pktread_update
* Update the number of packets processed
*
* Inputs:
* channel: RX DMA Channel number
* num_pkts: Number ofpkts processed by SW.
* A packet could constitute multiple
* buffers, in case jumbo packets.
*
* Return:
* NPI_FAILURE -
* NPI_RXDMA_OPCODE_INVALID -
* NPI_RXDMA_CHANNEL_INVALID -
*
*/
/*
* npi_rxdma_rdc_rcr_bufread_update
* Update the number of buffers processed
*
* Inputs:
* channel: RX DMA Channel number
* num_bufs: Number of buffer processed by SW. Multiple buffers
* could be part of a single packet.
*
* Return:
* NPI_FAILURE -
* NPI_RXDMA_OPCODE_INVALID -
* NPI_RXDMA_CHANNEL_INVALID -
*
*/
/*
* npi_rxdma_rdc_rbr_kick
* Kick RDC RBR
*
* Inputs:
* rdc: RX DMA Channel number
* num_buffers: Number of Buffers posted to the RBR
*
* Return:
*
*/
/*
* npi_rxdma_rdc_rbr_head_get
* Gets the current rbr head pointer.
*
* Inputs:
* rdc: RX DMA Channel number
* hdptr ptr to write the rbr head value
*
* Return:
*
*/
/*
* npi_rxdma_rdc_rbr_stat_get
* Returns the RBR stat. The stat consists of the
* RX buffers in the ring. It also indicates if there
* has been an overflow.
*
* Inputs:
* rdc: RX DMA Channel number
* rbr_stat_t: Structure to update stat
*
* Return:
*
*/
rbr_stat_t *);
/*
* npi_rxdma_cfg_rdc_reset
* Resets the RDC channel
*
* Inputs:
* rdc: RX DMA Channel number
*
* Return:
*
*/
/*
* npi_rxdma_rdc_enable
* Enables the RDC channel
*
* Inputs:
* rdc: RX DMA Channel number
*
* Return:
*
*/
/*
* npi_rxdma_rdc_disable
* Disables the RDC channel
*
* Inputs:
* rdc: RX DMA Channel number
*
* Return:
*
*/
/*
* npi_rxdma_cfg_rdc_rcr_timeout()
* Configure The RDC channel completion ring timeout.
* If a frame has been received, an event would be
* generated atleast at the expiration of the timeout.
*
* Enables timeout by default.
*
* Inputs:
* rdc: RX DMA Channel number
* rcr_timeout: Completion Ring timeout value
*
* Return:
* NPI_SUCCESS
* NPI_FAILURE
* NPI_SW_ERR
* NPI_HW_ERR
*
*/
uint8_t);
/*
* npi_rxdma_cfg_rdc_rcr_threshold()
* Configure The RDC channel completion ring threshold.
* An event would be If the number of frame received,
* surpasses the threshold value
*
* Inputs:
* rdc: RX DMA Channel number
* rcr_threshold: Completion Ring Threshold count
*
* Return:
* NPI_SUCCESS
* NPI_FAILURE
* NPI_SW_ERR
* NPI_HW_ERR
*
*/
uint16_t);
typedef struct _rdc_error_stat_t {
#if OLD
/*
* npi_rxdma_rdc_error_stat_get
* Gets the current Error stat for the RDC.
*
* Inputs:
* rdc: RX DMA Channel number
* error_stat Structure to write current RDC Error stat
*
* Return:
*
*/
uint8_t, rdc_error_stat_t *);
#endif
/*
* npi_rxdma_rdc_rcr_tail_get
* Gets the current RCR tail address for the RDC.
*
* Inputs:
* rdc: RX DMA Channel number
* tail_addr Structure to write current RDC RCR tail address
*
* Return:
*
*/
typedef struct _rdc_discard_stat_t {
/*
* npi_rxdma_rdc_discard_stat_get
* Gets the current discrad stats for the RDC.
*
* Inputs:
* rdc: RX DMA Channel number
* rcr_stat Structure to write current RDC discard stat
*
* Return:
*
*/
/*
* npi_rx_port_discard_stat_get
* Gets the current input (IPP) discrad stats for the rx port.
*
* Inputs:
* rdc: RX DMA Channel number
* rx_disc_cnt_t Structure to write current RDC discard stat
*
* Return:
*
*/
rx_disc_cnt_t *);
/*
* npi_rxdma_red_discard_stat_get
* Gets the current discrad count due RED
* The counter overflow bit is cleared, if it has been set.
*
* Inputs:
* rdc: RX DMA Channel number
* rx_disc_cnt_t Structure to write current RDC discard stat
*
* Return:
* NPI_SUCCESS
* NPI_RXDMA_RDC_INVALID
*
*/
rx_disc_cnt_t *);
/*
* npi_rxdma_red_discard_oflow_clear
* Clear RED discard counter overflow bit
*
* Inputs:
* rdc: RX DMA Channel number
*
* Return:
* NPI_SUCCESS
* NPI_RXDMA_RDC_INVALID
*
*/
uint8_t);
/*
* npi_rxdma_misc_discard_stat_get
* Gets the current discrad count for the rdc due to
* buffer pool empty
* The counter overflow bit is cleared, if it has been set.
*
* Inputs:
* rdc: RX DMA Channel number
* rx_disc_cnt_t Structure to write current RDC discard stat
*
* Return:
* NPI_SUCCESS
* NPI_RXDMA_RDC_INVALID
*
*/
rx_disc_cnt_t *);
/*
* npi_rxdma_red_discard_oflow_clear
* Clear RED discard counter overflow bit
* clear the overflow bit for buffer pool empty discrad counter
* for the rdc
*
*
* Inputs:
* rdc: RX DMA Channel number
*
* Return:
* NPI_SUCCESS
* NPI_RXDMA_RDC_INVALID
*
*/
uint8_t);
/*
* npi_rxdma_ring_perr_stat_get
* Gets the current RDC Memory parity error
* The counter overflow bit is cleared, if it has been set.
*
* Inputs:
* pre_cnt: Structure to write current RDC Prefetch memory
* Parity Error stat
* sha_cnt: Structure to write current RDC Shadow memory
* Parity Error stat
*
* Return:
* NPI_SUCCESS
* NPI_RXDMA_RDC_INVALID
*
*/
/*
* npi_rxdma_ring_perr_stat_get
* Clear RDC Memory Parity Error counter overflow bits
*
* Inputs:
* Return:
* NPI_SUCCESS
*
*/
/* Access the RDMC Memory: used for debugging */
rdmc_mem_access_t *, uint8_t);
/*
* npi_rxdma_rxctl_fifo_error_intr_set
* Configure The RX ctrl fifo error interrupt generation
*
* Inputs:
* mask: rx_ctl_dat_fifo_mask_t specifying the errors
*
* Return:
* NPI_SUCCESS
* NPI_FAILURE
*
*/
/*
* npi_rxdma_rxctl_fifo_error_status_get
* Read The RX ctrl fifo error Status
*
* Inputs:
* stat: rx_ctl_dat_fifo_stat_t to read the errors to
* valid fields in rx_ctl_dat_fifo_stat_t structure are:
* zcp_eop_err, ipp_eop_err, id_mismatch.
* Return:
* NPI_SUCCESS
* NPI_FAILURE
*
*/
/*
* npi_rxdma_channel_mex_set():
* This function is called to arm the DMA channel with
* mailbox updating capability. Software needs to rearm
* for each update by writing to the control and status register.
*
* Parameters:
* handle - NPI handle (virtualization flag must be defined).
* channel - logical RXDMA channel from 0 to 23.
* (If virtualization flag is not set, then
* logical channel is the same as the hardware
* channel number).
*
* Return:
* NPI_SUCCESS - If enable channel with mailbox update
* is complete successfully.
*
* Error:
* NPI_FAILURE -
* NPI_RXDMA_CHANNEL_INVALID -
*/
/*
* npi_rxdma_channel_rcrto_clear():
* This function is called to reset RCRTO bit to 0.
*
* Parameters:
* handle - NPI handle (virtualization flag must be defined).
* channel - logical RXDMA channel from 0 to 23.
* (If virtualization flag is not set, then
* logical channel is the same as the hardware
* channel number).
* Return:
* NPI_SUCCESS
*
* Error:
* NPI_FAILURE -
* NPI_RXDMA_CHANNEL_INVALID -
*/
/*
* npi_rxdma_channel_pt_drop_pkt_clear():
* This function is called to clear the port drop packet bit (debug).
*
* Parameters:
* handle - NPI handle (virtualization flag must be defined).
* channel - logical RXDMA channel from 0 to 23.
* (If virtualization flag is not set, then
* logical channel is the same as the hardware
* channel number).
* Return:
* NPI_SUCCESS
*
* Error:
* NPI_FAILURE -
* NPI_RXDMA_CHANNEL_INVALID -
*/
/*
* npi_rxdma_channel_wred_drop_clear():
* This function is called to wred drop bit (debug only).
*
* Parameters:
* handle - NPI handle (virtualization flag must be defined).
* channel - logical RXDMA channel from 0 to 23.
* (If virtualization flag is not set, then
* logical channel is the same as the hardware
* channel number).
* Return:
* NPI_SUCCESS
*
* Error:
* NPI_FAILURE -
* NPI_RXDMA_CHANNEL_INVALID -
*/
/*
* npi_rxdma_channel_rcr_shfull_clear():
* This function is called to clear RCR shadow full bit.
*
* Parameters:
* handle - NPI handle (virtualization flag must be defined).
* channel - logical RXDMA channel from 0 to 23.
* (If virtualization flag is not set, then
* logical channel is the same as the hardware
* channel number).
* Return:
* NPI_SUCCESS
*
* Error:
* NPI_FAILURE -
* NPI_RXDMA_CHANNEL_INVALID -
*/
/*
* npi_rxdma_channel_rcrfull_clear():
* This function is called to clear RCR full bit.
*
* Parameters:
* handle - NPI handle (virtualization flag must be defined).
* channel - logical RXDMA channel from 0 to 23.
* (If virtualization flag is not set, then
* logical channel is the same as the hardware
* channel number).
* Return:
* NPI_SUCCESS
*
* Error:
* NPI_FAILURE -
* NPI_RXDMA_CHANNEL_INVALID -
*/
/*
* npi_rxdma_rbr_pre_empty_clear():
* This function is called to control a receive DMA channel
* for arming the channel with mailbox updates, resetting
* various event status bits (control and status register).
*
* Parameters:
* handle - NPI handle (virtualization flag must be defined).
* control - NPI defined control type supported:
* - RXDMA_MEX_SET
* - RXDMA_RCRTO_CLEAR
* - RXDMA_PT_DROP_PKT_CLEAR
* - RXDMA_WRED_DROP_CLEAR
* - RXDMA_RCR_SFULL_CLEAR
* - RXDMA_RCR_FULL_CLEAR
* - RXDMA_RBR_PRE_EMPTY_CLEAR
* channel - logical RXDMA channel from 0 to 23.
* (If virtualization flag is not set, then
* logical channel is the same as the hardware.
* Return:
* NPI_SUCCESS
*
* Error:
* NPI_FAILURE -
* NPI_RXDMA_CHANNEL_INVALID -
*/
/*
* npi_rxdma_channel_control():
* This function is called to control a receive DMA channel
* for arming the channel with mailbox updates, resetting
* various event status bits (control and status register).
*
* Parameters:
* handle - NPI handle (virtualization flag must be defined).
* control - NPI defined control type supported:
* - RXDMA_MEX_SET
* - RXDMA_RCRTO_CLEAR
* - RXDMA_PT_DROP_PKT_CLEAR
* - RXDMA_WRED_DROP_CLEAR
* - RXDMA_RCR_SFULL_CLEAR
* - RXDMA_RCR_FULL_CLEAR
* - RXDMA_RBR_PRE_EMPTY_CLEAR
* channel - logical RXDMA channel from 0 to 23.
* (If virtualization flag is not set, then
* logical channel is the same as the hardware.
* Return:
* NPI_SUCCESS
*
* Error:
* NPI_FAILURE -
* NPI_TXDMA_OPCODE_INVALID -
* NPI_TXDMA_CHANNEL_INVALID -
*/
/*
* npi_rxdma_control_status():
* This function is called to operate on the control
* and status register.
*
* Parameters:
* handle - NPI handle
* op_mode - OP_GET: get hardware control and status
* OP_SET: set hardware control and status
* OP_UPDATE: update hardware control and status.
* OP_CLEAR: clear control and status register to 0s.
* channel - hardware RXDMA channel from 0 to 23.
* cs_p - pointer to hardware defined control and status
* structure.
* Return:
* NPI_SUCCESS
*
* Error:
* NPI_FAILURE -
* NPI_RXDMA_OPCODE_INVALID -
* NPI_RXDMA_CHANNEL_INVALID -
*/
/*
* npi_rxdma_event_mask():
* This function is called to operate on the event mask
* register which is used for generating interrupts.
*
* Parameters:
* handle - NPI handle
* op_mode - OP_GET: get hardware event mask
* OP_SET: set hardware interrupt event masks
* OP_CLEAR: clear control and status register to 0s.
* channel - hardware RXDMA channel from 0 to 23.
* mask_p - pointer to hardware defined event mask
* structure.
* Return:
* NPI_SUCCESS - If set is complete successfully.
*
* Error:
* NPI_FAILURE -
* NPI_RXDMA_OPCODE_INVALID -
* NPI_RXDMA_CHANNEL_INVALID -
*/
/*
* npi_rxdma_event_mask_config():
* This function is called to operate on the event mask
* register which is used for generating interrupts
* and status register.
*
* Parameters:
* handle - NPI handle
* op_mode - OP_GET: get hardware event mask
* OP_SET: set hardware interrupt event masks
* OP_CLEAR: clear control and status register to 0s.
* channel - hardware RXDMA channel from 0 to 23.
* cfgp - pointer to NPI defined event mask
* enum data type.
* Return:
* NPI_SUCCESS - If set is complete successfully.
*
* Error:
* NPI_FAILURE -
* NPI_RXDMA_OPCODE_INVALID -
* NPI_RXDMA_CHANNEL_INVALID -
*/
/*
* npi_rxdma_dump_rdc_regs
* Dumps the contents of rdc csrs and fzc registers
*
* Input:
* rdc: RX DMA number
*
* return:
* NPI_SUCCESS
* NPI_FAILURE
* NPI_RXDMA_RDC_INVALID
*
*/
/*
* npi_rxdma_dump_fzc_regs
* Dumps the contents of rdc csrs and fzc registers
*
* Input:
* rdc: RX DMA number
*
* return:
* NPI_SUCCESS
* NPI_FAILURE
* NPI_RXDMA_RDC_INVALID
*
*/
uint8_t);
#ifdef __cplusplus
}
#endif
#endif /* _NPI_RXDMA_H */