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ea1a228c80597366447774aa1988868492330eb5schwartz * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
ea1a228c80597366447774aa1988868492330eb5schwartz * Use is subject to license terms.
ea1a228c80597366447774aa1988868492330eb5schwartz#pragma ident "%Z%%M% %I% %E% SMI"
ea1a228c80597366447774aa1988868492330eb5schwartz * "Virtual register" definitions for the bit error performance counters.
ea1a228c80597366447774aa1988868492330eb5schwartz * The N2 PIU presents two bit error counters. Bit 63 on the first counter
ea1a228c80597366447774aa1988868492330eb5schwartz * serves as an enable for all bit error counters. Bit 62 serves as a clear
ea1a228c80597366447774aa1988868492330eb5schwartz * for all the bit error counters.
ea1a228c80597366447774aa1988868492330eb5schwartz * Busstat doesn't play well with a register that has counters, enable and
ea1a228c80597366447774aa1988868492330eb5schwartz * clear, so this module presents to the rest of the driver and to busstat a
ea1a228c80597366447774aa1988868492330eb5schwartz * new layered set of register interfaces.
ea1a228c80597366447774aa1988868492330eb5schwartz * These are:
ea1a228c80597366447774aa1988868492330eb5schwartz * SW_N2PIU_BITERR_CNT1_DATA Biterr counter 1 data (readonly)
ea1a228c80597366447774aa1988868492330eb5schwartz * Maps directly to HW biterr
ea1a228c80597366447774aa1988868492330eb5schwartz * counter 1. Returns data for
ea1a228c80597366447774aa1988868492330eb5schwartz * bad_dllps, bad_tlps,
ea1a228c80597366447774aa1988868492330eb5schwartz * phys_rcvr_errs
ea1a228c80597366447774aa1988868492330eb5schwartz * SW_N2PIU_BITERR_CNT2_DATA Biterr counter 2 data (readonly)
ea1a228c80597366447774aa1988868492330eb5schwartz * Maps to HW biterr counter 2, but
ea1a228c80597366447774aa1988868492330eb5schwartz * offers evt select of individual
ea1a228c80597366447774aa1988868492330eb5schwartz * lanes 0-7 or all lanes together
ea1a228c80597366447774aa1988868492330eb5schwartz * SW_N2PIU_BITERR_CLR Setting bit 62 here clears all biterr
ea1a228c80597366447774aa1988868492330eb5schwartz * counters (write-only)
ea1a228c80597366447774aa1988868492330eb5schwartz * SW_N2PIU_BITERR_SEL Bit 63 is overall biterr enable.
ea1a228c80597366447774aa1988868492330eb5schwartz * Bits 0-3 are event select for counter 2
ea1a228c80597366447774aa1988868492330eb5schwartz * (read-write)
ea1a228c80597366447774aa1988868492330eb5schwartz * Note: each is assigned an offset similar to the offset of real performance
ea1a228c80597366447774aa1988868492330eb5schwartz * counter registers. Offsets for these registers extend beyond the real reg
ea1a228c80597366447774aa1988868492330eb5schwartzextern "C" {
ea1a228c80597366447774aa1988868492330eb5schwartz/* SW abstractions for the BITERR counters. */
ea1a228c80597366447774aa1988868492330eb5schwartz/* Select register. Select enable for all biterr ctrs, and PIC3 events. */
ea1a228c80597366447774aa1988868492330eb5schwartz#define SW_N2PIU_BITERR_SEL HVIO_N2PIU_PERFREG_NUM_REGS
ea1a228c80597366447774aa1988868492330eb5schwartz/* Clear register. This zeros out all biterr ctrs. */
ea1a228c80597366447774aa1988868492330eb5schwartz#define SW_N2PIU_BITERR_CLR (HVIO_N2PIU_PERFREG_NUM_REGS + 1)
ea1a228c80597366447774aa1988868492330eb5schwartz/* Biterr counter 1. Same as in the PRM. */
ea1a228c80597366447774aa1988868492330eb5schwartz#define SW_N2PIU_BITERR_CNT1_DATA (HVIO_N2PIU_PERFREG_NUM_REGS + 2)
ea1a228c80597366447774aa1988868492330eb5schwartz * Biterr counter 2. Reports errors for all lanes, or for any individual lane.
ea1a228c80597366447774aa1988868492330eb5schwartz * Select what to report with the SELect register above. Enabled only if the
ea1a228c80597366447774aa1988868492330eb5schwartz * enable for all biterr counters is enabled.
ea1a228c80597366447774aa1988868492330eb5schwartz#define SW_N2PIU_BITERR_CNT2_DATA (HVIO_N2PIU_PERFREG_NUM_REGS + 3)
ea1a228c80597366447774aa1988868492330eb5schwartz/* Biterr counter abstraction functions. */
ea1a228c80597366447774aa1988868492330eb5schwartzextern int n2piupc_biterr_attach(void **);
ea1a228c80597366447774aa1988868492330eb5schwartzextern void n2piupc_biterr_detach(void *);
ea1a228c80597366447774aa1988868492330eb5schwartzextern int n2piupc_biterr_write(n2piupc_t *n2piupc_p, int regid, uint64_t data);
ea1a228c80597366447774aa1988868492330eb5schwartzextern int n2piupc_biterr_read(n2piupc_t *n2piupc_p, int regid, uint64_t *data);
ea1a228c80597366447774aa1988868492330eb5schwartz#endif /* _N2PIUPC_BITERR_H */