rock_asm.s revision c38855f9a86ebf0c18994ef3e272eda3aa745567
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#include <sys/asm_linkage.h>
#include <sys/rock_hypervisor_api.h>
#if defined(lint)
void
cpu_smt_pause(void)
{}
void
fp_zero(void)
{}
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
void
{}
void
cpu_atomic_delay(void)
{}
void
rock_mutex_delay(void)
{}
#else /* lint */
/*
* Called from various spin loops to prevent this strand from
* stealing too many cycles from its sibling, who is presumably
* doing useful work.
*
* With a 2.1 GHz clock, 100 membar #Halt instructions plus
* That is a suitable time for a PAUSE, as it is roughly equal to
* two memory accesses.
*/
/*
* fp_zero() - clear all fp data registers and the fsr
*/
.align 8
.xword 0
/* hcalls for performance counters */
/*
* uint64_t hv_rk_perf_count_init(uint64_t counter);
*/
/*
* uint64_t hv_rk_perf_count_release(uint64_t counter);
*/
/*
* uint64_t hv_rk_perf_count_set(uint64_t counter, uint64_t value)
*/
/*
* uint64_t hv_rk_perf_count_get(uint64_t counter, uint64_t *value)
*/
/*
* uint64_t hv_rk_perf_count_start(uint64_t counter, uint64_t value)
*/
/*
* uint64_t hv_rk_perf_count_overflow(uint64_t counter,
* uint64_t *ovf_cnt)
*/
/*
* uint64_t hv_rk_perf_count_stop(uint64_t counter)
*/
/*
* uint64_t hv_rk_perf_sample_init(uint64_t counter,
uint64_t ringbuf_pa)
*/
/*
* uint64_t hv_rk_perf_sample_release(uint64_t counter)
*/
/*
* uint64_t hv_rk_perf_sample_config(uint64_t sampler, uint64_t reg_va,
* uint64_t reg_value)
*/
/*
* uint64_t hv_rk_perf_sample_start(uint64_t sampler, uint64_t freq,
* uint64_t list_size, uint64_t valist_pa)
*/
/*
* uint64_t hv_rk_perf_sample_pending(uint64_t sampler,
* uint64_t *pend_cnt)
*/
/*
* uint64_t hv_rk_perf_sample_stop(uint64_t sampler)
*/
/*
* Invalidate all of the entries within the TSB, by setting the inv bit
* in the tte_tag field of each tsbe.
*
* We take advantage of the fact that the TSBs are page aligned and a
* multiple of PAGESIZE to use ASI_BLK_INIT_xxx ASI.
*
* See TSB_LOCK_ENTRY and the miss handlers for how this works in practice
* (in short, we set all bits in the upper word of the tag, and we give the
* invalid bit precedence over other tag bits in both places).
*/
#define VIS_BLOCKSIZE 64
#include "assym.h" /* T_PREEMPT */
! kpreempt_disable();
.cpu_inv_blkstart:
stda %d32, [%i0+128]%asi
stda %d32, [%i0+64]%asi
stda %d32, [%i0]%asi
add %i0, %i4, %i0
sub %i1, %i4, %i1
.cpu_inv_doblock:
cmp %i1, (4*VIS_BLOCKSIZE) ! check for completion
bgeu,a %icc, .cpu_inv_blkstart
stda %d32, [%i0+192]%asi
.cpu_inv_finish:
membar #Sync
brz,a %l2, .cpu_inv_finished
wr %l0, 0, %fprs ! restore fprs
! restore fpregs from stack
ldda [%l1]ASI_BLK_P, %d32
membar #Sync
wr %l0, 0, %fprs ! restore fprs
.cpu_inv_finished:
! kpreempt_enable();
ldsb [THREAD_REG + T_PREEMPT], %l3
dec %l3
stb %l3, [THREAD_REG + T_PREEMPT]
ret
restore
SET_SIZE(cpu_inv_tsb)
/*
* This is CPU specific delay routine for atomic backoff.
* It is used in case of Rock CPU. The rd instruction uses
* less resources than casx on these CPUs.
*/
.align 32
ENTRY(cpu_atomic_delay)
rd %ccr, %g0
rd %ccr, %g0
retl
rd %ccr, %g0
SET_SIZE(cpu_atomic_delay)
/*
* Delay to last ~100 nano seconds on a 2.1 GHz. Membars
* should be linear and not in a loop to avoid impact
* on the sibling strand (BR pipeline is shared by
* two sibling strands).
*/
.align 64
ENTRY(rock_mutex_delay)
membar #Halt
membar #Halt
membar #Halt
membar #Halt
membar #Halt
membar #Halt
membar #Halt
membar #Halt
membar #Halt
membar #Halt
membar #Halt
membar #Halt
membar #Halt
membar #Halt
membar #Halt
membar #Halt
membar #Halt
membar #Halt
membar #Halt
retl
membar #Halt
SET_SIZE(rock_mutex_delay)
#endif /* lint */