niagara_asm.s revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#if !defined(lint)
#include "assym.h"
#endif
/*
* Niagara processor specific assembly routines
*/
#include <sys/asm_linkage.h>
#include <sys/machparam.h>
#include <sys/hypervisor_api.h>
#include <sys/niagararegs.h>
#include <sys/niagaraasi.h>
#include <vm/hat_sfmmu.h>
#if defined(lint)
/*ARGSUSED*/
{ return (0); }
/*ARGSUSED*/
{ return (0); }
#else /* lint */
/*
* hv_niagara_getperf(uint64_t perfreg, uint64_t *datap)
*/
1:
/*
* hv_niagara_setperf(uint64_t perfreg, uint64_t data)
*/
#endif /* !lint */
#if defined (lint)
/*
* Invalidate all of the entries within the TSB, by setting the inv bit
* in the tte_tag field of each tsbe.
*
* We take advantage of the fact that the TSBs are page aligned and a
* multiple of PAGESIZE to use ASI_BLK_INIT_xxx ASI.
*
* See TSB_LOCK_ENTRY and the miss handlers for how this works in practice
* (in short, we set all bits in the upper word of the tag, and we give the
* invalid bit precedence over other tag bits in both places).
*/
/*ARGSUSED*/
void
{}
#else /* lint */
/*
* The following code assumes that the tsb_base (%o0) is 256 bytes
* aligned and the tsb_bytes count is multiple of 256 bytes.
*/
1:
#endif /* lint */
#ifdef NIAGARA_ERRATUM_39
/*
* This workaround will be removed prior to the FCS release.
*/
#if defined(lint)
/*ARGSUSED*/
{ return (0); }
#else /* lint */
/*
* The following hypervisor calls are used to get the CPU version register
* for the workaround.
*/
#define HV_DIAG_RA2PA 0x200
#define HV_DIAG_HEXEC 0x201
/*
* niagara_getver(uint64_t ni_getver_ra, uint64_t *cpu_version)
*/
2:
/*
* Hypervisor code sequence to get chip version via HV_DIAG_HEXEC.
* Returns E_HOK in %o0 and %hver register value in %o1.
*/
.align 16
#endif /* lint */
#endif NIAGARA_ERRATUM_39