4496171313bed39e96f21bc2f9faf2868e267ae3girish/*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * CDDL HEADER START
4496171313bed39e96f21bc2f9faf2868e267ae3girish *
4496171313bed39e96f21bc2f9faf2868e267ae3girish * The contents of this file are subject to the terms of the
4496171313bed39e96f21bc2f9faf2868e267ae3girish * Common Development and Distribution License (the "License").
4496171313bed39e96f21bc2f9faf2868e267ae3girish * You may not use this file except in compliance with the License.
4496171313bed39e96f21bc2f9faf2868e267ae3girish *
4496171313bed39e96f21bc2f9faf2868e267ae3girish * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
4496171313bed39e96f21bc2f9faf2868e267ae3girish * or http://www.opensolaris.org/os/licensing.
4496171313bed39e96f21bc2f9faf2868e267ae3girish * See the License for the specific language governing permissions
4496171313bed39e96f21bc2f9faf2868e267ae3girish * and limitations under the License.
4496171313bed39e96f21bc2f9faf2868e267ae3girish *
4496171313bed39e96f21bc2f9faf2868e267ae3girish * When distributing Covered Code, include this CDDL HEADER in each
4496171313bed39e96f21bc2f9faf2868e267ae3girish * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
4496171313bed39e96f21bc2f9faf2868e267ae3girish * If applicable, add the following below this CDDL HEADER, with the
4496171313bed39e96f21bc2f9faf2868e267ae3girish * fields enclosed by brackets "[]" replaced with your own identifying
4496171313bed39e96f21bc2f9faf2868e267ae3girish * information: Portions Copyright [yyyy] [name of copyright owner]
4496171313bed39e96f21bc2f9faf2868e267ae3girish *
4496171313bed39e96f21bc2f9faf2868e267ae3girish * CDDL HEADER END
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
4496171313bed39e96f21bc2f9faf2868e267ae3girish * Use is subject to license terms.
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish#if !defined(lint)
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include "assym.h"
4496171313bed39e96f21bc2f9faf2868e267ae3girish#endif
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * Niagara2 processor specific assembly routines
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/asm_linkage.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/machasi.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/machparam.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/hypervisor_api.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/niagara2regs.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/machasi.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <sys/niagaraasi.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish#include <vm/hat_sfmmu.h>
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish#if defined(lint)
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*ARGSUSED*/
4496171313bed39e96f21bc2f9faf2868e267ae3girishuint64_t
4496171313bed39e96f21bc2f9faf2868e267ae3girishhv_niagara_getperf(uint64_t perfreg, uint64_t *datap)
4496171313bed39e96f21bc2f9faf2868e267ae3girish{ return (0); }
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*ARGSUSED*/
4496171313bed39e96f21bc2f9faf2868e267ae3girishuint64_t
4496171313bed39e96f21bc2f9faf2868e267ae3girishhv_niagara_setperf(uint64_t perfreg, uint64_t data)
4496171313bed39e96f21bc2f9faf2868e267ae3girish{ return (0); }
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish#else /* lint */
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish /*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * hv_niagara_getperf(uint64_t perfreg, uint64_t *datap)
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish ENTRY(hv_niagara_getperf)
4496171313bed39e96f21bc2f9faf2868e267ae3girish mov %o1, %o4 ! save datap
59ac0c1669407488b67ae9e273667a340dccc611davemq#if defined(NIAGARA2_IMPL)
4496171313bed39e96f21bc2f9faf2868e267ae3girish mov HV_NIAGARA2_GETPERF, %o5
59ac0c1669407488b67ae9e273667a340dccc611davemq#elif defined(VFALLS_IMPL)
59ac0c1669407488b67ae9e273667a340dccc611davemq mov HV_VFALLS_GETPERF, %o5
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu#elif defined(KT_IMPL)
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu mov HV_KT_GETPERF, %o5
59ac0c1669407488b67ae9e273667a340dccc611davemq#endif
4496171313bed39e96f21bc2f9faf2868e267ae3girish ta FAST_TRAP
4496171313bed39e96f21bc2f9faf2868e267ae3girish brz,a %o0, 1f
4496171313bed39e96f21bc2f9faf2868e267ae3girish stx %o1, [%o4]
4496171313bed39e96f21bc2f9faf2868e267ae3girish1:
4496171313bed39e96f21bc2f9faf2868e267ae3girish retl
4496171313bed39e96f21bc2f9faf2868e267ae3girish nop
4496171313bed39e96f21bc2f9faf2868e267ae3girish SET_SIZE(hv_niagara_getperf)
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish /*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * hv_niagara_setperf(uint64_t perfreg, uint64_t data)
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish ENTRY(hv_niagara_setperf)
59ac0c1669407488b67ae9e273667a340dccc611davemq#if defined(NIAGARA2_IMPL)
4496171313bed39e96f21bc2f9faf2868e267ae3girish mov HV_NIAGARA2_SETPERF, %o5
59ac0c1669407488b67ae9e273667a340dccc611davemq#elif defined(VFALLS_IMPL)
59ac0c1669407488b67ae9e273667a340dccc611davemq mov HV_VFALLS_SETPERF, %o5
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu#elif defined(KT_IMPL)
4df55fde49134f9735f84011f23a767c75e393c7Janie Lu mov HV_KT_SETPERF, %o5
59ac0c1669407488b67ae9e273667a340dccc611davemq#endif
4496171313bed39e96f21bc2f9faf2868e267ae3girish ta FAST_TRAP
4496171313bed39e96f21bc2f9faf2868e267ae3girish retl
4496171313bed39e96f21bc2f9faf2868e267ae3girish nop
4496171313bed39e96f21bc2f9faf2868e267ae3girish SET_SIZE(hv_niagara_setperf)
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish#endif /* !lint */
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish#if defined (lint)
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * Invalidate all of the entries within the TSB, by setting the inv bit
4496171313bed39e96f21bc2f9faf2868e267ae3girish * in the tte_tag field of each tsbe.
4496171313bed39e96f21bc2f9faf2868e267ae3girish *
4496171313bed39e96f21bc2f9faf2868e267ae3girish * We take advantage of the fact that the TSBs are page aligned and a
4496171313bed39e96f21bc2f9faf2868e267ae3girish * multiple of PAGESIZE to use ASI_BLK_INIT_xxx ASI.
4496171313bed39e96f21bc2f9faf2868e267ae3girish *
4496171313bed39e96f21bc2f9faf2868e267ae3girish * See TSB_LOCK_ENTRY and the miss handlers for how this works in practice
4496171313bed39e96f21bc2f9faf2868e267ae3girish * (in short, we set all bits in the upper word of the tag, and we give the
4496171313bed39e96f21bc2f9faf2868e267ae3girish * invalid bit precedence over other tag bits in both places).
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish/*ARGSUSED*/
4496171313bed39e96f21bc2f9faf2868e267ae3girishvoid
4496171313bed39e96f21bc2f9faf2868e267ae3girishcpu_inv_tsb(caddr_t tsb_base, uint_t tsb_bytes)
4496171313bed39e96f21bc2f9faf2868e267ae3girish{}
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish#else /* lint */
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish ENTRY(cpu_inv_tsb)
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish /*
4496171313bed39e96f21bc2f9faf2868e267ae3girish * The following code assumes that the tsb_base (%o0) is 256 bytes
4496171313bed39e96f21bc2f9faf2868e267ae3girish * aligned and the tsb_bytes count is multiple of 256 bytes.
4496171313bed39e96f21bc2f9faf2868e267ae3girish */
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish wr %g0, ASI_BLK_INIT_ST_QUAD_LDD_P, %asi
4496171313bed39e96f21bc2f9faf2868e267ae3girish set TSBTAG_INVALID, %o2
4496171313bed39e96f21bc2f9faf2868e267ae3girish sllx %o2, 32, %o2 ! INV bit in upper 32 bits of the tag
4496171313bed39e96f21bc2f9faf2868e267ae3girish1:
4496171313bed39e96f21bc2f9faf2868e267ae3girish stxa %o2, [%o0+0x0]%asi
4496171313bed39e96f21bc2f9faf2868e267ae3girish stxa %o2, [%o0+0x40]%asi
4496171313bed39e96f21bc2f9faf2868e267ae3girish stxa %o2, [%o0+0x80]%asi
4496171313bed39e96f21bc2f9faf2868e267ae3girish stxa %o2, [%o0+0xc0]%asi
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish stxa %o2, [%o0+0x10]%asi
4496171313bed39e96f21bc2f9faf2868e267ae3girish stxa %o2, [%o0+0x20]%asi
4496171313bed39e96f21bc2f9faf2868e267ae3girish stxa %o2, [%o0+0x30]%asi
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish stxa %o2, [%o0+0x50]%asi
4496171313bed39e96f21bc2f9faf2868e267ae3girish stxa %o2, [%o0+0x60]%asi
4496171313bed39e96f21bc2f9faf2868e267ae3girish stxa %o2, [%o0+0x70]%asi
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish stxa %o2, [%o0+0x90]%asi
4496171313bed39e96f21bc2f9faf2868e267ae3girish stxa %o2, [%o0+0xa0]%asi
4496171313bed39e96f21bc2f9faf2868e267ae3girish stxa %o2, [%o0+0xb0]%asi
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish stxa %o2, [%o0+0xd0]%asi
4496171313bed39e96f21bc2f9faf2868e267ae3girish stxa %o2, [%o0+0xe0]%asi
4496171313bed39e96f21bc2f9faf2868e267ae3girish stxa %o2, [%o0+0xf0]%asi
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish subcc %o1, 0x100, %o1
4496171313bed39e96f21bc2f9faf2868e267ae3girish bgu,pt %ncc, 1b
4496171313bed39e96f21bc2f9faf2868e267ae3girish add %o0, 0x100, %o0
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish membar #Sync
4496171313bed39e96f21bc2f9faf2868e267ae3girish retl
4496171313bed39e96f21bc2f9faf2868e267ae3girish nop
4496171313bed39e96f21bc2f9faf2868e267ae3girish
4496171313bed39e96f21bc2f9faf2868e267ae3girish SET_SIZE(cpu_inv_tsb)
4496171313bed39e96f21bc2f9faf2868e267ae3girish#endif /* lint */
895ca178e38ac3583d0c0d8317d51dc5f388df6eae
895ca178e38ac3583d0c0d8317d51dc5f388df6eae#if defined (lint)
895ca178e38ac3583d0c0d8317d51dc5f388df6eae/*
895ca178e38ac3583d0c0d8317d51dc5f388df6eae * This is CPU specific delay routine for atomic backoff. It is used in case
895ca178e38ac3583d0c0d8317d51dc5f388df6eae * of Niagara2 and VF CPUs. The rd instruction uses less resources than casx
895ca178e38ac3583d0c0d8317d51dc5f388df6eae * on these CPUs.
895ca178e38ac3583d0c0d8317d51dc5f388df6eae */
895ca178e38ac3583d0c0d8317d51dc5f388df6eaevoid
895ca178e38ac3583d0c0d8317d51dc5f388df6eaecpu_atomic_delay(void)
895ca178e38ac3583d0c0d8317d51dc5f388df6eae{}
895ca178e38ac3583d0c0d8317d51dc5f388df6eae#else /* lint */
895ca178e38ac3583d0c0d8317d51dc5f388df6eae ENTRY(cpu_atomic_delay)
895ca178e38ac3583d0c0d8317d51dc5f388df6eae rd %ccr, %g0
895ca178e38ac3583d0c0d8317d51dc5f388df6eae rd %ccr, %g0
895ca178e38ac3583d0c0d8317d51dc5f388df6eae retl
895ca178e38ac3583d0c0d8317d51dc5f388df6eae rd %ccr, %g0
895ca178e38ac3583d0c0d8317d51dc5f388df6eae SET_SIZE(cpu_atomic_delay)
895ca178e38ac3583d0c0d8317d51dc5f388df6eae#endif /* lint */