us3_module.h revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_US3_MODULE_H
#define _SYS_US3_MODULE_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef _KERNEL
/*
* Macros to access the "cheetah cpu private" data structure.
*/
/* JP J_REQ errors */
/* JP AID errors */
#if defined(SERRANO)
/* SERRANO AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */
#else /* SERRANO */
/* JP AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */
#endif /* SERRANO */
#if defined(SERRANO)
/*
* SERRANO AFSR bits from {Instruction,Data}_access_error traps
* (Traps 0xa, 0x32)
*/
#else /* SERRANO */
/* JP AFSR bits from {Instruction,Data}_access_error traps (Traps 0xa, 0x32) */
#endif /* SERRANO */
#if defined(SERRANO)
/* SERRANO AFSR bits from Fast_ECC_error trap (Trap 0x70) */
#else /* SERRANO */
/* JP AFSR bits from Fast_ECC_error trap (Trap 0x70) */
#endif /* SERRANO */
#if defined(SERRANO)
/* SERRANO AFSR bits from Fatal errors (processor asserts ERROR pin) */
#else /* SERRANO */
/* JP AFSR bits from Fatal errors (processor asserts ERROR pin) */
#endif /* SERRANO */
/* JP AFSR all valid error status bits */
#if defined(SERRANO)
/* SERRANO AFSR all ME status bits */
#else /* SERRANO */
/* JP AFSR all ME status bits */
#endif /* SERRANO */
#if defined(SERRANO)
/* SERRANO AFSR bits due to an Ecache error */
#else /* SERRANO */
/* JP AFSR bits due to an Ecache error */
#endif /* SERRANO */
/* JP AFSR bits due to a Memory error */
/* JP AFSR bits due to parity errors and have a valid BSYND */
/* JP AFSR bits with a valid ESYND field */
/* JP AFSR error bits for AFT Level 1 messages (uncorrected + TO + BERR) */
#elif defined(CHEETAH_PLUS)
/* Ch+ AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */
/* Ch+ AFSR bits from {Instruction,Data}_access_error traps (Traps 0xa, 0x32) */
/* Ch+ AFSR bits from Fast_ECC_error trap (Trap 0x70) */
/* Ch+ AFSR bits from Fatal errors (processor asserts ERROR pin) */
/* Ch+ AFSR all valid error status bits */
/* Ch+ AFSR all errors that set ME bit, in both AFSR and AFSR_EXT */
/* Ch+ AFSR bits due to an Ecache error */
/* Ch+ AFSR bits due to a Memory error */
/* Ch+ AFSR bits due to an Mtag error and have a valid MSYND */
/* Ch+ AFSR bits with a valid ESYND field */
/* Ch+ AFSR error bits for AFT Level 1 messages (uncorrected + TO + BERR) */
#else /* CHEETAH_PLUS */
/* AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */
/* AFSR bits from {Instruction,Data}_access_error traps (Traps 0xa, 0x32) */
/* AFSR bits from Fast_ECC_error trap (Trap 0x70) */
/* AFSR bits from Fatal errors (processor asserts ERROR pin) */
/* AFSR all valid error status bits */
/* AFSR all ME status bits */
/* AFSR bits due to an Ecache error */
/* AFSR bits due to a Memory error */
/* AFSR bits due to an Mtag error and have a valid MSYND */
/* AFSR bits with a valid ESYND field */
/* AFSR error bits for AFT Level 1 messages (uncorrected + TO + BERR) */
#endif /* CHEETAH_PLUS */
/* AFSR all valid bits (except for ETW) */
#else /* JALAPENO || SERRANO */
/* AFSR all valid bits */
#endif /* JALAPENO || SERRANO */
/*
* Panther AFSR_EXT bits from Disrupting (Corrected) ECC error Trap
* (Trap 0x63)
*/
/*
* Panther AFSR_EXT bits from {Instruction,Data}_access_error traps
* (Traps 0xa, 0x32)
*/
#define C_AFSR_EXT_ASYNC_ERRS (C_AFSR_L3_EDU)
/* Panther AFSR_EXT bits from Fast_ECC_error trap (Trap 0x70) */
/* Panther AFSR_EXT bits from Fatal errors (processor asserts ERROR pin) */
/* Panther AFSR_EXT all valid error status bits */
#define C_AFSR_EXT_ALL_ERRS (C_AFSR_EXT_FATAL_ERRS | \
/* Panther AFSR_EXT bits due to L3 cache errors */
/* Panther AFSR_EXT bits with a valid ESYND field */
/* PANTHER AFSR_EXT error bits for AFT Level 1 messages (uncorrected) */
/*
* AFSR / AFSR_EXT bits for which we need to panic the system.
*/
C_AFSR_EXT_FATAL_ERRS)) != 0)
/*
* For the Fast ECC TL1 handler, we are limited in how many registers
* we can use, so we need to store the AFSR_EXT bits within the AFSR
* register using some of the AFSR reserved bits.
*/
#define AFSR_EXT_IN_AFSR_SHIFT 20
/*
* Defines for the flag field in the CPU logout structure. See the
* definition of ch_cpu_logout_t for further description.
*/
#define CLO_FLAGS_TT_MASK 0xff000
#define CLO_FLAGS_TT_SHIFT 12
#define CLO_FLAGS_TL_MASK 0xf00
#define CLO_FLAGS_TL_SHIFT 8
#define C_M_SYND_SHIFT 16
/*
* Bits of Cheetah Asynchronous Fault Address Register
*/
/*
* Defines for the different types of dcache_flush
* it is stored in dflush_type
*/
/* each line for a match */
/* each line for a match */
/*
* D-Cache Tag Data Register
*
* +----------+--------+----------+
* | Reserved | DC_Tag | DC_Valid |
* +----------+--------+----------+
* 63 31 30 1 0
*
*/
#define CHEETAH_DC_VBIT_SHIFT 1
#define CHEETAH_DC_VBIT_MASK 0x1
/*
* Define for max size of "reason" string in panic flows. Since this is on
* the stack, we want to keep it as small as is reasonable.
*/
#define MAX_REASON_STRING 40
/*
* These error types are specific to Cheetah and are used internally for the
* Cheetah fault structure flt_type field.
*/
/*
* These next six error types (17-22) are only used in Jalapeno code
*/
/*
* These next four error types (23-26) are only used in Panther code
*/
/*
* Sets trap table entry ttentry by overwriting eight instructions from ttlabel
*/
/*
* Return values for implementation specific error logging in the routine
* cpu_impl_async_log_err()
*/
#define CH_ASYNC_LOG_DONE 0 /* finished logging the error */
#ifndef _ASM
/*
* Define Cheetah family (UltraSPARC-III) specific asynchronous error structure
*/
typedef struct cheetah_async_flt {
int flt_data_incomplete; /* Diagnostic data is incomplete */
int flt_trapped_ce; /* CEEN fault caught by trap handler */
#if defined(CPU_IMP_L1_CACHE_PARITY)
#endif /* CPU_IMP_L1_CACHE_PARITY */
/*
* Error type table struct.
*/
typedef struct ecc_type_to_info {
char *ec_reason; /* Short error description */
int ec_flt_type; /* Used by cpu_async_log_err */
char *ec_desc; /* Long error description */
char *ec_err_class; /* FM ereport class */
typedef struct bus_config_eclk {
#endif /* _ASM */
#endif /* _KERNEL */
#ifndef _ASM
/*
* Since all the US3_* files share a bunch of routines between each other
* we will put all the "extern" definitions in this header file so that we
* don't have to repeat it all in every file.
*/
/*
* functions that are defined in the US3 cpu module:
* -------------------------------------------------
*/
extern uint64_t get_safari_config(void);
extern void shipit(int, int);
extern void get_cpu_error_state(ch_cpu_errors_t *);
extern void set_cpu_error_state(ch_cpu_errors_t *);
extern void cpu_error_ecache_flush(ch_async_flt_t *);
extern void cpu_async_log_ic_parity_err(ch_async_flt_t *);
extern void cpu_async_log_dc_parity_err(ch_async_flt_t *);
extern uint64_t get_ecache_ctrl(void);
extern uint64_t get_jbus_config(void);
extern uint64_t get_mcu_ctl_reg1(void);
extern void cpu_init_trap(void);
extern int cpu_ecache_nway(void);
extern int cpu_scrub_cpu_setup(cpu_setup_t, int, void *);
#endif /* JALAPENO || SERRANO */
/*
* Address of the level 15 interrupt handler preamble, used to log Fast ECC
* at TL>0 errors, which will be moved to the trap table address above.
*/
extern void ch_pil15_interrupt_instr();
#ifdef CHEETAHPLUS_ERRATUM_25
extern int mondo_recover(uint16_t, int);
#endif /* CHEETAHPLUS_ERRATUM_25 */
/*
* Adddresses of the Fast ECC Error trap handler preambles which will be
* moved to the appropriate trap table addresses.
*/
extern void fecc_err_instr(void);
extern void fecc_err_tl1_instr(void);
extern void fecc_err_tl1_cont_instr(void);
#if defined(CHEETAH_PLUS)
#endif /* CHEETAH_PLUS */
extern void flush_dcache(void);
extern void flush_icache(void);
extern void flush_pcache(void);
extern void flush_ipb(void);
extern void icache_inval_all(void);
extern void dcache_inval_line(int index);
#if defined(CPU_IMP_L1_CACHE_PARITY)
#endif /* CPU_IMP_L1_CACHE_PARITY */
extern int cpu_impl_async_log_err(void *, errorq_elem_t *);
#if defined(CPU_IMP_L1_CACHE_PARITY)
#endif /* CPU_IMP_L1_CACHE_PARITY */
#if defined(CHEETAH_PLUS)
#endif
/*
* variables and structures that are defined in the US3 cpu module:
* ----------------------------------------------------------------
*/
extern bus_config_eclk_t bus_config_eclk[];
extern ecc_type_to_info_t ecc_type_to_info[];
extern uint64_t ch_err_tl1_paddrs[];
extern uchar_t ch_err_tl1_pending[];
#ifdef CHEETAHPLUS_ERRATUM_25
/*
* Tunable defined in us3_common.c
*/
extern int cheetah_sendmondo_recover;
#endif /* CHEETAHPLUS_ERRATUM_25 */
/*
* The following allows for a one time calculation of the number of dcache
* lines vs. calculating the number every time through the scrub routine.
*/
int dcache_nlines; /* max number of D$ lines */
extern uint64_t afar_overwrite[];
extern uint64_t esynd_overwrite[];
extern uint64_t msynd_overwrite[];
extern uint64_t jreq_overwrite[];
#if defined(SERRANO)
extern uint64_t afar2_overwrite[];
#endif /* SERRANO */
#endif /* JALAPENO || SERRANO */
/*
* variables and structures that are defined outside the US3 cpu module:
* ---------------------------------------------------------------------
*/
extern uint64_t xc_tick_limit;
extern uint64_t xc_tick_jump_limit;
extern struct kmem_cache *ch_private_cache;
#if defined(CPU_IMP_L1_CACHE_PARITY)
/*
* Addresses of the Dcache and Icache parity error trap table entries.
* If L1 cache parity protection is implemented, need to replace Dcache and
* Icache parity error handlers.
*/
extern void *tt0_dperr;
extern void *tt1_dperr;
extern void *tt1_swtrap1;
extern void *tt0_iperr;
extern void *tt1_iperr;
extern void *tt1_swtrap2;
/*
* Addresses of the Dcache and Icache parity error trap preambles, which will
* be moved to the appropriate trap table addresses.
*/
extern void dcache_parity_instr();
extern void dcache_parity_tl1_instr();
extern void dcache_parity_tl1_cont_instr();
extern void icache_parity_instr();
extern void icache_parity_tl1_instr();
extern void icache_parity_tl1_cont_instr();
#endif /* CPU_IMP_L1_CACHE_PARITY */
/*
* Addresses of the Fast ECC error trap table entries.
*/
extern void *tt0_fecc;
extern void *tt1_fecc;
extern void *tt1_swtrap0;
/*
* Address of trap table level 15 interrupt handler in the trap table.
*/
extern void *tt_pil15;
/*
* D$ and I$ global parameters.
*/
extern int dcache_size;
extern int dcache_linesize;
extern int icache_size;
extern int icache_linesize;
/*
* Set of all offline cpus
*/
extern cpuset_t cpu_offline_set;
#endif /* _ASM */
#ifdef __cplusplus
}
#endif
#endif /* _SYS_US3_MODULE_H */