pci_iommu.h revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_PCI_IOMMU_H
#define _SYS_PCI_IOMMU_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
typedef uint64_t dvma_addr_t;
typedef uint64_t dma_bypass_addr_t;
typedef uint64_t dma_peer_addr_t;
typedef uint16_t dvma_context_t;
/*
* The following typedef's represents the types for DMA transactions
*/
/*
* The following macros define the iommu page size and related operations.
*/
#define IOMMU_PAGE_SHIFT 13
#define IOMMU_BTOP(x) ((x) >> IOMMU_PAGE_SHIFT)
/*
* control register decoding
*/
/* tsb size: 0=1k 1=2k 2=4k 3=8k 4=16k 5=32k 6=64k 7=128k */
#define IOMMU_DARWIN_BOGUS_TSBSIZE 7
/*
* boiler plate for tte (everything except the pfn)
*/
/*
* The following macros define the address ranges supported for DVMA
* and iommu bypass transfers.
*/
#define COMMON_IOMMU_BYPASS_BASE 0xFFFC000000000000ull
#define COMMON_IOMMU_BYPASS_END 0xFFFC00FFFFFFFFFFull
/*
* For iommu bypass addresses, bit 43 specifies cacheability.
*/
#define COMMON_IOMMU_BYPASS_NONCACHE 0x0000080000000000ull
/*
* Generic iommu definitions and types:
*/
#define IOMMU_TLB_ENTRIES 16
/*
* The following macros are for loading and unloading iotte
* entries.
*/
#define COMMON_IOMMU_TTE_SIZE 8
#define COMMON_IOMMU_TTE_V 0x8000000000000000ull
#define COMMON_IOMMU_TTE_S 0x1000000000000000ull
#define COMMON_IOMMU_TTE_C 0x0000000000000010ull
#define COMMON_IOMMU_TTE_W 0x0000000000000002ull
#define COMMON_IOMMU_INVALID_TTE 0x0000000000000000ull
/*
* Tomatillo's micro TLB bug. errata #82
*/
typedef struct dvma_unbind_req {
/*
* iommu block soft state structure:
*
* Each pci node may share an iommu block structure with its peer
* node of have its own private iommu block structure.
*/
struct iommu {
int iommu_inst; /* ddi_get_instance(iommu_pci_p->pci_dip) */
volatile uint64_t *iommu_ctrl_reg;
volatile uint64_t *iommu_tsb_base_addr_reg;
volatile uint64_t *iommu_flush_page_reg;
/*
* virtual and physical addresses and size of the iommu tsb:
*/
/*
* address ranges of dvma space:
*/
/*
* address ranges of dma bypass space:
*/
/*
* virtual memory map and callback id for dvma space:
*/
/*
* fields for fast dvma interfaces:
*/
/*
* dvma fast track page cache byte map
*/
/*
* dvma context bitmap
*/
/*
* dvma debug
*/
struct dvma_rec *dvma_alloc_rec;
struct dvma_rec *dvma_free_rec;
struct dvma_rec *dvma_active_list;
/*
* tomatillo's micro TLB bug. errata #82
*/
};
typedef struct pci_dvma_range_prop {
#define IOMMU_CONTEXT_BITS 12
#define IOMMU_TTE_CTX_SHIFT 47
#define IOMMU_TTE2CTX(tte) \
/* dvma debug */
#define DVMA_DBG_ON(iommu_p) \
#define DVMA_DBG_OFF(iommu_p) \
ddi_dma_impl_t *mp);
ddi_dma_impl_t *mp);
/* dvma routines */
/* iommu initialization routines */
#ifdef __cplusplus
}
#endif
#endif /* _SYS_PCI_IOMMU_H */