pci_cb.h revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2004 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_PCI_CB_H
#define _SYS_PCI_CB_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
enum cb_nintr_index {
CBNINTR_PBM = 0, /* all not shared */
CBNINTR_PBM66 = 0, /* all not shared */
CBNINTR_PBM33 = 0, /* all not shared */
CBNINTR_MAX /* count coding */
};
/*
* control block soft state structure:
*
* Each pci node contains shares a control block structure with its peer
* node. The control block node contains csr and id registers for chip
* and acts as a "catch all" for other functionality that does not cleanly
* fall into other functional blocks. This block is also used to handle
* software workarounds for known hardware bugs in different chip revs.
*/
struct cb {
/* bank, 4th "reg" entry */
#ifdef _STARFIRE
#endif
};
extern void cb_intr_dist(void *arg);
#ifdef __cplusplus
}
#endif
#endif /* _SYS_PCI_CB_H */