db21554_config.h revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 1999 by Sun Microsystems, Inc.
* All rights reserved.
*/
#ifndef _SYS_DB21554_CONFIG_H
#define _SYS_DB21554_CONFIG_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* Some register definitions for configuration header.
*/
#define DB_PCONF_MEM_CSR PCI_CONF_BASE0
#define DB_PCONF_IO_CSR PCI_CONF_BASE1
#define DB_PCONF_DS_IO_MEM1 PCI_CONF_BASE2
#define DB_PCONF_DS_MEM2 PCI_CONF_BASE3
#define DB_PCONF_DS_MEM3 PCI_CONF_BASE4
#define DB_PCONF_DS_UMEM3 PCI_CONF_BASE5
#define DB_PCONF_EXP_ROM PCI_CONF_ROM
#define DB_SCONF_MEM_CSR PCI_CONF_BASE0
#define DB_SCONF_IO_CSR PCI_CONF_BASE1
#define DB_SCONF_US_IO_MEM0 PCI_CONF_BASE2
#define DB_SCONF_US_MEM1 PCI_CONF_BASE3
#define DB_SCONF_US_MEM2 PCI_CONF_BASE4
#define DB_IO_BIT 0x00000001
#define DB_VENDOR_ID 0x1011
#define DB_DEVICE_ID 0x46
#define DB_INVAL_VEND 0xffff
/* configuration own register bits : Register offset 0x90-91 */
/* the following is a 8-bit register version definition. */
#define DS8_CONF_OWN 0x01
#define US8_CONF_OWN 0x01
/* configuration control status register bits: Register offset 0x92-93 */
/* chip control 0 register bits: Register Offset 0xcc-cd */
/* chip control 1 register bits: Register Offset 0xce-cf */
#define P_PW_THRESHOLD 0x0001
#define S_PW_THRESHOLD 0x0002
#define P_DREAD_THRESHOLD_MASK 0x000C
#define S_DREAD_THRESHOLD_MASK 0x0030
#define DREAD_THRESHOLD_VALBITS 0x3
#define PAGESIZE_256 0x0100
#define PAGESIZE_512 0x0200
#define PAGESIZE_1K 0x0300
#define PAGESIZE_2K 0x0400
#define PAGESIZE_4K 0x0500
#define PAGESIZE_8K 0x0600
#define PAGESIZE_16K 0x0700
#define PAGESIZE_32K 0x0800
#define PAGESIZE_64K 0x0900
#define PAGESIZE_128K 0x0A00
#define PAGESIZE_256K 0x0B00
#define PAGESIZE_512K 0x0C00
#define PAGESIZE_1M 0x0D00
#define PAGESIZE_2M 0x0E00
#define PAGESIZE_4M 0x0F00
/* chip reset control register bits : Register Offset 0xd8-db */
/* chip status register bits : Register Offset 0xd0-d1 */
#define DS_POST_WRDATA_DISCA 0x0008
#define US_POST_WRDATA_DISCA 0x0800
/* form a type 0 configuration address */
((reg) & 0xfc))
/* form a type 1 configuration address */
#define DB_ENABLE_PCI_CONF_CYCLE_TYPE0 0
#define DB_ENABLE_PCI_CONF_CYCLE_TYPE1 1
/*
* add local address offsets and get the right config address double
* word aligned type 0 format addresses.
*/
#define DB_PCI_CONF_CYCLE_TYPE0_ADDR(conf_addr) \
/*
* add local address offsets and get the right config address double
* word aligned type 1 format addresses.
*/
#define DB_PCI_CONF_CYCLE_TYPE1_ADDR(conf_addr) \
#define PCI_HDR_SIZE 64
typedef struct db_pci_header {
typedef struct db_conf_regs {
#ifdef __cplusplus
}
#endif
#endif /* _SYS_DB21554_CONFIG_H */