d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * CDDL HEADER START
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d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * Common Development and Distribution License, Version 1.0 only
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * (the "License"). You may not use this file except in compliance
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * with the License.
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * See the License for the specific language governing permissions
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * and limitations under the License.
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * When distributing Covered Code, include this CDDL HEADER in each
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * If applicable, add the following below this CDDL HEADER, with the
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d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * CDDL HEADER END
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * Copyright 2005 Sun Microsystems, Inc. All rights reserved.
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * Use is subject to license terms.
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro#pragma ident "%Z%%M% %I% %E% SMI"
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloroextern "C" {
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * ADM1026 has 4 GPIO Config registers used to set Polarity and Direction.
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * To config a particular GPIO, the low 16 bits of the reg_mask member
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * of the i2c_gpio_t struct is used as a logical mask to indicate which
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * GPIO pin(s) to access and the reg_val member is used to set/clear those
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * GPIO pins' P or D bit(s).
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * GPIO# 3 2 1 0
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * +--+--+--+--+
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * |PD|PD|PD|PD| <-- ADM1026_GPIO_CFG1
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * +--+--+--+--+ Logical Mask: 0x000f
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * GPIO# 7 6 5 4
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * +--+--+--+--+
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * |PD|PD|PD|PD| <-- ADM1026_GPIO_CFG2
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * +--+--+--+--+ Logical Mask: 0x00f0
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * GPIO# 11 10 9 8
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * +--+--+--+--+
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * |PD|PD|PD|PD| <-- ADM1026_GPIO_CFG3
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * +--+--+--+--+ Logical Mask: 0x0f00
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * GPIO# 15 14 13 12
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * +--+--+--+--+
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * |PD|PD|PD|PD| <-- ADM1026_GPIO_CFG4
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * +--+--+--+--+ Logical Mask: 0xf000
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro#define ADM1026_GPIO_CFG1 0x08 /* Config GPIO 03-00 in/out + hi/lo */
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro#define ADM1026_GPIO_CFG2 0x09 /* Config GPIO 07-04 in/out + hi/lo */
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro#define ADM1026_GPIO_CFG3 0x0a /* Config GPIO 11-08 in/out + hi/lo */
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro#define ADM1026_GPIO_CFG4 0x0b /* Config GPIO 15-12 in/out + hi/lo */
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * ADM1026 has 2 GPIO Output registers to set GPIO pins.
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * To set a particular GPIO pin, the low 16 bits of the reg_mask member
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * of the i2c_gpio_t struct is used as a 1:1 mask of the 16 GPIO pin(s)
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * to access and the reg_val member is used to set/clear the GPIO pin(s).
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * GPIO# 76 54 32 10
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * +--+--+--+--+
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * |xx|xx|xx|xx| <-- ADM1026_STS_REG5
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * +--+--+--+--+ Logical Mask: 0x00ff
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * GPIO# 11 11 11 98
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * +--+--+--+--+
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * |xx|xx|xx|xx| <-- ADM1026_STS_REG6
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro * +--+--+--+--+ Logical Mask: 0xff00
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro#define BITSPERCFG 2 /* Polarity + Dir bits per GPIO cfg */
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro#define POLARITY_BIT 2 /* Polarity bit = hi bit GPIO cfg */
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro#define D1CMN_ERR(ARGS) { if (adm1026_dbg & 0x1) cmn_err ARGS; }
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro#define D2CMN_ERR(ARGS) { if (adm1026_dbg & 0x2) cmn_err ARGS; }
d58fda4376e4bf67072ce2e69f6f47036f9dbb68jbeloro#endif /* _ADM1026_IMPL_H */