29949e866e40b95795203f3ee46f44a197c946e4stevel * CDDL HEADER START
29949e866e40b95795203f3ee46f44a197c946e4stevel * The contents of this file are subject to the terms of the
29949e866e40b95795203f3ee46f44a197c946e4stevel * Common Development and Distribution License (the "License").
29949e866e40b95795203f3ee46f44a197c946e4stevel * You may not use this file except in compliance with the License.
29949e866e40b95795203f3ee46f44a197c946e4stevel * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
29949e866e40b95795203f3ee46f44a197c946e4stevel * See the License for the specific language governing permissions
29949e866e40b95795203f3ee46f44a197c946e4stevel * and limitations under the License.
29949e866e40b95795203f3ee46f44a197c946e4stevel * When distributing Covered Code, include this CDDL HEADER in each
29949e866e40b95795203f3ee46f44a197c946e4stevel * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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29949e866e40b95795203f3ee46f44a197c946e4stevel * information: Portions Copyright [yyyy] [name of copyright owner]
29949e866e40b95795203f3ee46f44a197c946e4stevel * CDDL HEADER END
29949e866e40b95795203f3ee46f44a197c946e4stevel * Copyright 1998 Sun Microsystems, Inc. All rights reserved.
29949e866e40b95795203f3ee46f44a197c946e4stevel * Use is subject to license terms.
29949e866e40b95795203f3ee46f44a197c946e4stevel#pragma ident "%Z%%M% %I% %E% SMI"
29949e866e40b95795203f3ee46f44a197c946e4stevelextern "C" {
29949e866e40b95795203f3ee46f44a197c946e4stevel#define BLINK_TIMEOUT_USEC 500 * (MICROSEC / MILLISEC)
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_TAZBLKBRDCPU_STRING "SUNW,UltraSPARC-II"
29949e866e40b95795203f3ee46f44a197c946e4stevel * I2c Sensor Types
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8574 0x02 /* PS, FAN, LED, Fail and Control */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define TDA8444T 0x03 /* Fan Speed Control, 8 bit D/A */
29949e866e40b95795203f3ee46f44a197c946e4stevel * Max number of a particular
29949e866e40b95795203f3ee46f44a197c946e4stevel * device on 1 bus.
29949e866e40b95795203f3ee46f44a197c946e4stevel * Defines for the PCF8583 Clock Calendar Chip
29949e866e40b95795203f3ee46f44a197c946e4stevel * We use this chip as a watchdog timer for the fans
29949e866e40b95795203f3ee46f44a197c946e4stevel * should the kernel thread controling the fans get
29949e866e40b95795203f3ee46f44a197c946e4stevel * wedged. If it does, the alarm wil go off and
29949e866e40b95795203f3ee46f44a197c946e4stevel * set the fans to max speed.
29949e866e40b95795203f3ee46f44a197c946e4stevel * Valid addresses for this chip are A0, A2.
29949e866e40b95795203f3ee46f44a197c946e4stevel * We use the address at A0.
29949e866e40b95795203f3ee46f44a197c946e4stevel * To address this chip the format is as folows (write mode)
29949e866e40b95795203f3ee46f44a197c946e4stevel * | SLaveaddress |MEMORY LOCATION| DATA|
29949e866e40b95795203f3ee46f44a197c946e4stevel * Wgere memory location is the internal location from
29949e866e40b95795203f3ee46f44a197c946e4stevel * 0x00 - 0x0F. 0x00 is the CSR and MUST be addressed
29949e866e40b95795203f3ee46f44a197c946e4stevel * directly.
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PS_DEFAULT_VAL 17 /* corresponds to 90 C in lookup table */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CPU_AMB_RISE 20 /* cpu runs avg of 20 above amb */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PS_AMB_RISE 30 /* cpu runs avg of 30 above amb */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Keyswitch Definitions */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Disk Fault bit fields */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Front Status Panel Definitions */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_FSP_USRMASK (ENVCTRL_FSP_DISK_ERR | ENVCTRL_FSP_GEN_ERR)
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Kstat Structures and defines */
29949e866e40b95795203f3ee46f44a197c946e4stevel boolean_t curr_share_ok; /* current share imbalance */
29949e866e40b95795203f3ee46f44a197c946e4stevel * configuration registers
29949e866e40b95795203f3ee46f44a197c946e4stevel * Register S1 Looks like the following:
29949e866e40b95795203f3ee46f44a197c946e4stevel * WRITE MODE ONLY
29949e866e40b95795203f3ee46f44a197c946e4stevel * MSB -------------------------------------> LSB
29949e866e40b95795203f3ee46f44a197c946e4stevel * ----------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * | X | ESO | ES1 | ES2 | ENI | STA | STO | ACK |
29949e866e40b95795203f3ee46f44a197c946e4stevel * ----------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * Low order bits
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Hight order bits */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CSRS1_PIN 0x80 /* READ and WRITE mode Enable Serial Output */
29949e866e40b95795203f3ee46f44a197c946e4stevel * configuration registers
29949e866e40b95795203f3ee46f44a197c946e4stevel * Register S1 Looks like the following:
29949e866e40b95795203f3ee46f44a197c946e4stevel * READ MODE ONLY
29949e866e40b95795203f3ee46f44a197c946e4stevel * MSB -------------------------------------> LSB
29949e866e40b95795203f3ee46f44a197c946e4stevel * ----------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * | PIN | 0 | STS | BER | AD0/LRB | AAS | LAB | BB|
29949e866e40b95795203f3ee46f44a197c946e4stevel * ----------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CSRS1_STS 0x20 /* For Slave receiv mode stop */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define START CSRS1_PIN | CSRS1_ESO | CSRS1_STA | CSRS1_ACK
29949e866e40b95795203f3ee46f44a197c946e4stevel#define STOP CSRS1_PIN | CSRS1_ESO | CSRS1_STO | CSRS1_ACK
29949e866e40b95795203f3ee46f44a197c946e4stevel * A read wants to have an NACK on the bus to stop
29949e866e40b95795203f3ee46f44a197c946e4stevel * transmitting data from the slave. If you don't
29949e866e40b95795203f3ee46f44a197c946e4stevel * NACK the SDA line will get stuck low. After this you
29949e866e40b95795203f3ee46f44a197c946e4stevel * can send the stop with the ack.
29949e866e40b95795203f3ee46f44a197c946e4stevel * ESO = Enable Serial output
29949e866e40b95795203f3ee46f44a197c946e4stevel * ES1 and ES2 have different meanings based upon ES0.
29949e866e40b95795203f3ee46f44a197c946e4stevel * The following table explains this association.
29949e866e40b95795203f3ee46f44a197c946e4stevel * ES0 = 0 = serial interface off.
29949e866e40b95795203f3ee46f44a197c946e4stevel * ---------------------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * | A0 | ES1 | ES1 | iACK | OPERATION
29949e866e40b95795203f3ee46f44a197c946e4stevel * ---------------------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * | H | X | X | X | Read/write CSR1 (S1) Status n/a
29949e866e40b95795203f3ee46f44a197c946e4stevel * | | | | |
29949e866e40b95795203f3ee46f44a197c946e4stevel * | L | 0 | 0 | X | R/W Own Address S0'
29949e866e40b95795203f3ee46f44a197c946e4stevel * | | | | |
29949e866e40b95795203f3ee46f44a197c946e4stevel * | L | 0 | 1 | X | R/W Intr Vector S3
29949e866e40b95795203f3ee46f44a197c946e4stevel * | | | | |
29949e866e40b95795203f3ee46f44a197c946e4stevel * | L | 1 | 0 | X | R/W Clock Register S2
29949e866e40b95795203f3ee46f44a197c946e4stevel * ---------------------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * ES0 = 1 = serial interface ON.
29949e866e40b95795203f3ee46f44a197c946e4stevel * ---------------------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * | A0 | ES1 | ES1 | iACK | OPERATION
29949e866e40b95795203f3ee46f44a197c946e4stevel * ---------------------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * | H | X | X | H | Write Control Register (S1)
29949e866e40b95795203f3ee46f44a197c946e4stevel * | | | | |
29949e866e40b95795203f3ee46f44a197c946e4stevel * | H | X | X | H | Read Status Register (S1)
29949e866e40b95795203f3ee46f44a197c946e4stevel * | | | | |
29949e866e40b95795203f3ee46f44a197c946e4stevel * | L | X | 0 | H | R/W Data Register (S0)
29949e866e40b95795203f3ee46f44a197c946e4stevel * | | | | |
29949e866e40b95795203f3ee46f44a197c946e4stevel * | L | X | 1 | H | R/W Interrupt Vector (S3)
29949e866e40b95795203f3ee46f44a197c946e4stevel * | | | | |
29949e866e40b95795203f3ee46f44a197c946e4stevel * | X | 0 | X | L | R Interrupt Vector (S3) ack cycle
29949e866e40b95795203f3ee46f44a197c946e4stevel * | | | | |
29949e866e40b95795203f3ee46f44a197c946e4stevel * | X | 1 | X | L | long distance mode
29949e866e40b95795203f3ee46f44a197c946e4stevel * ---------------------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel uchar_t pad[3]; /* Padding XXX Will go away in FCS */
29949e866e40b95795203f3ee46f44a197c946e4stevel * PCF8591 Chip Used for temperature sensors
29949e866e40b95795203f3ee46f44a197c946e4stevel * Check with bob to see if singled ended inputs are true
29949e866e40b95795203f3ee46f44a197c946e4stevel * for the pcf8591 temp sensors..
29949e866e40b95795203f3ee46f44a197c946e4stevel * Addressing Register definition.
29949e866e40b95795203f3ee46f44a197c946e4stevel * A0-A2 valid range is 0-7
29949e866e40b95795203f3ee46f44a197c946e4stevel * 7 6 5 4 3 2 1 0
29949e866e40b95795203f3ee46f44a197c946e4stevel * ------------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * | 1 | 0 | 0 | 1 | A2 | A1 | A0 | R/W |
29949e866e40b95795203f3ee46f44a197c946e4stevel * ------------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_CPU_PCF8591_ADDR (PCF8591_BASE_ADDR | PCF8591_DEV7)
29949e866e40b95795203f3ee46f44a197c946e4stevel * For the LM75 thermal watchdog chip by TI
29949e866e40b95795203f3ee46f44a197c946e4stevel * CONTROL OF CHIP
29949e866e40b95795203f3ee46f44a197c946e4stevel * PCF8591 Temp sensing control register definitions
29949e866e40b95795203f3ee46f44a197c946e4stevel * 7 6 5 4 3 2 1 0
29949e866e40b95795203f3ee46f44a197c946e4stevel * ---------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * | 0 | AOE | X | X | 0 | AIF | X | X |
29949e866e40b95795203f3ee46f44a197c946e4stevel * ---------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * AOE = Analog out enable.. not used on out implementation
29949e866e40b95795203f3ee46f44a197c946e4stevel * 5 & 4 = Analog Input Programming.. see data sheet for bits..
29949e866e40b95795203f3ee46f44a197c946e4stevel * AIF = Auto increment flag
29949e866e40b95795203f3ee46f44a197c946e4stevel * bits 1 & 0 are for the Chennel number.
29949e866e40b95795203f3ee46f44a197c946e4stevel * PCF8574 Fan Fail, Power Supply Fail Detector
29949e866e40b95795203f3ee46f44a197c946e4stevel * This device is driven by interrupts. Each time it interrupts
29949e866e40b95795203f3ee46f44a197c946e4stevel * you must look at the CSR to see which ports caused the interrupt
29949e866e40b95795203f3ee46f44a197c946e4stevel * they are indicated by a 1.
29949e866e40b95795203f3ee46f44a197c946e4stevel * Address map of this chip
29949e866e40b95795203f3ee46f44a197c946e4stevel * -------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * | 0 | 1 | 1 | 1 | A2 | A1 | A0 | 0 |
29949e866e40b95795203f3ee46f44a197c946e4stevel * -------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * TDA8444T chip structure
29949e866e40b95795203f3ee46f44a197c946e4stevel * FAN Speed Control
29949e866e40b95795203f3ee46f44a197c946e4stevel/* ADDRESSING */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Control information and port addressing */
29949e866e40b95795203f3ee46f44a197c946e4stevel * This table converts an A/D value from the cpu thermistor to a
29949e866e40b95795203f3ee46f44a197c946e4stevel * temperature in degrees C. Usable range is typically 35-135.
29949e866e40b95795203f3ee46f44a197c946e4stevel * This is the lookup table used for P1 and FCS systems to convert a temperature
29949e866e40b95795203f3ee46f44a197c946e4stevel * to a fanspeed for the CPU side of the machine.
29949e866e40b95795203f3ee46f44a197c946e4stevel * This is the lookup table used for P1 and FCS systems to convert a temperature
29949e866e40b95795203f3ee46f44a197c946e4stevel * to a fanspeed for the CPU side of the machine.
29949e866e40b95795203f3ee46f44a197c946e4stevel * Get a fan speed setting based upon a temperature value
29949e866e40b95795203f3ee46f44a197c946e4stevel * from the above lookup tables.
29949e866e40b95795203f3ee46f44a197c946e4stevel * Less than zero ia a special case and greater than 70 is a
29949e866e40b95795203f3ee46f44a197c946e4stevel * the operating range of the powersupply. The system operating
29949e866e40b95795203f3ee46f44a197c946e4stevel * range is 5 - 40 Degrees C.
29949e866e40b95795203f3ee46f44a197c946e4stevel * This may need some tuning.
29949e866e40b95795203f3ee46f44a197c946e4stevel * The MAX_CPU_TEMP is set to 80 now, this table is used to set their
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_RESETTMPR (int)(_IOW('p', 76, uchar_t))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_SETMODE (int)(_IOW('p', 77, uchar_t))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_SETTEMP (int)(_IOW('p', 79, uchar_t))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_SETFAN (int)(_IOW('p', 80, struct envctrl_tda8444t_chip))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_SETWDT (int)(_IOW('p', 81, uchar_t))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_GETFAN (int)(_IOR('p', 81, struct envctrl_tda8444t_chip))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_GETTEMP (int)(_IOR('p', 82, struct envctrl_pcf8591_chip))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_GETFANFAIL (int)(_IOR('p', 83, struct envctrl_pcf8574_chip))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_SETFSP (int)(_IOW('p', 84, uchar_t))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_SETDSKLED (int)(_IOW('p', 85, struct envctrl_pcf8574_chip))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_GETDSKLED (int)(_IOR('p', 86, struct envctrl_pcf8574_chip))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_GETMODE (int)(_IOR('p', 87, uchar_t))
29949e866e40b95795203f3ee46f44a197c946e4stevel struct envctrl_ps ps_kstats[MAX_DEVS]; /* kstats for powersupplies */
29949e866e40b95795203f3ee46f44a197c946e4stevel struct envctrl_fan fan_kstats[MAX_DEVS]; /* kstats for fans */
29949e866e40b95795203f3ee46f44a197c946e4stevel struct envctrl_encl encl_kstats[MAX_DEVS]; /* kstats for enclosure */
29949e866e40b95795203f3ee46f44a197c946e4stevel int cpu_pr_location[ENVCTRL_MAX_CPUS]; /* slot true if cpu present */
29949e866e40b95795203f3ee46f44a197c946e4stevel ddi_iblock_cookie_t ic_trap_cookie; /* interrupt cookie */
29949e866e40b95795203f3ee46f44a197c946e4stevel /* CPR support */
29949e866e40b95795203f3ee46f44a197c946e4stevel int ps_present[MAXPS+1]; /* PS present t/f 0 not used */
29949e866e40b95795203f3ee46f44a197c946e4stevel int num_fans_failed; /* don't change fan speed if > 0 */
29949e866e40b95795203f3ee46f44a197c946e4stevel int initting; /* 1 is TRUE , 0 is FALSE , used to mask intrs */
29949e866e40b95795203f3ee46f44a197c946e4stevel boolean_t shutdown; /* TRUE = power off in error event */
29949e866e40b95795203f3ee46f44a197c946e4stevel#endif /* _KERNEL */
29949e866e40b95795203f3ee46f44a197c946e4stevel#endif /* _SYS_ENVCTRL_H */