29949e866e40b95795203f3ee46f44a197c946e4stevel/*
29949e866e40b95795203f3ee46f44a197c946e4stevel * CDDL HEADER START
29949e866e40b95795203f3ee46f44a197c946e4stevel *
29949e866e40b95795203f3ee46f44a197c946e4stevel * The contents of this file are subject to the terms of the
29949e866e40b95795203f3ee46f44a197c946e4stevel * Common Development and Distribution License (the "License").
29949e866e40b95795203f3ee46f44a197c946e4stevel * You may not use this file except in compliance with the License.
29949e866e40b95795203f3ee46f44a197c946e4stevel *
29949e866e40b95795203f3ee46f44a197c946e4stevel * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
29949e866e40b95795203f3ee46f44a197c946e4stevel * or http://www.opensolaris.org/os/licensing.
29949e866e40b95795203f3ee46f44a197c946e4stevel * See the License for the specific language governing permissions
29949e866e40b95795203f3ee46f44a197c946e4stevel * and limitations under the License.
29949e866e40b95795203f3ee46f44a197c946e4stevel *
29949e866e40b95795203f3ee46f44a197c946e4stevel * When distributing Covered Code, include this CDDL HEADER in each
29949e866e40b95795203f3ee46f44a197c946e4stevel * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
29949e866e40b95795203f3ee46f44a197c946e4stevel * If applicable, add the following below this CDDL HEADER, with the
29949e866e40b95795203f3ee46f44a197c946e4stevel * fields enclosed by brackets "[]" replaced with your own identifying
29949e866e40b95795203f3ee46f44a197c946e4stevel * information: Portions Copyright [yyyy] [name of copyright owner]
29949e866e40b95795203f3ee46f44a197c946e4stevel *
29949e866e40b95795203f3ee46f44a197c946e4stevel * CDDL HEADER END
29949e866e40b95795203f3ee46f44a197c946e4stevel */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/*
29949e866e40b95795203f3ee46f44a197c946e4stevel * Copyright 1998 Sun Microsystems, Inc. All rights reserved.
29949e866e40b95795203f3ee46f44a197c946e4stevel * Use is subject to license terms.
29949e866e40b95795203f3ee46f44a197c946e4stevel */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#ifndef _SYS_ENVCTRL_H
29949e866e40b95795203f3ee46f44a197c946e4stevel#define _SYS_ENVCTRL_H
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#pragma ident "%Z%%M% %I% %E% SMI"
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#ifdef __cplusplus
29949e866e40b95795203f3ee46f44a197c946e4stevelextern "C" {
29949e866e40b95795203f3ee46f44a197c946e4stevel#endif
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define OVERTEMP_TIMEOUT_USEC 60 * MICROSEC
29949e866e40b95795203f3ee46f44a197c946e4stevel#define BLINK_TIMEOUT_USEC 500 * (MICROSEC / MILLISEC)
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_NORMAL_MODE 0x01
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_DIAG_MODE 0x02
29949e866e40b95795203f3ee46f44a197c946e4stevel#define MAX_TAZ_CONTROLLERS 0x02
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_CHAR_ZERO 0x00
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PS_550 550
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PS_650 650
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_INIT_TEMPR 20
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_TAZCPU_STRING "SUNW,UltraSPARC"
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_TAZBLKBRDCPU_STRING "SUNW,UltraSPARC-II"
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_MAX_CPUS 8
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/*
29949e866e40b95795203f3ee46f44a197c946e4stevel * MACROS
29949e866e40b95795203f3ee46f44a197c946e4stevel */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define S1 &unitp->bus_ctl_regs->s1
29949e866e40b95795203f3ee46f44a197c946e4stevel#define S0 &unitp->bus_ctl_regs->s0
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/*
29949e866e40b95795203f3ee46f44a197c946e4stevel * I2c Sensor Types
29949e866e40b95795203f3ee46f44a197c946e4stevel */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCD8584 0x00 /* Bus Controller Master */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8591 0x01 /* Temp Sensor 8bit A/D, D/A */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8574 0x02 /* PS, FAN, LED, Fail and Control */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define TDA8444T 0x03 /* Fan Speed Control, 8 bit D/A */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8574A 0x04 /* 8574A chip */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8583 0x05 /* PCF8583 clock chip */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/*
29949e866e40b95795203f3ee46f44a197c946e4stevel * Max number of a particular
29949e866e40b95795203f3ee46f44a197c946e4stevel * device on 1 bus.
29949e866e40b95795203f3ee46f44a197c946e4stevel */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define MAX_DEVS 0x10
29949e866e40b95795203f3ee46f44a197c946e4stevel#define I2C_NODEV 0xFF
29949e866e40b95795203f3ee46f44a197c946e4stevel#define MIN_FAN_BANKS 0x02
29949e866e40b95795203f3ee46f44a197c946e4stevel#define INSTANCE_0 0x00
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/*
29949e866e40b95795203f3ee46f44a197c946e4stevel * Defines for the PCF8583 Clock Calendar Chip
29949e866e40b95795203f3ee46f44a197c946e4stevel * We use this chip as a watchdog timer for the fans
29949e866e40b95795203f3ee46f44a197c946e4stevel * should the kernel thread controling the fans get
29949e866e40b95795203f3ee46f44a197c946e4stevel * wedged. If it does, the alarm wil go off and
29949e866e40b95795203f3ee46f44a197c946e4stevel * set the fans to max speed.
29949e866e40b95795203f3ee46f44a197c946e4stevel * Valid addresses for this chip are A0, A2.
29949e866e40b95795203f3ee46f44a197c946e4stevel * We use the address at A0.
29949e866e40b95795203f3ee46f44a197c946e4stevel * To address this chip the format is as folows (write mode)
29949e866e40b95795203f3ee46f44a197c946e4stevel * | SLaveaddress |MEMORY LOCATION| DATA|
29949e866e40b95795203f3ee46f44a197c946e4stevel * Wgere memory location is the internal location from
29949e866e40b95795203f3ee46f44a197c946e4stevel * 0x00 - 0x0F. 0x00 is the CSR and MUST be addressed
29949e866e40b95795203f3ee46f44a197c946e4stevel * directly.
29949e866e40b95795203f3ee46f44a197c946e4stevel */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8583_BASE_ADDR 0xA0
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8583_READ_BIT 0x01
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CLOCK_CSR_REG 0x00
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ALARM_CTRL_REG 0x07
29949e866e40b95795203f3ee46f44a197c946e4stevel#define EGG_TIMER_VAL 0x96
29949e866e40b95795203f3ee46f44a197c946e4stevel#define DIAG_MAX_TIMER_VAL 0x00
29949e866e40b95795203f3ee46f44a197c946e4stevel#define MAX_CL_VAL 59
29949e866e40b95795203f3ee46f44a197c946e4stevel#define MIN_DIAG_TEMPR 0x00
29949e866e40b95795203f3ee46f44a197c946e4stevel#define MAX_DIAG_TEMPR 70
29949e866e40b95795203f3ee46f44a197c946e4stevel#define MAX_AMB_TEMP 50
29949e866e40b95795203f3ee46f44a197c946e4stevel#define MAX_CPU_TEMP 80
29949e866e40b95795203f3ee46f44a197c946e4stevel#define MAX_PS_TEMP 100
29949e866e40b95795203f3ee46f44a197c946e4stevel#define MAX_PS_ADVAL 0xfd
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PS_DEFAULT_VAL 17 /* corresponds to 90 C in lookup table */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PS_TEMP_WARN 95
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CPU_AMB_RISE 20 /* cpu runs avg of 20 above amb */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PS_AMB_RISE 30 /* cpu runs avg of 30 above amb */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CLOCK_ALARM_REG_A 0x08
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CLOCK_ENABLE_TIMER 0xCB
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CLOCK_ENABLE_TIMER_S 0xCA
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CLOCK_DISABLE 0xA0
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CLOCK_ENABLE 0x04
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Keyswitch Definitions */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_FSP_KEYMASK 0xC0
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_FSP_POMASK 0x20
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_FSP_KEYLOCKED 0x00
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_FSP_KEYOFF 0x40
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_FSP_KEYDIAG 0x80
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_FSP_KEYON 0xC0
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Disk Fault bit fields */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_DISK_0 0x01
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_DISK_1 0x02
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_DISK_2 0x04
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_DISK_3 0x08
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_DISK_4 0x10
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_DISK_5 0x20
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_DISK_6 0x40
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_DISK_7 0x80
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_4SLOT_BACKPLANE 0x0F
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_8SLOT_BACKPLANE 0xFF
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Front Status Panel Definitions */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_FSP_DISK_ERR 0x01
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_FSP_PS_ERR 0x02
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_FSP_TEMP_ERR 0x04
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_FSP_GEN_ERR 0x08
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_FSP_ACTIVE 0x10
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_FSP_POWER 0x20
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_FSP_USRMASK (ENVCTRL_FSP_DISK_ERR | ENVCTRL_FSP_GEN_ERR)
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_ENCL_FSP 0x00
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_ENCL_AMBTEMPR 0x01
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_ENCL_CPUTEMPR 0x02
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_ENCL_BACKPLANE4 0x03
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_ENCL_BACKPLANE8 0x04
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_FSP_OFF 0x4F
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_DISK4LED_ALLOFF 0xF0
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_DISK8LED_ALLOFF 0xFF
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Kstat Structures and defines */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_FAN_TYPE_CPU 0x00
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_FAN_TYPE_PS 0x01
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_FAN_TYPE_AFB 0x02
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_MODULE_NAME "envctrl"
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_KSTAT_NUMPS "envctrl_numps"
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_KSTAT_PSNAME "envctrl_pwrsupply"
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_KSTAT_NUMFANS "envctrl_numfans"
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_KSTAT_FANSTAT "envctrl_fanstat"
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_KSTAT_NUMENCLS "envctrl_numencls"
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_KSTAT_ENCL "envctrl_enclosure"
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4steveltypedef struct envctrl_ps {
29949e866e40b95795203f3ee46f44a197c946e4stevel int instance; /* instance of this type */
29949e866e40b95795203f3ee46f44a197c946e4stevel ushort_t ps_tempr; /* temperature */
29949e866e40b95795203f3ee46f44a197c946e4stevel int ps_rating; /* type in watts */
29949e866e40b95795203f3ee46f44a197c946e4stevel boolean_t ps_ok; /* normal state or not. */
29949e866e40b95795203f3ee46f44a197c946e4stevel boolean_t curr_share_ok; /* current share imbalance */
29949e866e40b95795203f3ee46f44a197c946e4stevel boolean_t limit_ok; /* overlimit warning */
29949e866e40b95795203f3ee46f44a197c946e4stevel} envctrl_ps_t;
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4steveltypedef struct envctrl_fan {
29949e866e40b95795203f3ee46f44a197c946e4stevel int instance; /* instance of this type */
29949e866e40b95795203f3ee46f44a197c946e4stevel int type; /* CPU, PS or AMBIENT fan */
29949e866e40b95795203f3ee46f44a197c946e4stevel boolean_t fans_ok; /* are the fans okay */
29949e866e40b95795203f3ee46f44a197c946e4stevel int fanflt_num; /* if not okay, which fan faulted */
29949e866e40b95795203f3ee46f44a197c946e4stevel uint_t fanspeed; /* chip to set speed of fans */
29949e866e40b95795203f3ee46f44a197c946e4stevel} envctrl_fan_t;
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4steveltypedef struct envctrl_encl {
29949e866e40b95795203f3ee46f44a197c946e4stevel int instance;
29949e866e40b95795203f3ee46f44a197c946e4stevel int type;
29949e866e40b95795203f3ee46f44a197c946e4stevel uint_t value;
29949e866e40b95795203f3ee46f44a197c946e4stevel} envctrl_encl_t;
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/*
29949e866e40b95795203f3ee46f44a197c946e4stevel * configuration registers
29949e866e40b95795203f3ee46f44a197c946e4stevel * Register S1 Looks like the following:
29949e866e40b95795203f3ee46f44a197c946e4stevel * WRITE MODE ONLY
29949e866e40b95795203f3ee46f44a197c946e4stevel *
29949e866e40b95795203f3ee46f44a197c946e4stevel * MSB -------------------------------------> LSB
29949e866e40b95795203f3ee46f44a197c946e4stevel * ----------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * | X | ESO | ES1 | ES2 | ENI | STA | STO | ACK |
29949e866e40b95795203f3ee46f44a197c946e4stevel * ----------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * Low order bits
29949e866e40b95795203f3ee46f44a197c946e4stevel */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CSRS1_ENI 0x08 /* Enable interrupts */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CSRS1_STA 0x04 /* Packet Start */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CSRS1_STO 0x02 /* Packet Stop */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CSRS1_ACK 0x01 /* Packet ACK */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Hight order bits */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CSRS1_PIN 0x80 /* READ and WRITE mode Enable Serial Output */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CSRS1_ESO 0x40 /* Enable Serial Output */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CSRS1_ES1 0x20
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CSRS1_ES2 0x10
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/*
29949e866e40b95795203f3ee46f44a197c946e4stevel * configuration registers
29949e866e40b95795203f3ee46f44a197c946e4stevel * Register S1 Looks like the following:
29949e866e40b95795203f3ee46f44a197c946e4stevel * READ MODE ONLY
29949e866e40b95795203f3ee46f44a197c946e4stevel *
29949e866e40b95795203f3ee46f44a197c946e4stevel * MSB -------------------------------------> LSB
29949e866e40b95795203f3ee46f44a197c946e4stevel * ----------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * | PIN | 0 | STS | BER | AD0/LRB | AAS | LAB | BB|
29949e866e40b95795203f3ee46f44a197c946e4stevel * ----------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CSRS1_STS 0x20 /* For Slave receiv mode stop */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CSRS1_BER 0x10 /* Bus Error */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CSRS1_LRB 0x08 /* Last Received Bit */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CSRS1_AAS 0x04 /* Addressed as Slave */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CSRS1_LAB 0x02 /* Lost Arbitration Bit */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CSRS1_BB 0x01 /* Bus Busy */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define START CSRS1_PIN | CSRS1_ESO | CSRS1_STA | CSRS1_ACK
29949e866e40b95795203f3ee46f44a197c946e4stevel#define STOP CSRS1_PIN | CSRS1_ESO | CSRS1_STO | CSRS1_ACK
29949e866e40b95795203f3ee46f44a197c946e4stevel/*
29949e866e40b95795203f3ee46f44a197c946e4stevel * A read wants to have an NACK on the bus to stop
29949e866e40b95795203f3ee46f44a197c946e4stevel * transmitting data from the slave. If you don't
29949e866e40b95795203f3ee46f44a197c946e4stevel * NACK the SDA line will get stuck low. After this you
29949e866e40b95795203f3ee46f44a197c946e4stevel * can send the stop with the ack.
29949e866e40b95795203f3ee46f44a197c946e4stevel */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define NACK CSRS1_PIN | CSRS1_ESO
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/*
29949e866e40b95795203f3ee46f44a197c946e4stevel * ESO = Enable Serial output
29949e866e40b95795203f3ee46f44a197c946e4stevel * ES1 and ES2 have different meanings based upon ES0.
29949e866e40b95795203f3ee46f44a197c946e4stevel * The following table explains this association.
29949e866e40b95795203f3ee46f44a197c946e4stevel *
29949e866e40b95795203f3ee46f44a197c946e4stevel * ES0 = 0 = serial interface off.
29949e866e40b95795203f3ee46f44a197c946e4stevel * ---------------------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * | A0 | ES1 | ES1 | iACK | OPERATION
29949e866e40b95795203f3ee46f44a197c946e4stevel * ---------------------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * | H | X | X | X | Read/write CSR1 (S1) Status n/a
29949e866e40b95795203f3ee46f44a197c946e4stevel * | | | | |
29949e866e40b95795203f3ee46f44a197c946e4stevel * | L | 0 | 0 | X | R/W Own Address S0'
29949e866e40b95795203f3ee46f44a197c946e4stevel * | | | | |
29949e866e40b95795203f3ee46f44a197c946e4stevel * | L | 0 | 1 | X | R/W Intr Vector S3
29949e866e40b95795203f3ee46f44a197c946e4stevel * | | | | |
29949e866e40b95795203f3ee46f44a197c946e4stevel * | L | 1 | 0 | X | R/W Clock Register S2
29949e866e40b95795203f3ee46f44a197c946e4stevel * ---------------------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel *
29949e866e40b95795203f3ee46f44a197c946e4stevel * ES0 = 1 = serial interface ON.
29949e866e40b95795203f3ee46f44a197c946e4stevel * ---------------------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * | A0 | ES1 | ES1 | iACK | OPERATION
29949e866e40b95795203f3ee46f44a197c946e4stevel * ---------------------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * | H | X | X | H | Write Control Register (S1)
29949e866e40b95795203f3ee46f44a197c946e4stevel * | | | | |
29949e866e40b95795203f3ee46f44a197c946e4stevel * | H | X | X | H | Read Status Register (S1)
29949e866e40b95795203f3ee46f44a197c946e4stevel * | | | | |
29949e866e40b95795203f3ee46f44a197c946e4stevel * | L | X | 0 | H | R/W Data Register (S0)
29949e866e40b95795203f3ee46f44a197c946e4stevel * | | | | |
29949e866e40b95795203f3ee46f44a197c946e4stevel * | L | X | 1 | H | R/W Interrupt Vector (S3)
29949e866e40b95795203f3ee46f44a197c946e4stevel * | | | | |
29949e866e40b95795203f3ee46f44a197c946e4stevel * | X | 0 | X | L | R Interrupt Vector (S3) ack cycle
29949e866e40b95795203f3ee46f44a197c946e4stevel * | | | | |
29949e866e40b95795203f3ee46f44a197c946e4stevel * | X | 1 | X | L | long distance mode
29949e866e40b95795203f3ee46f44a197c946e4stevel * ---------------------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel *
29949e866e40b95795203f3ee46f44a197c946e4stevel */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#ifdef TESTBED
29949e866e40b95795203f3ee46f44a197c946e4stevelstruct envctrl_pcd8584_regs {
29949e866e40b95795203f3ee46f44a197c946e4stevel uchar_t s0; /* Own Address S0' */
29949e866e40b95795203f3ee46f44a197c946e4stevel uchar_t pad[3]; /* Padding XXX Will go away in FCS */
29949e866e40b95795203f3ee46f44a197c946e4stevel uchar_t s1; /* Control Status register */
29949e866e40b95795203f3ee46f44a197c946e4stevel uchar_t pad1[3];
29949e866e40b95795203f3ee46f44a197c946e4stevel uchar_t clock_s2; /* Clock programming register */
29949e866e40b95795203f3ee46f44a197c946e4stevel};
29949e866e40b95795203f3ee46f44a197c946e4stevel#else
29949e866e40b95795203f3ee46f44a197c946e4stevelstruct envctrl_pcd8584_regs {
29949e866e40b95795203f3ee46f44a197c946e4stevel uchar_t s0; /* Own Address S0' */
29949e866e40b95795203f3ee46f44a197c946e4stevel uchar_t s1; /* Control Status register */
29949e866e40b95795203f3ee46f44a197c946e4stevel uchar_t clock_s2; /* Clock programming register */
29949e866e40b95795203f3ee46f44a197c946e4stevel};
29949e866e40b95795203f3ee46f44a197c946e4stevel#endif
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_BUS_INIT0 0x80
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_BUS_INIT1 0x55
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_BUS_CLOCK0 0xA0
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_BUS_CLOCK1 0x1C
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_BUS_ESI 0xC1
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/*
29949e866e40b95795203f3ee46f44a197c946e4stevel * PCF8591 Chip Used for temperature sensors
29949e866e40b95795203f3ee46f44a197c946e4stevel *
29949e866e40b95795203f3ee46f44a197c946e4stevel * Check with bob to see if singled ended inputs are true
29949e866e40b95795203f3ee46f44a197c946e4stevel * for the pcf8591 temp sensors..
29949e866e40b95795203f3ee46f44a197c946e4stevel *
29949e866e40b95795203f3ee46f44a197c946e4stevel * Addressing Register definition.
29949e866e40b95795203f3ee46f44a197c946e4stevel * A0-A2 valid range is 0-7
29949e866e40b95795203f3ee46f44a197c946e4stevel *
29949e866e40b95795203f3ee46f44a197c946e4stevel * 7 6 5 4 3 2 1 0
29949e866e40b95795203f3ee46f44a197c946e4stevel * ------------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * | 1 | 0 | 0 | 1 | A2 | A1 | A0 | R/W |
29949e866e40b95795203f3ee46f44a197c946e4stevel * ------------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8591_BASE_ADDR 0x90
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8501_MAX_DEVS 0x08
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define MAXPS 0x02 /* 0 based array */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PSTEMP0 0x00 /* DUMMY PS */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PSTEMP1 0x94
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PSTEMP2 0x92
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PSTEMP3 0x90
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_CPU_PCF8591_ADDR (PCF8591_BASE_ADDR | PCF8591_DEV7)
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8591_DEV0 0x00
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8591_DEV1 0x02
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8591_DEV2 0x04
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8591_DEV3 0x06
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8591_DEV4 0x08
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8591_DEV5 0x0A
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8591_DEV6 0x0C
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8591_DEV7 0x0E
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/*
29949e866e40b95795203f3ee46f44a197c946e4stevel * For the LM75 thermal watchdog chip by TI
29949e866e40b95795203f3ee46f44a197c946e4stevel */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define LM75_BASE_ADDR 0x9A
29949e866e40b95795203f3ee46f44a197c946e4stevel#define LM75_READ_BIT 0x01
29949e866e40b95795203f3ee46f44a197c946e4stevel#define LM75_CONFIG_ADDR2 0x02
29949e866e40b95795203f3ee46f44a197c946e4stevel#define LM75_CONFIG_ADDR4 0x04
29949e866e40b95795203f3ee46f44a197c946e4stevel#define LM75_CONFIG_ADDR6 0x06
29949e866e40b95795203f3ee46f44a197c946e4stevel#define LM75_CONFIG_ADDR8 0x08
29949e866e40b95795203f3ee46f44a197c946e4stevel#define LM75_CONFIG_ADDRA 0x0A
29949e866e40b95795203f3ee46f44a197c946e4stevel#define LM75_CONFIG_ADDRC 0x0C
29949e866e40b95795203f3ee46f44a197c946e4stevel#define LM75_CONFIG_ADDRE 0x0E
29949e866e40b95795203f3ee46f44a197c946e4stevel#define LM75_COMP_MASK 0x100
29949e866e40b95795203f3ee46f44a197c946e4stevel#define LM75_COMP_MASK_UPPER 0xFF
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/*
29949e866e40b95795203f3ee46f44a197c946e4stevel * CONTROL OF CHIP
29949e866e40b95795203f3ee46f44a197c946e4stevel * PCF8591 Temp sensing control register definitions
29949e866e40b95795203f3ee46f44a197c946e4stevel *
29949e866e40b95795203f3ee46f44a197c946e4stevel * 7 6 5 4 3 2 1 0
29949e866e40b95795203f3ee46f44a197c946e4stevel * ---------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * | 0 | AOE | X | X | 0 | AIF | X | X |
29949e866e40b95795203f3ee46f44a197c946e4stevel * ---------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * AOE = Analog out enable.. not used on out implementation
29949e866e40b95795203f3ee46f44a197c946e4stevel * 5 & 4 = Analog Input Programming.. see data sheet for bits..
29949e866e40b95795203f3ee46f44a197c946e4stevel *
29949e866e40b95795203f3ee46f44a197c946e4stevel * AIF = Auto increment flag
29949e866e40b95795203f3ee46f44a197c946e4stevel * bits 1 & 0 are for the Chennel number.
29949e866e40b95795203f3ee46f44a197c946e4stevel */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8591_ANALOG_OUTPUT_EN 0x40
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8591_ANALOG_INPUT_EN 0x00
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8591_READ_BIT 0x01
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8591_AUTO_INCR 0x04
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8591_OSCILATOR 0x40
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8591_MAX_PORTS 0x04
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8591_CH_0 0x00
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8591_CH_1 0x01
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8591_CH_2 0x02
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8591_CH_3 0x03
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevelstruct envctrl_pcf8591_chip {
29949e866e40b95795203f3ee46f44a197c946e4stevel uchar_t chip_num; /* valid values are 0-7 */
29949e866e40b95795203f3ee46f44a197c946e4stevel int type; /* type is PCF8591 */
29949e866e40b95795203f3ee46f44a197c946e4stevel uchar_t sensor_num; /* AIN0, AIN1, AIN2 AIN3 */
29949e866e40b95795203f3ee46f44a197c946e4stevel uchar_t temp_val; /* value of temp probe */
29949e866e40b95795203f3ee46f44a197c946e4stevel};
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/*
29949e866e40b95795203f3ee46f44a197c946e4stevel * PCF8574 Fan Fail, Power Supply Fail Detector
29949e866e40b95795203f3ee46f44a197c946e4stevel * This device is driven by interrupts. Each time it interrupts
29949e866e40b95795203f3ee46f44a197c946e4stevel * you must look at the CSR to see which ports caused the interrupt
29949e866e40b95795203f3ee46f44a197c946e4stevel * they are indicated by a 1.
29949e866e40b95795203f3ee46f44a197c946e4stevel *
29949e866e40b95795203f3ee46f44a197c946e4stevel * Address map of this chip
29949e866e40b95795203f3ee46f44a197c946e4stevel *
29949e866e40b95795203f3ee46f44a197c946e4stevel * -------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel * | 0 | 1 | 1 | 1 | A2 | A1 | A0 | 0 |
29949e866e40b95795203f3ee46f44a197c946e4stevel * -------------------------------------------
29949e866e40b95795203f3ee46f44a197c946e4stevel *
29949e866e40b95795203f3ee46f44a197c946e4stevel */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8574A_BASE_ADDR 0x70
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8574_BASE_ADDR 0x40
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PCF8574_READ_BIT 0x01
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PCF8574_DEV0 0x00
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PCF8574_DEV1 0x02
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PCF8574_DEV2 0x04
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PCF8574_DEV3 0x06
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PCF8574_DEV4 0x08
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PCF8574_DEV5 0x0A
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PCF8574_DEV6 0x0C
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PCF8574_DEV7 0x0E
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_INTR_CHIP PCF8574_DEV7
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PS1 PCF8574A_BASE_ADDR | ENVCTRL_PCF8574_DEV3
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PS2 PCF8574A_BASE_ADDR | ENVCTRL_PCF8574_DEV2
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PS3 PCF8574A_BASE_ADDR | ENVCTRL_PCF8574_DEV1
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PCF8574_PORT0 0x01
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PCF8574_PORT1 0x02
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PCF8574_PORT2 0x04
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PCF8574_PORT3 0x08
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PCF8574_PORT4 0x10
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PCF8574_PORT5 0x20
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PCF8574_PORT6 0x40
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PCF8574_PORT7 0x80
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_DFLOP_INIT0 0x77
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_DFLOP_INIT1 0x7F
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_DEVINTR_INTI0 0xF7
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_DEVINTR_INTI1 0xFF
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CPU_FAN_1 0x01
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CPU_FAN_2 0x02
29949e866e40b95795203f3ee46f44a197c946e4stevel#define CPU_FAN_3 0x03
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PS_FAN_1 CPU_FAN_1
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PS_FAN_2 CPU_FAN_2
29949e866e40b95795203f3ee46f44a197c946e4stevel#define PS_FAN_3 CPU_FAN_3
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define AFB_FAN_1 0x00
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevelstruct envctrl_pcf8574_chip {
29949e866e40b95795203f3ee46f44a197c946e4stevel uchar_t chip_num; /* valid values are 0-7 */
29949e866e40b95795203f3ee46f44a197c946e4stevel int type; /* type is PCF8574 */
29949e866e40b95795203f3ee46f44a197c946e4stevel uint_t val;
29949e866e40b95795203f3ee46f44a197c946e4stevel};
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/*
29949e866e40b95795203f3ee46f44a197c946e4stevel * TDA8444T chip structure
29949e866e40b95795203f3ee46f44a197c946e4stevel * FAN Speed Control
29949e866e40b95795203f3ee46f44a197c946e4stevel */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/* ADDRESSING */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define TDA8444T_BASE_ADDR 0x40
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_TDA8444T_DEV0 0x00
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_TDA8444T_DEV1 0x02
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_TDA8444T_DEV2 0x04
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_TDA8444T_DEV3 0x06
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_TDA8444T_DEV4 0x08
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_TDA8444T_DEV5 0x0A
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_TDA8444T_DEV6 0x0C
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_TDA8444T_DEV7 0x0E
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_FAN_ADDR_MIN ENVCTRL_TDA8444T_DEV0
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_FAN_ADDR_MAX ENVCTRL_TDA8444T_DEV7
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Control information and port addressing */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define NO_AUTO_PORT_INCR 0xF0
29949e866e40b95795203f3ee46f44a197c946e4stevel#define AUTO_PORT_INCR 0x00
29949e866e40b95795203f3ee46f44a197c946e4stevel#define TDA8444T_READ_BIT 0x01
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_CPU_FANS 0x00
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PS_FANS 0x01
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_AFB_FANS 0x02
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PORT3 0x03
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PORT4 0x04
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PORT5 0x05
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PORT6 0x06
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PORT7 0x07
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define MAX_FAN_SPEED 0x3f
29949e866e40b95795203f3ee46f44a197c946e4stevel#define MIN_FAN_VAL 0x00
29949e866e40b95795203f3ee46f44a197c946e4stevel#define MAX_FAN_VAL 0x3f
29949e866e40b95795203f3ee46f44a197c946e4stevel#define AFB_MAX 0x3f
29949e866e40b95795203f3ee46f44a197c946e4stevel#define AFB_MIN 0x1d
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevelstruct envctrl_tda8444t_chip {
29949e866e40b95795203f3ee46f44a197c946e4stevel uchar_t chip_num; /* valid values are 0-7 */
29949e866e40b95795203f3ee46f44a197c946e4stevel int type; /* type is TDA8444T */
29949e866e40b95795203f3ee46f44a197c946e4stevel uchar_t fan_num; /* Ao0-Ao7 */
29949e866e40b95795203f3ee46f44a197c946e4stevel uchar_t val; /* for fan speed */
29949e866e40b95795203f3ee46f44a197c946e4stevel};
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/*
29949e866e40b95795203f3ee46f44a197c946e4stevel * This table converts an A/D value from the cpu thermistor to a
29949e866e40b95795203f3ee46f44a197c946e4stevel * temperature in degrees C. Usable range is typically 35-135.
29949e866e40b95795203f3ee46f44a197c946e4stevel */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevelstatic short cpu_temps[] = {
29949e866e40b95795203f3ee46f44a197c946e4stevel150, 150, 150, 150, 150, 150, 150, 150, /* 0-7 */
29949e866e40b95795203f3ee46f44a197c946e4stevel150, 150, 150, 150, 150, 150, 150, 150, /* 8-15 */
29949e866e40b95795203f3ee46f44a197c946e4stevel150, 150, 150, 150, 150, 150, 150, 150, /* 16-23 */
29949e866e40b95795203f3ee46f44a197c946e4stevel150, 150, 150, 148, 146, 144, 143, 142, /* 24-31 */
29949e866e40b95795203f3ee46f44a197c946e4stevel141, 140, 138, 136, 135, 134, 133, 132, /* 32-39 */
29949e866e40b95795203f3ee46f44a197c946e4stevel131, 130, 129, 128, 127, 126, 125, 124, /* 40-47 */
29949e866e40b95795203f3ee46f44a197c946e4stevel123, 122, 121, 121, 120, 120, 119, 118, /* 48-55 */
29949e866e40b95795203f3ee46f44a197c946e4stevel117, 116, 115, 114, 113, 112, 112, 111, /* 56-63 */
29949e866e40b95795203f3ee46f44a197c946e4stevel111, 110, 110, 110, 109, 109, 108, 107, /* 64-71 */
29949e866e40b95795203f3ee46f44a197c946e4stevel106, 106, 105, 105, 104, 103, 102, 101, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel101, 100, 100, 100, 99, 99, 98, 98, /* 80-87 */
29949e866e40b95795203f3ee46f44a197c946e4stevel97, 97, 96, 96, 95, 95, 94, 94, /* 88-95 */
29949e866e40b95795203f3ee46f44a197c946e4stevel93, 93, 92, 92, 91, 91, 91, 90, /* 96-103 */
29949e866e40b95795203f3ee46f44a197c946e4stevel90, 90, 89, 89, 88, 88, 87, 87, /* 104-111 */
29949e866e40b95795203f3ee46f44a197c946e4stevel86, 86, 85, 85, 84, 84, 83, 83, /* 112-119 */
29949e866e40b95795203f3ee46f44a197c946e4stevel82, 82, 82, 81, 81, 80, 80, 80, /* 120-127 */
29949e866e40b95795203f3ee46f44a197c946e4stevel80, 79, 79, 79, 78, 78, 78, 77, /* 128-135 */
29949e866e40b95795203f3ee46f44a197c946e4stevel77, 77, 76, 76, 76, 75, 75, 75, /* 136-143 */
29949e866e40b95795203f3ee46f44a197c946e4stevel74, 74, 74, 73, 73, 73, 72, 72, /* 144-151 */
29949e866e40b95795203f3ee46f44a197c946e4stevel72, 71, 71, 71, 70, 70, 70, 70, /* 142-159 */
29949e866e40b95795203f3ee46f44a197c946e4stevel69, 69, 69, 68, 68, 68, 68, 67, /* 160-167 */
29949e866e40b95795203f3ee46f44a197c946e4stevel67, 67, 67, 66, 66, 66, 66, 65, /* 168-175 */
29949e866e40b95795203f3ee46f44a197c946e4stevel65, 65, 64, 64, 64, 63, 63, 63, /* 176-183 */
29949e866e40b95795203f3ee46f44a197c946e4stevel62, 62, 62, 61, 61, 61, 61, 60, /* 184-191 */
29949e866e40b95795203f3ee46f44a197c946e4stevel60, 60, 60, 59, 59, 59, 58, 58, /* 192-199 */
29949e866e40b95795203f3ee46f44a197c946e4stevel58, 57, 57, 57, 56, 56, 56, 56, /* 200-207 */
29949e866e40b95795203f3ee46f44a197c946e4stevel55, 55, 55, 55, 54, 54, 54, 53, /* 208-215 */
29949e866e40b95795203f3ee46f44a197c946e4stevel53, 53, 52, 52, 52, 51, 51, 51, /* 216-223 */
29949e866e40b95795203f3ee46f44a197c946e4stevel51, 50, 50, 50, 49, 49, 49, 48, /* 224-231 */
29949e866e40b95795203f3ee46f44a197c946e4stevel48, 48, 47, 47, 47, 46, 46, 46, /* 232-239 */
29949e866e40b95795203f3ee46f44a197c946e4stevel45, 45, 45, 44, 44, 44, 43, 43, /* 240-247 */
29949e866e40b95795203f3ee46f44a197c946e4stevel43, 42, 42, 42, 41, 41, 41, 40, /* 248-255 */
29949e866e40b95795203f3ee46f44a197c946e4stevel40, /* 256 */
29949e866e40b95795203f3ee46f44a197c946e4stevel};
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevelstatic short ps_temps[] = {
29949e866e40b95795203f3ee46f44a197c946e4stevel160, 155, 154, 150, 130, 125, 120, 115, /* 0-7 */
29949e866e40b95795203f3ee46f44a197c946e4stevel110, 110, 106, 103, 101, 100, 97, 94, /* 8-15 */
29949e866e40b95795203f3ee46f44a197c946e4stevel92, 90, 88, 86, 84, 83, 82, 81, /* 16-23 */
29949e866e40b95795203f3ee46f44a197c946e4stevel80, 79, 78, 77, 76, 74, 72, 71, /* 24-31 */
29949e866e40b95795203f3ee46f44a197c946e4stevel70, 69, 68, 67, 66, 65, 64, 63, /* 32-39 */
29949e866e40b95795203f3ee46f44a197c946e4stevel62, 62, 61, 61, 60, 60, 60, 59, /* 40-47 */
29949e866e40b95795203f3ee46f44a197c946e4stevel59, 58, 58, 57, 56, 56, 55, 55, /* 48-55 */
29949e866e40b95795203f3ee46f44a197c946e4stevel54, 54, 53, 53, 52, 52, 51, 51, /* 56-63 */
29949e866e40b95795203f3ee46f44a197c946e4stevel50, 50, 50, 49, 49, 49, 49, 48, /* 64-71 */
29949e866e40b95795203f3ee46f44a197c946e4stevel48, 48, 48, 47, 47, 47, 47, 46, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel46, 46, 45, 44, 43, 42, 41, 41, /* 80-87 */
29949e866e40b95795203f3ee46f44a197c946e4stevel40, 40, 40, 40, 39, 39, 39, 38, /* 88-95 */
29949e866e40b95795203f3ee46f44a197c946e4stevel38, 38, 37, 37, 36, 36, 36, 35, /* 96-103 */
29949e866e40b95795203f3ee46f44a197c946e4stevel35, 35, 35, 34, 34, 34, 33, 33, /* 104-111 */
29949e866e40b95795203f3ee46f44a197c946e4stevel32, 32, 32, 32, 32, 32, 31, 31, /* 112-119 */
29949e866e40b95795203f3ee46f44a197c946e4stevel31, 31, 31, 30, 30, 30, 29, 29, /* 120-127 */
29949e866e40b95795203f3ee46f44a197c946e4stevel29, 29, 29, 29, 28, 28, 28, 28, /* 128-135 */
29949e866e40b95795203f3ee46f44a197c946e4stevel28, 28, 27, 27, 27, 27, 27, 26, /* 136-143 */
29949e866e40b95795203f3ee46f44a197c946e4stevel26, 26, 26, 26, 26, 26, 26, 26, /* 144-151 */
29949e866e40b95795203f3ee46f44a197c946e4stevel25, 25, 25, 25, 24, 24, 23, 23, /* 142-159 */
29949e866e40b95795203f3ee46f44a197c946e4stevel22, 22, 21, 21, 21, 21, 21, 21, /* 160-167 */
29949e866e40b95795203f3ee46f44a197c946e4stevel20, 20, 20, 20, 19, 19, 19, 19, /* 168-175 */
29949e866e40b95795203f3ee46f44a197c946e4stevel19, 18, 18, 18, 18, 18, 17, 17, /* 176-183 */
29949e866e40b95795203f3ee46f44a197c946e4stevel17, 17, 17, 16, 16, 16, 16, 15, /* 184-191 */
29949e866e40b95795203f3ee46f44a197c946e4stevel15, 15, 15, 15, 15, 14, 14, 14, /* 192-199 */
29949e866e40b95795203f3ee46f44a197c946e4stevel14, 14, 13, 13, 13, 13, 12, 12, /* 200-207 */
29949e866e40b95795203f3ee46f44a197c946e4stevel12, 12, 12, 11, 11, 11, 11, 11, /* 208-215 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 216-223 */
29949e866e40b95795203f3ee46f44a197c946e4stevel9, 9, 9, 9, 9, 9, 8, 8, /* 224-231 */
29949e866e40b95795203f3ee46f44a197c946e4stevel8, 8, 8, 7, 7, 7, 7, 7, /* 232-239 */
29949e866e40b95795203f3ee46f44a197c946e4stevel7, 6, 6, 6, 6, 6, 6, 6, /* 240-247 */
29949e866e40b95795203f3ee46f44a197c946e4stevel5, 5, 5, 5, 5, 5, 5, 4, /* 248-255 */
29949e866e40b95795203f3ee46f44a197c946e4stevel4, /* 256 */
29949e866e40b95795203f3ee46f44a197c946e4stevel};
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/*
29949e866e40b95795203f3ee46f44a197c946e4stevel * This is the lookup table used for P1 and FCS systems to convert a temperature
29949e866e40b95795203f3ee46f44a197c946e4stevel * to a fanspeed for the CPU side of the machine.
29949e866e40b95795203f3ee46f44a197c946e4stevel */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevelstatic short acme_cpu_fanspd[] = {
29949e866e40b95795203f3ee46f44a197c946e4stevel31, 31, 31, 31, 31, 31, 31, 31, /* 0-7 */
29949e866e40b95795203f3ee46f44a197c946e4stevel31, 31, 31, 31, 31, 31, 31, 31, /* 8-15 */
29949e866e40b95795203f3ee46f44a197c946e4stevel31, 31, 31, 31, 31, 31, 31, 31, /* 16-23 */
29949e866e40b95795203f3ee46f44a197c946e4stevel31, 31, 31, 31, 32, 33, 34, 35, /* 24-31 */
29949e866e40b95795203f3ee46f44a197c946e4stevel36, 37, 38, 39, 40, 42, 43, 45, /* 32-39 */
29949e866e40b95795203f3ee46f44a197c946e4stevel48, 49, 50, 51, 52, 53, 54, 55, /* 40-47 */
29949e866e40b95795203f3ee46f44a197c946e4stevel56, 57, 58, 59, 60, 61, 62, 63, /* 48-55 */
29949e866e40b95795203f3ee46f44a197c946e4stevel63, 63, 63, 63, 63, 63, 63, 63, /* 56-63 */
29949e866e40b95795203f3ee46f44a197c946e4stevel63, 63, 63, 63, 63, 63, 63, 63, /* 64-71 */
29949e866e40b95795203f3ee46f44a197c946e4stevel63, 63, 63, 63, 63, 63, 63, 63, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel63, 63, 63, 63, 63, 63, 63, 63, /* 80-87 */
29949e866e40b95795203f3ee46f44a197c946e4stevel63, 63, 63, 63, 63, 63, 63, 63, /* 88-95 */
29949e866e40b95795203f3ee46f44a197c946e4stevel63, 63, 63, 63, 63, 63, 63, 63, /* 96-103 */
29949e866e40b95795203f3ee46f44a197c946e4stevel63, 63, 63, 63, 63, 63, 63, 63, /* 104-111 */
29949e866e40b95795203f3ee46f44a197c946e4stevel};
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/*
29949e866e40b95795203f3ee46f44a197c946e4stevel * This is the lookup table used for P1 and FCS systems to convert a temperature
29949e866e40b95795203f3ee46f44a197c946e4stevel * to a fanspeed for the CPU side of the machine.
29949e866e40b95795203f3ee46f44a197c946e4stevel */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevelstatic short acme_ps_fanspd[] = {
29949e866e40b95795203f3ee46f44a197c946e4stevel31, 31, 31, 31, 31, 31, 31, 31, /* 0-7 */
29949e866e40b95795203f3ee46f44a197c946e4stevel31, 31, 31, 31, 31, 31, 31, 31, /* 8-15 */
29949e866e40b95795203f3ee46f44a197c946e4stevel31, 31, 31, 31, 31, 31, 31, 31, /* 16-23 */
29949e866e40b95795203f3ee46f44a197c946e4stevel31, 31, 31, 31, 31, 33, 34, 35, /* 24-31 */
29949e866e40b95795203f3ee46f44a197c946e4stevel36, 37, 38, 38, 39, 40, 41, 42, /* 32-39 */
29949e866e40b95795203f3ee46f44a197c946e4stevel43, 45, 46, 47, 48, 48, 48, 48, /* 40-47 */
29949e866e40b95795203f3ee46f44a197c946e4stevel48, 48, 49, 50, 51, 52, 53, 54, /* 48-55 */
29949e866e40b95795203f3ee46f44a197c946e4stevel55, 56, 57, 58, 59, 60, 61, 62, /* 56-63 */
29949e866e40b95795203f3ee46f44a197c946e4stevel63, 63, 63, 63, 63, 63, 63, 63, /* 64-71 */
29949e866e40b95795203f3ee46f44a197c946e4stevel63, 63, 63, 63, 63, 63, 63, 63, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel63, 63, 63, 63, 63, 63, 63, 63, /* 80-87 */
29949e866e40b95795203f3ee46f44a197c946e4stevel63, 63, 63, 63, 63, 63, 63, 63, /* 88-95 */
29949e866e40b95795203f3ee46f44a197c946e4stevel63, 63, 63, 63, 63, 63, 63, 63, /* 96-103 */
29949e866e40b95795203f3ee46f44a197c946e4stevel63, 63, 63, 63, 63, 63, 63, 63, /* 104-111 */
29949e866e40b95795203f3ee46f44a197c946e4stevel};
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevelstatic short ps_fans[] = {
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 0-7 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 8-15 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 16-23 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 24-31 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 32-39 */
29949e866e40b95795203f3ee46f44a197c946e4stevel11, 12, 13, 14, 15, 16, 17, 18, /* 24-31 */
29949e866e40b95795203f3ee46f44a197c946e4stevel19, 20, 21, 22, 23, 24, 25, 26, /* 32-39 */
29949e866e40b95795203f3ee46f44a197c946e4stevel27, 28, 29, 30, 31, 32, 33, 34, /* 40-47 */
29949e866e40b95795203f3ee46f44a197c946e4stevel35, 36, 37, 38, 39, 40, 41, 42, /* 48-55 */
29949e866e40b95795203f3ee46f44a197c946e4stevel43, 44, 45, 46, 47, 48, 49, 50, /* 56-63 */
29949e866e40b95795203f3ee46f44a197c946e4stevel50, 50, 50, 50, 50, 50, 50, 50, /* 56-63 */
29949e866e40b95795203f3ee46f44a197c946e4stevel13, 12, 11, 10, 10, 10, 10, 10, /* 64-71 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10, 10, 10, 10, 10, 10, 10, 10, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel10,
29949e866e40b95795203f3ee46f44a197c946e4stevel};
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel/*
29949e866e40b95795203f3ee46f44a197c946e4stevel * Get a fan speed setting based upon a temperature value
29949e866e40b95795203f3ee46f44a197c946e4stevel * from the above lookup tables.
29949e866e40b95795203f3ee46f44a197c946e4stevel * Less than zero ia a special case and greater than 70 is a
29949e866e40b95795203f3ee46f44a197c946e4stevel * the operating range of the powersupply. The system operating
29949e866e40b95795203f3ee46f44a197c946e4stevel * range is 5 - 40 Degrees C.
29949e866e40b95795203f3ee46f44a197c946e4stevel * This may need some tuning.
29949e866e40b95795203f3ee46f44a197c946e4stevel * The MAX_CPU_TEMP is set to 80 now, this table is used to set their
29949e866e40b95795203f3ee46f44a197c946e4stevel * fans.
29949e866e40b95795203f3ee46f44a197c946e4stevel */
29949e866e40b95795203f3ee46f44a197c946e4stevelstatic short fan_speed[] = {
29949e866e40b95795203f3ee46f44a197c946e4stevel30, 29, 28, 27, 26, 25, 24, 23, /* 0-7 */
29949e866e40b95795203f3ee46f44a197c946e4stevel23, 23, 23, 23, 22, 21, 20, 20, /* 8-15 */
29949e866e40b95795203f3ee46f44a197c946e4stevel20, 20, 20, 20, 20, 20, 20, 20, /* 16-23 */
29949e866e40b95795203f3ee46f44a197c946e4stevel19, 18, 17, 16, 15, 14, 13, 12, /* 24-31 */
29949e866e40b95795203f3ee46f44a197c946e4stevel11, 11, 11, 11, 11, 11, 11, 11, /* 32-39 */
29949e866e40b95795203f3ee46f44a197c946e4stevel11, 11, 11, 10, 10, 10, 9, 8, /* 40-47 */
29949e866e40b95795203f3ee46f44a197c946e4stevel7, 6, 5, 4, 3, 2, 1, 1, /* 48-55 */
29949e866e40b95795203f3ee46f44a197c946e4stevel1, 1, 1, 1, 1, 1, 1, 1, /* 56-63 */
29949e866e40b95795203f3ee46f44a197c946e4stevel1, 1, 1, 1, 1, 1, 1, 1, /* 64-71 */
29949e866e40b95795203f3ee46f44a197c946e4stevel1, 1, 1, 1, 1, 1, 1, 1, /* 72-79 */
29949e866e40b95795203f3ee46f44a197c946e4stevel1, 1, 1, 1, 1, 1, 1, 1, /* 80-87 */
29949e866e40b95795203f3ee46f44a197c946e4stevel};
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PANEL_LEDS_PR "panel-leds-present"
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_PANEL_LEDS_STA "panel-leds-state"
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_DISK_LEDS_PR "disk-leds-present"
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_DISK_LEDS_STA "disk-leds-state"
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_LED_BLINK "activity-led-blink?"
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_RESETTMPR (int)(_IOW('p', 76, uchar_t))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_SETMODE (int)(_IOW('p', 77, uchar_t))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_SETTEMP (int)(_IOW('p', 79, uchar_t))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_SETFAN (int)(_IOW('p', 80, struct envctrl_tda8444t_chip))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_SETWDT (int)(_IOW('p', 81, uchar_t))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_GETFAN (int)(_IOR('p', 81, struct envctrl_tda8444t_chip))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_GETTEMP (int)(_IOR('p', 82, struct envctrl_pcf8591_chip))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_GETFANFAIL (int)(_IOR('p', 83, struct envctrl_pcf8574_chip))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_SETFSP (int)(_IOW('p', 84, uchar_t))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_SETDSKLED (int)(_IOW('p', 85, struct envctrl_pcf8574_chip))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_GETDSKLED (int)(_IOR('p', 86, struct envctrl_pcf8574_chip))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define ENVCTRL_IOC_GETMODE (int)(_IOR('p', 87, uchar_t))
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#if defined(_KERNEL)
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevelstruct envctrlunit {
29949e866e40b95795203f3ee46f44a197c946e4stevel struct envctrl_pcd8584_regs *bus_ctl_regs;
29949e866e40b95795203f3ee46f44a197c946e4stevel ddi_acc_handle_t ctlr_handle;
29949e866e40b95795203f3ee46f44a197c946e4stevel kmutex_t umutex; /* lock for this structure */
29949e866e40b95795203f3ee46f44a197c946e4stevel int instance;
29949e866e40b95795203f3ee46f44a197c946e4stevel dev_info_t *dip; /* device information */
29949e866e40b95795203f3ee46f44a197c946e4stevel struct envctrl_ps ps_kstats[MAX_DEVS]; /* kstats for powersupplies */
29949e866e40b95795203f3ee46f44a197c946e4stevel struct envctrl_fan fan_kstats[MAX_DEVS]; /* kstats for fans */
29949e866e40b95795203f3ee46f44a197c946e4stevel struct envctrl_encl encl_kstats[MAX_DEVS]; /* kstats for enclosure */
29949e866e40b95795203f3ee46f44a197c946e4stevel int cpu_pr_location[ENVCTRL_MAX_CPUS]; /* slot true if cpu present */
29949e866e40b95795203f3ee46f44a197c946e4stevel uint_t num_fans_present;
29949e866e40b95795203f3ee46f44a197c946e4stevel uint_t num_ps_present;
29949e866e40b95795203f3ee46f44a197c946e4stevel uint_t num_encl_present;
29949e866e40b95795203f3ee46f44a197c946e4stevel uint_t num_cpus_present;
29949e866e40b95795203f3ee46f44a197c946e4stevel kstat_t *psksp;
29949e866e40b95795203f3ee46f44a197c946e4stevel kstat_t *fanksp;
29949e866e40b95795203f3ee46f44a197c946e4stevel kstat_t *enclksp;
29949e866e40b95795203f3ee46f44a197c946e4stevel ddi_iblock_cookie_t ic_trap_cookie; /* interrupt cookie */
29949e866e40b95795203f3ee46f44a197c946e4stevel queue_t *readq; /* pointer to readq */
29949e866e40b95795203f3ee46f44a197c946e4stevel queue_t *writeq; /* pointer to writeq */
29949e866e40b95795203f3ee46f44a197c946e4stevel mblk_t *msg; /* current message block */
29949e866e40b95795203f3ee46f44a197c946e4stevel /* CPR support */
29949e866e40b95795203f3ee46f44a197c946e4stevel boolean_t suspended; /* TRUE if driver suspended */
29949e866e40b95795203f3ee46f44a197c946e4stevel boolean_t oflag; /* already open */
29949e866e40b95795203f3ee46f44a197c946e4stevel int current_mode; /* NORMAL or DIAG_MODE */
29949e866e40b95795203f3ee46f44a197c946e4stevel int AFB_present; /* is the AFB present */
29949e866e40b95795203f3ee46f44a197c946e4stevel timeout_id_t timeout_id; /* timeout id */
29949e866e40b95795203f3ee46f44a197c946e4stevel timeout_id_t pshotplug_id; /* ps poll id */
29949e866e40b95795203f3ee46f44a197c946e4stevel int ps_present[MAXPS+1]; /* PS present t/f 0 not used */
29949e866e40b95795203f3ee46f44a197c946e4stevel int num_fans_failed; /* don't change fan speed if > 0 */
29949e866e40b95795203f3ee46f44a197c946e4stevel int activity_led_blink;
29949e866e40b95795203f3ee46f44a197c946e4stevel int present_led_state; /* is it on or off?? */
29949e866e40b95795203f3ee46f44a197c946e4stevel timeout_id_t blink_timeout_id;
29949e866e40b95795203f3ee46f44a197c946e4stevel int initting; /* 1 is TRUE , 0 is FALSE , used to mask intrs */
29949e866e40b95795203f3ee46f44a197c946e4stevel boolean_t shutdown; /* TRUE = power off in error event */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel};
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#endif /* _KERNEL */
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#ifdef __cplusplus
29949e866e40b95795203f3ee46f44a197c946e4stevel}
29949e866e40b95795203f3ee46f44a197c946e4stevel#endif
29949e866e40b95795203f3ee46f44a197c946e4stevel
29949e866e40b95795203f3ee46f44a197c946e4stevel#endif /* _SYS_ENVCTRL_H */