29949e866e40b95795203f3ee46f44a197c946e4stevel * CDDL HEADER START
29949e866e40b95795203f3ee46f44a197c946e4stevel * The contents of this file are subject to the terms of the
29949e866e40b95795203f3ee46f44a197c946e4stevel * Common Development and Distribution License (the "License").
29949e866e40b95795203f3ee46f44a197c946e4stevel * You may not use this file except in compliance with the License.
29949e866e40b95795203f3ee46f44a197c946e4stevel * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
29949e866e40b95795203f3ee46f44a197c946e4stevel * See the License for the specific language governing permissions
29949e866e40b95795203f3ee46f44a197c946e4stevel * and limitations under the License.
29949e866e40b95795203f3ee46f44a197c946e4stevel * When distributing Covered Code, include this CDDL HEADER in each
29949e866e40b95795203f3ee46f44a197c946e4stevel * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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29949e866e40b95795203f3ee46f44a197c946e4stevel * fields enclosed by brackets "[]" replaced with your own identifying
29949e866e40b95795203f3ee46f44a197c946e4stevel * information: Portions Copyright [yyyy] [name of copyright owner]
29949e866e40b95795203f3ee46f44a197c946e4stevel * CDDL HEADER END
29949e866e40b95795203f3ee46f44a197c946e4stevel * Copyright 2005 Sun Microsystems, Inc. All rights reserved.
29949e866e40b95795203f3ee46f44a197c946e4stevel * Use is subject to license terms.
29949e866e40b95795203f3ee46f44a197c946e4stevel#pragma ident "%Z%%M% %I% %E% SMI"
29949e866e40b95795203f3ee46f44a197c946e4stevelextern "C" {
29949e866e40b95795203f3ee46f44a197c946e4stevel/* useful debugging stuff */
29949e866e40b95795203f3ee46f44a197c946e4stevel * OBP supplies us with 6 register sets for the FHC. The code for the fhc
29949e866e40b95795203f3ee46f44a197c946e4stevel * driver relies on these register sets being presented by the PROM in the
29949e866e40b95795203f3ee46f44a197c946e4stevel * order specified below. If this changes, the following comments must be
29949e866e40b95795203f3ee46f44a197c946e4stevel * revised and the code in fhc_init() must be changed to reflect these
29949e866e40b95795203f3ee46f44a197c946e4stevel * revisions.
29949e866e40b95795203f3ee46f44a197c946e4stevel * They are:
29949e866e40b95795203f3ee46f44a197c946e4stevel * 0 FHC internal registers
29949e866e40b95795203f3ee46f44a197c946e4stevel * 1 IGR Interrupt Group Number
29949e866e40b95795203f3ee46f44a197c946e4stevel * 2 FanFail IMR, ISMR
29949e866e40b95795203f3ee46f44a197c946e4stevel * 3 System IMR, ISMR
29949e866e40b95795203f3ee46f44a197c946e4stevel * 4 UART IMR, ISMR
29949e866e40b95795203f3ee46f44a197c946e4stevel * 5 TOD IMR, ISMR
29949e866e40b95795203f3ee46f44a197c946e4stevel * The offsets are defined as offsets from the base of the OBP register
29949e866e40b95795203f3ee46f44a197c946e4stevel * set which the register belongs to.
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Register set 0 */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define FHC_OFF_RCTRL 0x10 /* FHC Reset Control and Status */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define FHC_OFF_CTRL 0x20 /* FHC Control and Status */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define FHC_OFF_BSR 0x30 /* FHC Board Status Register */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define FHC_OFF_JTAG_CTRL 0xF0 /* JTAG Control Register */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define FHC_OFF_JTAG_CMD 0x100 /* JTAG Comamnd Register */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Register sets 2-5, the ISMR offset is the same */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define FHC_OFF_ISMR 0x10 /* FHC Interrupt State Machine */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Bit field defines for FHC Control and Status Register */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* NOTE: this bit is only used by firmware and must always be cleared by OS */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Bit field defines for FHC Reset Control and Status Register */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Bit field defines for the JTAG control register. */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Macros for decoding UPA speed pins from the Board Status Register */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Macro for extracting the "plus" bit from the Board Status Register */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Macros for physical access */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define FHC_CTRL(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \
29949e866e40b95795203f3ee46f44a197c946e4stevel#define FHC_JTAG_CTRL(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \
29949e866e40b95795203f3ee46f44a197c946e4stevel#define FHC_IGN(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \
29949e866e40b95795203f3ee46f44a197c946e4stevel#define FHC_SIM(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \
29949e866e40b95795203f3ee46f44a197c946e4stevel#define FHC_SSM(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \
29949e866e40b95795203f3ee46f44a197c946e4stevel#define FHC_UIM(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \
29949e866e40b95795203f3ee46f44a197c946e4stevel#define FHC_USM(board) (FHC_BOARD_BASE(2*(board)) + FHC_OFFSET + \
29949e866e40b95795203f3ee46f44a197c946e4stevel * the foolowing defines are used for trans phy-addr to board number
29949e866e40b95795203f3ee46f44a197c946e4stevel * The following defines are used by the fhc driver to determine the
29949e866e40b95795203f3ee46f44a197c946e4stevel * difference between IO and CPU type boards. This will be replaced
29949e866e40b95795203f3ee46f44a197c946e4stevel * later by JTAG scan to determine board type.
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Bit field defines for Board Status Register */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Bit field defines for the FHC Board Status Register when on a disk board */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Size of temperature recording array */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Maximum number of boards in system */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Maximum number of Board Power Supplies. */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Use predefined strings to name the kstats from this driver. */
29949e866e40b95795203f3ee46f44a197c946e4stevel * The following defines are for the AC chip, but are needed to be global,
29949e866e40b95795203f3ee46f44a197c946e4stevel * so have been put in the fhc header file.
29949e866e40b95795203f3ee46f44a197c946e4stevel * Most Sunfire ASICs have the chip rev encoded into bits 31-28 of the
29949e866e40b95795203f3ee46f44a197c946e4stevel * component ID register.
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Use predefined strings to name the kstats from this driver. */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Bit field defines for Interrupt Mapping registers */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define IMR_VALID ((uint_t)1 << INR_EN_SHIFT) /* Mondo valid bit */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Bit defines for Interrupt State Machine Register */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define INT_PENDING 3 /* state of the interrupt dispatch */
29949e866e40b95795203f3ee46f44a197c946e4stevel uint_t mapping_reg_cache; /* cache current value for CPR */
29949e866e40b95795203f3ee46f44a197c946e4stevel * Convert the Board Number field in the FHC Board Status Register to
29949e866e40b95795203f3ee46f44a197c946e4stevel * a board number. The field in the register is bits 0,3-1 of the board
29949e866e40b95795203f3ee46f44a197c946e4stevel * number. Therefore a macro is necessary to extract the board number.
29949e866e40b95795203f3ee46f44a197c946e4stevel#define FHC_PS2BOARD(ps) ((((ps) & 0x6) << 1) | ((ps) & 0x1))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define FHC_BOARD2PS(board) ((((board) & 0xc) >> 1) | ((board) & 0x1))
29949e866e40b95795203f3ee46f44a197c946e4stevel/* this base address is assumed to never map to real memory */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define FHC_BOARD_BASE(cpuid) (FHC_BOARD_0 + (cpuid) * FHC_BOARD_SPAN)
29949e866e40b95795203f3ee46f44a197c946e4stevel#define FHC_DTAG_BASE(cpuid) (FHC_BOARD_BASE(cpuid) + FHC_DTAG_OFFSET)
29949e866e40b95795203f3ee46f44a197c946e4stevel * Each Sunfire CPU Board has 32Kbytes of SRAM on the FireHose Bus.
29949e866e40b95795203f3ee46f44a197c946e4stevel * The SRAM is allocated as follows:
29949e866e40b95795203f3ee46f44a197c946e4stevel * 0x1ff.f020.0000 - 0x1ff.f020.5fff scratch/stacks
29949e866e40b95795203f3ee46f44a197c946e4stevel * 0x1ff.f020.6000 - 0x1ff.f020.67ff reset info (2K bytes)
29949e866e40b95795203f3ee46f44a197c946e4stevel * 0x1ff.f020.6800 - 0x1ff.f020.6fff POST private (2K bytes)
29949e866e40b95795203f3ee46f44a197c946e4stevel * 0x1ff.f020.7000 - 0x1ff.f020.77ff OS private (2K bytes)
29949e866e40b95795203f3ee46f44a197c946e4stevel * 0x1ff.f020.7800 - 0x1ff.f020.7fff OBP private (2K bytes)
29949e866e40b95795203f3ee46f44a197c946e4stevel#define FHC_LOCAL_OS_PAGEBASE ((FHC_LOCAL_SRAM_BASE + FHC_SRAM_OS_BASE) & \
29949e866e40b95795203f3ee46f44a197c946e4stevel#define FHC_SRAM_OS_OFFSET ((FHC_LOCAL_SRAM_BASE + FHC_SRAM_OS_BASE) & \
29949e866e40b95795203f3ee46f44a197c946e4stevel * Defines for the kstats created for passing temperature values and
29949e866e40b95795203f3ee46f44a197c946e4stevel * history out to user level programs. All temperatures passed out
29949e866e40b95795203f3ee46f44a197c946e4stevel * will be in degrees Centigrade, corrected for the board type the
29949e866e40b95795203f3ee46f44a197c946e4stevel * temperature was read from. Since each Board type has a different
29949e866e40b95795203f3ee46f44a197c946e4stevel * response curve for the A/D convertor, the temperatures are all
29949e866e40b95795203f3ee46f44a197c946e4stevel * calibrated inside the kernel.
29949e866e40b95795203f3ee46f44a197c946e4stevel * This kstat is used for manually overriding temperatures.
29949e866e40b95795203f3ee46f44a197c946e4stevel#define TEMP_OVERRIDE_KSTAT_NAME "temperature override"
29949e866e40b95795203f3ee46f44a197c946e4stevel * Time averaging based method of recording temperature history.
29949e866e40b95795203f3ee46f44a197c946e4stevel * Higher level temperature arrays are composed of temperature averages
29949e866e40b95795203f3ee46f44a197c946e4stevel * of the array one level below. When the lower array completes a
29949e866e40b95795203f3ee46f44a197c946e4stevel * set of data, the data is averaged and placed into the higher
29949e866e40b95795203f3ee46f44a197c946e4stevel * level array. Then the lower level array is overwritten until
29949e866e40b95795203f3ee46f44a197c946e4stevel * it is once again complete, where the process repeats.
29949e866e40b95795203f3ee46f44a197c946e4stevel * This method gives a user a fine grained view of the last minute,
29949e866e40b95795203f3ee46f44a197c946e4stevel * and larger grained views of the temperature as one goes back in
29949e866e40b95795203f3ee46f44a197c946e4stevel * The time units for the longer samples are based on the value
29949e866e40b95795203f3ee46f44a197c946e4stevel * of the OVERTEMP_TIMEOUT_SEC and the number of elements in each
29949e866e40b95795203f3ee46f44a197c946e4stevel * of the arrays between level 1 and the higher level.
29949e866e40b95795203f3ee46f44a197c946e4stevel/* definition of the clock board index */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define L1_SZ 30 /* # of OVERTEMP_TIMEOUT_SEC samples */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define L2_SZ 15 /* size of array for level 2 samples */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define L3_SZ 12 /* size of array for level 3 samples */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define L4_SZ 4 /* size of array for level 4 samples */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define L5_SZ 2 /* size of array for level 5 samples */
29949e866e40b95795203f3ee46f44a197c946e4stevel * Macros for determining when to do the temperature averaging of arrays.
29949e866e40b95795203f3ee46f44a197c946e4stevel#define L5_INDEX(i) ((i) / (L1_SZ * L2_SZ * L3_SZ * L4_SZ))
29949e866e40b95795203f3ee46f44a197c946e4stevel#define L5_REM(i) ((i) % (L1_SZ * L2_SZ * L3_SZ * L4_SZ))
29949e866e40b95795203f3ee46f44a197c946e4stevel * define for an illegal temperature. This temperature will never be seen
29949e866e40b95795203f3ee46f44a197c946e4stevel * in a real system, so it is used as an illegal value in the various
29949e866e40b95795203f3ee46f44a197c946e4stevel * functions processing the temperature data structure.
29949e866e40b95795203f3ee46f44a197c946e4stevel * State variable for board temperature. Each board has its own
29949e866e40b95795203f3ee46f44a197c946e4stevel * temperature state. State transitions from OK -> bad direction
29949e866e40b95795203f3ee46f44a197c946e4stevel * happen instantaneously, but use a counter in the opposite
29949e866e40b95795203f3ee46f44a197c946e4stevel * direction, so that noise in the A/D counters does not cause
29949e866e40b95795203f3ee46f44a197c946e4stevel * a large number of messages to appear.
29949e866e40b95795203f3ee46f44a197c946e4stevelenum temp_state { TEMP_OK = 0, /* normal board temperature */
29949e866e40b95795203f3ee46f44a197c946e4stevel * Number of temperature poll counts to wait before printing that the
29949e866e40b95795203f3ee46f44a197c946e4stevel * system has cooled down.
29949e866e40b95795203f3ee46f44a197c946e4stevel#define TEMP_STATE_COUNT ((TEMP_STATE_TIMEOUT_SEC) / \
29949e866e40b95795203f3ee46f44a197c946e4stevel * Number of poll counts that a system temperature must be at or above danger
29949e866e40b95795203f3ee46f44a197c946e4stevel * temperature before system is halted and powers down.
29949e866e40b95795203f3ee46f44a197c946e4stevel * State variable for temperature trend. Each state represents the
29949e866e40b95795203f3ee46f44a197c946e4stevel * current temperature trend for a given device.
29949e866e40b95795203f3ee46f44a197c946e4stevelenum temp_trend { TREND_UNKNOWN = 0, /* Unknown temperature trend */
29949e866e40b95795203f3ee46f44a197c946e4stevel TREND_RAPID_RISE = 5, /* Rapidly rising temperature */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Thresholds for temperature trend */
29949e866e40b95795203f3ee46f44a197c946e4stevel * Main structure for passing the calibrated and time averaged temperature
29949e866e40b95795203f3ee46f44a197c946e4stevel * values to user processes. This structure is copied out via the kstat
29949e866e40b95795203f3ee46f44a197c946e4stevel * mechanism.
29949e866e40b95795203f3ee46f44a197c946e4stevel#define TEMP_KSTAT_VERSION 3 /* version of temp_stats structure */
29949e866e40b95795203f3ee46f44a197c946e4stevel enum temp_state state; /* state of board temperature */
29949e866e40b95795203f3ee46f44a197c946e4stevel int shutdown_cnt; /* counter for overtemp shutdown */
29949e866e40b95795203f3ee46f44a197c946e4stevel enum temp_trend trend; /* temperature trend for board */
29949e866e40b95795203f3ee46f44a197c946e4stevel short override; /* override temperature for testing */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* The variable fhc_cpu_warning_temp_threshold is initialized to this value. */
29949e866e40b95795203f3ee46f44a197c946e4stevel * Fault list management.
29949e866e40b95795203f3ee46f44a197c946e4stevel * The following defines and enum definitions have been created to support
29949e866e40b95795203f3ee46f44a197c946e4stevel * the fault list (struct ft_list). These defines must match with the
29949e866e40b95795203f3ee46f44a197c946e4stevel * fault string table in fhc.c. If any faults are added, they must be
29949e866e40b95795203f3ee46f44a197c946e4stevel * added at the end of this list, and the table must be modified
29949e866e40b95795203f3ee46f44a197c946e4stevel * accordingly.
29949e866e40b95795203f3ee46f44a197c946e4stevel FT_INSUFFICIENT_POWER, /* System has insufficient power */
29949e866e40b95795203f3ee46f44a197c946e4stevel * This extern allows other drivers to use the ft_str_table if they
29949e866e40b95795203f3ee46f44a197c946e4stevel * have fhc specified as a depends_on driver.
29949e866e40b95795203f3ee46f44a197c946e4stevelextern char *ft_str_table[];
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Maximum length of string table entries */
29949e866e40b95795203f3ee46f44a197c946e4stevel * The fault list structure is a structure for holding information on
29949e866e40b95795203f3ee46f44a197c946e4stevel * kernel detected faults. The fault list structures are linked into
29949e866e40b95795203f3ee46f44a197c946e4stevel * a list and the list is protected by the ftlist_mutex. There are
29949e866e40b95795203f3ee46f44a197c946e4stevel * also several routines for manipulating the fault list.
29949e866e40b95795203f3ee46f44a197c946e4stevel int32_t pad; /* padding to replace old next pointer */
29949e866e40b95795203f3ee46f44a197c946e4stevel enum ft_class fclass; /* System or board class fault */
29949e866e40b95795203f3ee46f44a197c946e4stevel time32_t create_time; /* Time stamp at fault detection */
29949e866e40b95795203f3ee46f44a197c946e4stevel * Allow binary compatibility between ILP32 and LP64 by
29949e866e40b95795203f3ee46f44a197c946e4stevel * eliminating the next pointer and making ft_list a fixed size.
29949e866e40b95795203f3ee46f44a197c946e4stevel * The structure name "ft_list" remains unchanged for
29949e866e40b95795203f3ee46f44a197c946e4stevel * source compatibility of kstat applications.
29949e866e40b95795203f3ee46f44a197c946e4stevel * Board list management.
29949e866e40b95795203f3ee46f44a197c946e4stevel * Enumerated types for defining type of system and clock
29949e866e40b95795203f3ee46f44a197c946e4stevel * boards. It is used by both the kernel and user programs.
29949e866e40b95795203f3ee46f44a197c946e4stevel * Defined strings for comparing with OBP board-type property. If OBP ever
29949e866e40b95795203f3ee46f44a197c946e4stevel * changes the board-type properties, these string defines must be changed
29949e866e40b95795203f3ee46f44a197c946e4stevel * The following structures and union are needed because the bd_info
29949e866e40b95795203f3ee46f44a197c946e4stevel * structure describes all types of system boards.
29949e866e40b95795203f3ee46f44a197c946e4stevel * XXX - We cannot determine Spitfire rev from JTAG scan, so it is
29949e866e40b95795203f3ee46f44a197c946e4stevel * left blank for now. Future implementations might fill in this info.
29949e866e40b95795203f3ee46f44a197c946e4stevel int ec_compid; /* Ecache RAM ID, needed for cache size */
29949e866e40b95795203f3ee46f44a197c946e4stevel int cpu_detected; /* Something on the CPU JTAG ring. */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Defines for the FFB size field */
29949e866e40b95795203f3ee46f44a197c946e4stevel int ffb_size; /* not present, single or dbl buffered */
29949e866e40b95795203f3ee46f44a197c946e4stevel int ffb_size; /* not present, single or dbl buffered */
29949e866e40b95795203f3ee46f44a197c946e4stevel * board_state and bd_info are maintained for backward
29949e866e40b95795203f3ee46f44a197c946e4stevel * compatibility with prtdiag and others user programs that may rely
29949e866e40b95795203f3ee46f44a197c946e4stevel enum board_state state; /* current state of this board */
29949e866e40b95795203f3ee46f44a197c946e4stevel char prom_rev[64]; /* best guess as to what is needed */
29949e866e40b95795203f3ee46f44a197c946e4stevel * Config admin interface.
29949e866e40b95795203f3ee46f44a197c946e4stevel * Receptacle states.
29949e866e40b95795203f3ee46f44a197c946e4steveltypedef enum {
29949e866e40b95795203f3ee46f44a197c946e4stevel SYSC_CFGA_RSTATE_DISCONNECTED, /* DISCONNECTED state */
29949e866e40b95795203f3ee46f44a197c946e4stevel * Occupant states.
29949e866e40b95795203f3ee46f44a197c946e4steveltypedef enum {
29949e866e40b95795203f3ee46f44a197c946e4stevel SYSC_CFGA_OSTATE_UNCONFIGURED = 0, /* UNCONFIGURED state */
29949e866e40b95795203f3ee46f44a197c946e4steveltypedef enum {
29949e866e40b95795203f3ee46f44a197c946e4stevel * Error definitions for CFGADM platform library
29949e866e40b95795203f3ee46f44a197c946e4steveltypedef enum {
29949e866e40b95795203f3ee46f44a197c946e4stevel SYSC_ERR_PRECHARGE, /* not enough precharge for slot */
29949e866e40b95795203f3ee46f44a197c946e4stevel SYSC_ERR_HW_COMPAT, /* incompatible hardware found during dr */
29949e866e40b95795203f3ee46f44a197c946e4stevel SYSC_ERR_NON_DR_PROM, /* prom not support Dynamic Reconfiguration */
29949e866e40b95795203f3ee46f44a197c946e4stevel SYSC_ERR_CORE_RESOURCE, /* core resource cannot be removed */
29949e866e40b95795203f3ee46f44a197c946e4stevel SYSC_ERR_DR_INIT, /* error encountered in sysc_dr_init op */
29949e866e40b95795203f3ee46f44a197c946e4stevel SYSC_ERR_NDI_ATTACH, /* error encountered in NDI attach operations */
29949e866e40b95795203f3ee46f44a197c946e4stevel SYSC_ERR_NDI_DETACH, /* error encountered in NDI detach operations */
29949e866e40b95795203f3ee46f44a197c946e4stevel * Config admin structure.
29949e866e40b95795203f3ee46f44a197c946e4stevel /* generic representation of the attachment point below */
29949e866e40b95795203f3ee46f44a197c946e4stevel sysc_cfga_rstate_t rstate; /* current receptacle state */
29949e866e40b95795203f3ee46f44a197c946e4stevel sysc_cfga_ostate_t ostate; /* current occupant state */
29949e866e40b95795203f3ee46f44a197c946e4stevel sysc_cfga_cond_t condition; /* current board condition */
29949e866e40b95795203f3ee46f44a197c946e4stevel time32_t last_change; /* last state/condition change */
29949e866e40b95795203f3ee46f44a197c946e4stevel /* platform specific below */
29949e866e40b95795203f3ee46f44a197c946e4stevel char prom_rev[64]; /* best guess as to what is needed */
29949e866e40b95795203f3ee46f44a197c946e4stevel * Config admin command structure for SYSC_CFGA ioctls.
29949e866e40b95795203f3ee46f44a197c946e4stevel caddr32_t outputstr; /* output returned from ioctl */
29949e866e40b95795203f3ee46f44a197c946e4stevel * Sysctrl DR sequencer interface.
29949e866e40b95795203f3ee46f44a197c946e4stevel dev_info_t **dip_list; /* list of top dips for board */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYSC_DR_FHC 0x1 /* connect phase init (fhc) */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYSC_DR_DEVS 0x2 /* config phase init (devices) */
29949e866e40b95795203f3ee46f44a197c946e4stevel * Sysctrl event interface.
29949e866e40b95795203f3ee46f44a197c946e4stevel * sysctrl audit message events
29949e866e40b95795203f3ee46f44a197c946e4steveltypedef struct {
29949e866e40b95795203f3ee46f44a197c946e4stevel void (*update)(void *, sysc_cfga_stat_t *, sysc_evt_t);
29949e866e40b95795203f3ee46f44a197c946e4stevelvoid fhc_bd_sc_register(void f(void *, sysc_cfga_stat_t *, sysc_evt_t), void *);
29949e866e40b95795203f3ee46f44a197c946e4stevel * The board list structure is the central storage for the kernel's
29949e866e40b95795203f3ee46f44a197c946e4stevel * knowledge of normally booted and hotplugged boards.
29949e866e40b95795203f3ee46f44a197c946e4stevel struct fhc_soft_state *softsp; /* handle for DDI soft state */
29949e866e40b95795203f3ee46f44a197c946e4stevel void *dev_softsp; /* opaque pointer to device state */
29949e866e40b95795203f3ee46f44a197c946e4stevel struct kstat *ksp; /* pointer used in kstat destroy */
29949e866e40b95795203f3ee46f44a197c946e4stevel * Fhc_bd.c holds 2 resizable arrays of boards. First for clock
29949e866e40b95795203f3ee46f44a197c946e4stevel * boards under central and second for normally booted and
29949e866e40b95795203f3ee46f44a197c946e4stevel * hotplugged boards.
29949e866e40b95795203f3ee46f44a197c946e4stevel#define SYSC_OUTPUT_LEN MAXPATHLEN /* output str len */
29949e866e40b95795203f3ee46f44a197c946e4stevel * Board list management interface.
29949e866e40b95795203f3ee46f44a197c946e4stevelvoid fhc_bdlist_prime(int, int, int);
29949e866e40b95795203f3ee46f44a197c946e4stevelvoid fhc_bd_init(struct fhc_soft_state *, int, enum board_type);
29949e866e40b95795203f3ee46f44a197c946e4stevelvoid fhc_bd_env_set(int, void *);
29949e866e40b95795203f3ee46f44a197c946e4stevel * In order to indicate that we are in an environmental chamber, or
29949e866e40b95795203f3ee46f44a197c946e4stevel * oven, the test people will set the 'mfg-mode' property in the
29949e866e40b95795203f3ee46f44a197c946e4stevel * options node to 'chamber'. Therefore we have the following define.
29949e866e40b95795203f3ee46f44a197c946e4stevel * zs design for fhc has two zs' interrupting on same interrupt mondo
29949e866e40b95795203f3ee46f44a197c946e4stevel * This requires us to poll for zs and zs alone. The poll list has been
29949e866e40b95795203f3ee46f44a197c946e4stevel * defined as a fixed size for simplicity.
29949e866e40b95795203f3ee46f44a197c946e4stevel/* FHC Interrupt routine wrapper structure */
29949e866e40b95795203f3ee46f44a197c946e4stevel * The JTAG master command structure. It contains the address of the
29949e866e40b95795203f3ee46f44a197c946e4stevel * the JTAG controller on this system board. The controller can only
29949e866e40b95795203f3ee46f44a197c946e4stevel * be used if this FHC holds the JTAG master signal. This is checked
29949e866e40b95795203f3ee46f44a197c946e4stevel * by reading the JTAG control register on this FHC.
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Functions exported to manage the fault list */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* memloc's are protected under the bdlist lock */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Functions used to manage memory 'segments' */
29949e866e40b95795203f3ee46f44a197c946e4stevel#define FHC_MEMLOC_MAX (0x10000000000ull >> FHC_MEMLOC_SHIFT)
29949e866e40b95795203f3ee46f44a197c946e4stevelvoid fhc_add_memloc(int board, uint64_t pa, uint_t size);
29949e866e40b95795203f3ee46f44a197c946e4stevel/* Structures used in the driver to manage the hardware */
29949e866e40b95795203f3ee46f44a197c946e4stevel struct bd_list *list; /* pointer to board list entry */
29949e866e40b95795203f3ee46f44a197c946e4stevel int is_central; /* A central space instance of FHC */
29949e866e40b95795203f3ee46f44a197c946e4stevel volatile uint_t *rctrl; /* FHC Reset Control and Status */
29949e866e40b95795203f3ee46f44a197c946e4stevel volatile uint_t *bsr; /* FHC Board Status register */
29949e866e40b95795203f3ee46f44a197c946e4stevel volatile uint_t *jtag_ctrl; /* JTAG Control register */
29949e866e40b95795203f3ee46f44a197c946e4stevel uchar_t spurious_zs_cntr; /* Spurious counter for zs devices */
29949e866e40b95795203f3ee46f44a197c946e4stevel /* this lock protects the following data */
29949e866e40b95795203f3ee46f44a197c946e4stevel /* ! non interrupt use only ! */
29949e866e40b95795203f3ee46f44a197c946e4stevel /* The JTAG master structure has internal locking */
29949e866e40b95795203f3ee46f44a197c946e4stevel /* the pointer to the kstat is stored for deletion upon detach */
29949e866e40b95795203f3ee46f44a197c946e4stevel * Function shared with child drivers which require fhc
29949e866e40b95795203f3ee46f44a197c946e4stevel * support. They gain access to this function through the use of the
29949e866e40b95795203f3ee46f44a197c946e4stevel * _depends_on variable.
29949e866e40b95795203f3ee46f44a197c946e4stevelvoid update_temp(dev_info_t *pdip, struct temp_stats *envstat, uchar_t value);
29949e866e40b95795203f3ee46f44a197c946e4stevelextern int fhc_board_poweroffcpus(int board, char *errbuf, int cpu_flags);
29949e866e40b95795203f3ee46f44a197c946e4stevel/* FHC interrupt specification */
29949e866e40b95795203f3ee46f44a197c946e4stevel/* kstat structure used by fhc to pass data to user programs. */
29949e866e40b95795203f3ee46f44a197c946e4stevel struct kstat_named csr; /* FHC Control and Status Register */
29949e866e40b95795203f3ee46f44a197c946e4stevel struct kstat_named bsr; /* FHC Board Status Register */
29949e866e40b95795203f3ee46f44a197c946e4stevel#endif /* _KERNEL */
29949e866e40b95795203f3ee46f44a197c946e4stevel#endif /* _ASM */
29949e866e40b95795203f3ee46f44a197c946e4stevel#endif /* _SYS_FHC_H */