scat_dcd.h revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 1999-2003 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SCAT_DCD_H
#define _SCAT_DCD_H
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* This file contains definitions of the structures gdcd_t and ldcd_t,
* Global and Local Domain Configuration Descriptors and the various
* substructures they contain.
* The gdcd is the information handed off to OBP and the OS by POST
* in the "golden" I/O SRAM of a domain in Sun Fire 15000 systems.
* The ldcd contains information about the two ports local to each
* sram, kept in that local sram, to support DR operations.
*/
#include <post/scat_const.h>
#include <post/scat_asicbrd_types.h>
#ifdef __cplusplus
extern "C" {
#endif
#define DCD_VERSION 4
#define PMBANKS_PER_PORT 2
#define LMBANKS_PER_PMBANK 2
#define IOBUS_PER_PORT 2
#define DIMMS_PER_PORT 8
#define DIMMS_PER_PMBANK 4
#define ECDIMMS_PER_PORT 2
/*
* This is intended to handle Jubatus8X - up to 8 CPU cores
* within one Safari port.
*/
#define SAF_AGENT_PER_PORT 8
/*
* The most significant element of the otherwise unused
* prd_t.prd_wic_links[LINKS_PER_PORT] in processor ports is
* reserved for use by DR to save the prd_prsv of the port
* while that is temporarily marked RSV_UNCONFIG when the
* processor is borrowed for I/O cage testing for DR.
* It is expected that .prd_wic_links[PRD_LINK_IX_HOLD_CPUPORT_PRSV]
* will be restored to RSV_UNDEFINED when the prd_prsv is
* restored to its original value. It would be a Good Thing to
* check that prd_prsv is not ever being set to RSV_UNDEFINED;
* it's probably wrong to restore it to other than RSV_GOOD().
*/
/*
* There are four Address Decode Registers, 0 - 3, one for each
* logical bank. ADR 0 and 2 control the logical banks in
* physical bank 0; ADR 1 and 3 control the logical banks in
* physical bank 1.
*/
/* ======================================================== */
/*
* RSV stands for Resource Status Value.
* These are the values used in all cases where the status of
* a resource is maintained in a byte element of a structure.
* These are ordered in terms of preserving interesting information
* in POST displays where all configurations are displayed in a
* single value. The highest value for a resource over all
* configurations is shown.
* Of course, this is just for help to engineers/technicians in
* understanding what happened; for the most part, everything
* except "GOOD" is just different flavors of "BAD".
* This is not an enum because they need to fit in a byte.
*/
/* Always subject to more... */
/*
* Odd proc of a good Lockstep pair. Valid only for prd_prsv for
* processor ports.
*/
#define RSV_LOCKSTEP 0xD
/*
* This will be used instead of RSV_MISS when an hsPCI
* cassette is present but it contains no PCI adapter.
* Intended to be used only for prd_t.prd_iocard_rsv[][]
*/
/*
* This definition of Good depends on context.
* Some customers of this status may want to use only PASS.
*/
/* ============================================================ */
/* Port Resource Descriptor - PRD */
typedef struct {
/*
* For ports with memory, the address decode register
* for each bank, and the address control register.
*/
/* DOUBLEWORD */
/* to interconnect speed */
/* memory configuration state */
/* DOUBLEWORD */
/*
* This is intended to handle Jubatus2X - 8X.
* For all other cases, expect that prd_agent[0] = prd_prsv,
* and prd_agent[7:1] = RSV_UNDEFINED.
* For JubatusnX, it conveys the status of the
* n core processors.
*/
/* DOUBLEWORD */
/* for ports that have memory */
/* bank rsv */
/*
* If a physical bank has two logical
* banks, they are always the same size.
*/
/* DOUBLEWORD */
/* for ports with IO buses */
/*
* Currently, only 1 adapter is on each bus and index
* zero is used for that. Index 1 is reserved.
* The remaining 2 are used to support in-kernel-probing,
* to avoid board specific hooks.
* They only exist on bus 1 of Schizo 0 on the board.
*/
#define IOBOARD_BBCRIO_PORT 0
#define IOBOARD_BBCRIO_BUS 1
#define IOCARD_RSV_SBBC_INDEX 2
#define IOCARD_RSV_RIO_INDEX 3
/* DOUBLEWORD */
/* For ports with WCI links, status of each link */
/* DOUBLEWORD */
/*
* Status for dimms [1:0][3:0].
* This contains at most only probing information.
* Testing is done on logical banks, so results are
* not representable at the dimm level, since each
* dimm contains part of two logical banks.
*
* Also, probing is expensive in time, so it is
* skipped if the results would not affect available
* resources.
* Example: if dimm 0 of a pbank is missing, the other
* three dimms are ignored and will be RSV_UNKNOWN.
*/
/* DOUBLEWORD */
/* status for ecache dimms 0..1 */
/* DOUBLEWORD */
/* DOUBLEWORD */
} prd_t;
/* prd_mem_config_state manifest constants */
/* Types of Safari ports. Not an enum so it fits in a byte. */
#define SAFPTYPE_NULL 0
#define SAFPTYPE_CPU 1
#define SAFPTYPE_sPCI 2
#define SAFPTYPE_cPCI 3
#define SAFPTYPE_WCI 4
#define SAFPTYPE_PCIX 5
#define SAFPTYPE_MAX SAFPTYPE_PCIX
#define SAFTYPE_PCI(type) \
/* ======================================================== */
/* Local and Global Domain Configuration Descriptors LDCD & GDCD */
/* Enumeration of process types for xdcd.h.dcd_lmod_type */
typedef enum {
DCDLMT_OTHER, /* Something not otherwise in this enum */
DCDLMT_POST_BOOT, /* POST at initial domain creation */
DCDLMT_POST_DR, /* POST for some sort of DR case */
DCDLMT_OBP, /* Domain Open Boot */
DCDLMT_OS, /* Domain Solaris */
DCDLMT_DR_SMS, /* DR process running on SSC */
DCDLMT_DR_DOMAIN, /* DR process running on domain */
DCDLMT_OTHER_SMS, /* Non-DR process running on SSC */
DCDLMT_COUNT /* Array size for strings, etc. */
/* dcd substructure for status of L1 boards in each slot */
typedef struct {
/*
* The cdc information is rightfully
* only relevant to the EXB and the
* slot 0 board of that EXB. But it
* needs to stay with that slot 0
* board over DR operations, so
* it goes here.
* It should be ignored for slot 1
* boards.
*/
/* DOUBLEWORD */
/*
* So Starcat software that doesn't
* have knowledge of the CPU sram
* TOC format can find the LDCD in
* CPU srams.
*/
/* DOUBLEWORD */
/*
* When this flag is set, all CPUs on this L1 board should be
* configured with a NULL Local Physical Address (LPA) range in
* their Safari Config Registers.
* This flag can be ignored for boards with no processors.
*/
#define L1SSFLG_THIS_L1_NULL_PROC_LPA (1 << 0)
/* dcd substructure for memory chunk list. */
typedef struct {
} mem_chunk_t;
typedef struct {
#define MAX_EXP_MEM_CHUNKS (S0_LPORT_COUNT * \
typedef struct {
typedef struct {
/* originally created this domain */
/* or POSTed this board. */
/* DOUBLEWORD */
/* by POST. To be backward compatible */
/* in ILD32, uint64_t is used instead */
/* of time_t. */
/* this structure. */
/* of this structure. If the last */
/* modifier has no PID, set to 0. */
/* this structure. See above. */
/* DOUBLEWORD */
/* this structure has been modified. */
/* Set to 0 by original POST. */
/* for most recent boot or test. */
/* DOUBLEWORD */
/* DOUBLEWORD */
} dcd_header_t;
/*
* This flag is only for use in LDCDs. It is set when this
* board is part of a domain and the local DCD is considered
* only a secondary copy of the information in the GDCD.
* We do not keep the GDCD location here, since that would
* impose extra work on DR when the golden IOSRAM board detaches.
* POST will set this in all LDCDs in a newly booted domain.
*/
#define DCDFLAG_IN_DOMAIN (1u << 0)
/*
* This flag is only for use in LDCDs. It is set when this
* board was called for hpost -H (h.dcd_lmod_type is DCDLMT_POST_DR)
* and no testing was required. All that was done was clearing.
*/
/* POST inititalizes dcd_testcage_mbyte_PA to this value */
/*
* zero (0) in dcd_testcage_log2_mbytes has the special meaning
* that no testcage memory is to be allocated.
* zero (0) in dcd_testcage_log2_mbytes_align is a real
* alignment of 1MB.
*/
#define DCD_DR_TESTCAGE_DISABLED (0) /* zero size cage */
#define DCD_DR_TESTCAGE_LOG2_1MB_ALIGN (0) /* 2^0 = 1 for */
/*
* The remainder of these constants can be used for
* either dcd_testcage_* variable and indicate the
* value shown.
*/
/* Global DCD - exists only in golden I/O sram */
typedef struct {
dcd_header_t h;
/* DOUBLEWORD */
/* DOUBLEWORD */
/*
* Specification of the required size and alignment of
* the DR testcage memory used during POST -H testcage runs.
* The formula is bytes = (1 << (log2_value + 20)).
*/
/* DOUBLEWORD */
/*
* Specification of the DR testcage memory base physical addr.
* This is initialized to DCD_TESTCAGE_PA_INIT by POST
* and set by setkeyswitch when it determines the location of
* the testcage. The formula is PA = (mbyte_PA << 20).
*/
/* DOUBLEWORD */
/* Information on the L1 boards in each slot: */
/* DOUBLEWORD */
/*
* Information on 108 Safari ports.
* See scat_const.h for macros that will help in computing
* indexes into this array, particularly "PWE" and "PFP".
*/
/* DOUBLEWORD */
/*
* memory chunk list for the domain; max 288 chunks.
* This is the worst case scenario where there is no
* interleaving and no re-configuration of the memory address
* decode registers to make board memory contiguous.
* This uses 288 * 16bytes = 4608KB.
*/
} gdcd_t;
/* Local DCD - exists in every I/O, CPU, and WCI sram */
typedef struct {
dcd_header_t h;
/* DOUBLEWORD */
/* Information on the L1 board in this slot: */
/* DOUBLEWORD */
/* Information on 2 Safari ports: */
/* DOUBLEWORD */
/* memory chunk list for this exp; max 16 chunks */
} ldcd_t;
#ifdef __cplusplus
}
#endif
#endif /* !_SCAT_DCD_H */