03831d35f7499c87d51205817c93e9a8d42c4baestevel * CDDL HEADER START
03831d35f7499c87d51205817c93e9a8d42c4baestevel * The contents of this file are subject to the terms of the
1e2e7a75ddb1eedcefa449ce98fd5862749b72eehuah * Common Development and Distribution License (the "License").
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03831d35f7499c87d51205817c93e9a8d42c4baestevel * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
03831d35f7499c87d51205817c93e9a8d42c4baestevel * See the License for the specific language governing permissions
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03831d35f7499c87d51205817c93e9a8d42c4baestevel * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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03831d35f7499c87d51205817c93e9a8d42c4baestevel * CDDL HEADER END
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * Use is subject to license terms.
03831d35f7499c87d51205817c93e9a8d42c4baestevel * This file is through cpp before being used as
03831d35f7499c87d51205817c93e9a8d42c4baestevel * an inline. It contains support routines used
03831d35f7499c87d51205817c93e9a8d42c4baestevel * only by DR.
03831d35f7499c87d51205817c93e9a8d42c4baestevel#if defined(lint)
03831d35f7499c87d51205817c93e9a8d42c4baestevel#endif /* lint */
03831d35f7499c87d51205817c93e9a8d42c4baestevel#if defined(lint)
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
07d06da50d310a325b457d6330165aebab1e0064Surya Prakkidrmach_shutdown_asm(uint64_t estack, uint64_t flushaddr,
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_rename(uint64_t *script, uint_t *err, uint64_t *id)
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_rename_wait(uint64_t not_used_0, uint64_t not_used_1)
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_rename_done(uint64_t not_used_0, uint64_t not_used_1)
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_rename_abort(uint64_t not_used_0, uint64_t not_used_1)
03831d35f7499c87d51205817c93e9a8d42c4baestevel/*ARGSUSED*/
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0x0ull);
03831d35f7499c87d51205817c93e9a8d42c4baestevel/* ARGSUSED */
03831d35f7499c87d51205817c93e9a8d42c4baestevel return (0x0);
03831d35f7499c87d51205817c93e9a8d42c4baestevel#else /* lint */
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! This code is run at TL > 0, being exec'd via a cross trap.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! While running at trap level > 0, all memory accesses are
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! performed using NUCLEUS context, which is always 0.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Since the cross trap handler does not force PRIMARY context
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! to be zero, the following casxa instruction must specify
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! NUCLEUS ASI.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! This ASI must be specified explicitly (via casxa), rather
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! than using casx. This is because of the fact that the
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! default casx specifies ASI_PRIMARY, which if non-zero, can
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! prevent the cpu from translating the address, leading to panic
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! on bad trap following repetitive dtlb misses. This behavior
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! was encountered on MCPUs when using casx instruction.
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define ATOMIC_ADD_LONG(label, simm, reg1, reg2, reg3) \
03831d35f7499c87d51205817c93e9a8d42c4baestevel set label, reg1 ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel ldx [reg1], reg2 ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel add reg2, simm, reg3 ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel casxa [reg1]ASI_N, reg2, reg3 ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmp reg2, reg3 ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel bne,a,pn %xcc, 1b ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel ldx [reg1], reg2
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define HERE(reg1, simm, reg2) \
03831d35f7499c87d51205817c93e9a8d42c4baestevel rdpr %tick, reg2 ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel stx reg2, [reg1 + simm]
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Returns processor icache size and linesize in reg1 and
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! reg2, respectively.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Panther has a larger icache compared to Cheetahplus and
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define GET_ICACHE_PARAMS(reg1, reg2) \
03831d35f7499c87d51205817c93e9a8d42c4baestevel GET_CPU_IMPL(reg1) ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmp reg1, PANTHER_IMPL ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel bne %xcc, 1f ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel set PN_ICACHE_SIZE, reg1 ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel set PN_ICACHE_LSIZE, reg2 ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel set CH_ICACHE_SIZE, reg1 ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel set CH_ICACHE_LSIZE, reg2 ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define DRMACH_MCU_IDLE_READS 3
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Macro to check if a Panther MC is idle. The EMU Activity
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Status register is first read to clear the MCU status bit.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! The MCU status is then checked DRMACH_MCU_IDLE_READS times
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! to verify the MCU is indeed idle. A single non-idle status
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! will fail the idle check. This could be made more lenient
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! by adding a retry loop.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! addr: Panther EMU Activity Status register read address.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Assumed to be 0x18 for local ASI access or else
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! FIREPLANE_ADDRESS_REG + 0x400050 for PIO access.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! 0 is returned in this register if MCU is idle and
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! queues are empty. Otherwise, -1 is returned in this
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! register.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! asi: Immediate asi value. Assumed to be ASI_SAFARI_CONFIG
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! for local ASI or ASI_IO for PIO access.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! scr1: Scratch
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! scr2: Scratch
03831d35f7499c87d51205817c93e9a8d42c4baestevel#define CHECK_MCU_IDLE(addr, asi, scr1, scr2) \
03831d35f7499c87d51205817c93e9a8d42c4baestevel ldxa [addr]asi, %g0 ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel clr scr2 ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel btst MCU_ACT_STATUS, scr1 ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel bne,a 2f ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel sub %g0, 1, addr ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel inc scr2 ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmp scr2, DRMACH_MCU_IDLE_READS ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel ble,a 0b ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel ldxa [addr]asi, scr1 ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel clr addr ;\
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! drmach_shutdown_asm
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! %o0 = stack pointer
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! %o1 = ecache flush address (ignored if cheetah+ processor)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! %o2 = ecache size
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! %o3 = ecache line size
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! %o4 = phys addr of byte to clear when finished
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Stores a zero at [%o4]ASI_MEM when the processor
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! is ready to be removed from domain coherency.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ENTRY_NP(drmach_shutdown_asm)
03831d35f7499c87d51205817c93e9a8d42c4baestevel membar #LoadStore ! parsley.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Calculate pointer to data area. Determine size of
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! drmach_shutdown_asm, add to base address and align
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! to next 16 byte boundary. Leave result in %g6.
03831d35f7499c87d51205817c93e9a8d42c4baestevel set drmach_shutdown_asm_end, %g6
03831d35f7499c87d51205817c93e9a8d42c4baestevel set drmach_shutdown_asm, %g1
03831d35f7499c87d51205817c93e9a8d42c4baestevel set drmach_cpu_sram_va, %g2
03831d35f7499c87d51205817c93e9a8d42c4baestevel ldx [%g2], %g2
03831d35f7499c87d51205817c93e9a8d42c4baestevel sub %g6, %g1, %g6
03831d35f7499c87d51205817c93e9a8d42c4baestevel add %g6, %g2, %g6
03831d35f7499c87d51205817c93e9a8d42c4baestevel add %g6, 15, %g6
03831d35f7499c87d51205817c93e9a8d42c4baestevel andn %g6, 15, %g6
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Save parameters
03831d35f7499c87d51205817c93e9a8d42c4baestevel stx %o0, [%g6 + 0] ! save stack pointer
03831d35f7499c87d51205817c93e9a8d42c4baestevel stx %o1, [%g6 + 24] ! save E$ flush PA
03831d35f7499c87d51205817c93e9a8d42c4baestevel st %o2, [%g6 + 32] ! save E$ size
03831d35f7499c87d51205817c93e9a8d42c4baestevel st %o3, [%g6 + 36] ! save E$ linesize
03831d35f7499c87d51205817c93e9a8d42c4baestevel stx %o4, [%g6 + 40] ! save phys addr of signal byte
03831d35f7499c87d51205817c93e9a8d42c4baestevel set dcache_size, %g1
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g1], %g1
03831d35f7499c87d51205817c93e9a8d42c4baestevel st %g1, [%g6 + 8] ! save dcache_size
03831d35f7499c87d51205817c93e9a8d42c4baestevel set dcache_linesize, %g1
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g1], %g1
03831d35f7499c87d51205817c93e9a8d42c4baestevel st %g1, [%g6 + 12] ! save dcache_linesize
03831d35f7499c87d51205817c93e9a8d42c4baestevel GET_ICACHE_PARAMS(%g1, %g2)
03831d35f7499c87d51205817c93e9a8d42c4baestevel st %g1, [%g6 + 16] ! save icache_size
03831d35f7499c87d51205817c93e9a8d42c4baestevel st %g2, [%g6 + 20] ! save icache_linesize
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Flushes all active windows except the current one.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Can cause spill traps to occur.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Make sure all asynchronous processing is complete.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Note: has no implications on pending bus transactions.
03831d35f7499c87d51205817c93e9a8d42c4baestevel membar #Sync
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Move stack. Algorithm copied from t0stacktop setup of
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Replaces SWITCH_STACK() macro used in Starfire DR.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ldx [%g6 + 0], %g1
03831d35f7499c87d51205817c93e9a8d42c4baestevel sub %g1, SA(KFPUSIZE+GSR_SIZE), %g2
03831d35f7499c87d51205817c93e9a8d42c4baestevel and %g2, 0x3f, %g3
03831d35f7499c87d51205817c93e9a8d42c4baestevel sub %g2, %g3, %o2
03831d35f7499c87d51205817c93e9a8d42c4baestevel sub %o2, SA(MPCBSIZE) + STACK_BIAS, %sp
03831d35f7499c87d51205817c93e9a8d42c4baestevel stx %sp, [%g6 + 48] ! for debug
03831d35f7499c87d51205817c93e9a8d42c4baestevel HERE(%g6, 128, %g1) ! initialization complete (for debug)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Panther needs to flush the L2 cache before the L3
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! cache is flushed by the ecache flushall macro.
03831d35f7499c87d51205817c93e9a8d42c4baestevel PN_L2_FLUSHALL(%g1, %g2, %g3)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Flush E$. The purpose of this flush is to rid the E$ of
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! lines in states O or Os. Implicitly flushes W$.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ldx [%g6 + 24], %g1 ! *ecache_flushaddr
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g6 + 32], %g2 ! ecache_size
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g6 + 36], %g3 ! ecache_linesize
03831d35f7499c87d51205817c93e9a8d42c4baestevel ECACHE_FLUSHALL(%g2, %g3, %g1, %g4)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Since the bus sync list read below does not guarantee
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! transaction completion on Panther domains, as an
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! optimization Panther skips the read and subsequent
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! E$ flush.
03831d35f7499c87d51205817c93e9a8d42c4baestevel GET_CPU_IMPL(%g1)
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmp %g1, PANTHER_IMPL
03831d35f7499c87d51205817c93e9a8d42c4baestevel be %xcc, drmach_shutdown_ecache_flushed
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Ensure all outstanding writebacks have retired. Following this
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! sync, all writes must be strictly managed.
03831d35f7499c87d51205817c93e9a8d42c4baestevel set drmach_bus_sync_list, %g1
03831d35f7499c87d51205817c93e9a8d42c4baestevel BUS_SYNC(%g1, %g2)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Flush E$ again to victimize references to drmach_bus_sync_list.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ldx [%g6 + 24], %g1 ! *ecache_flushaddr
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g6 + 32], %g2 ! ecache_size
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g6 + 36], %g3 ! ecache_linesize
03831d35f7499c87d51205817c93e9a8d42c4baestevel ECACHE_FLUSHALL(%g2, %g3, %g1, %g4)
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_shutdown_ecache_flushed:
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g6 + 8], %g1 ! flush dcache
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g6 + 12], %g2
03831d35f7499c87d51205817c93e9a8d42c4baestevel CH_DCACHE_FLUSHALL(%g1, %g2, %g3)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g6 + 16], %g1 ! flush icache
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g6 + 20], %g2
03831d35f7499c87d51205817c93e9a8d42c4baestevel CH_ICACHE_FLUSHALL(%g1, %g2, %g3, %g4)
03831d35f7499c87d51205817c93e9a8d42c4baestevel PCACHE_FLUSHALL(%g1, %g2, %g3) ! flush pcache (no parameters)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Flush all unlocked dtlb and itlb entries.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Replaces TLB_FLUSH_UNLOCKED macro used in Starfire DR.
03831d35f7499c87d51205817c93e9a8d42c4baestevel sethi %hi(FLUSH_ADDR), %g1
03831d35f7499c87d51205817c93e9a8d42c4baestevel set DEMAP_ALL_TYPE, %g2
03831d35f7499c87d51205817c93e9a8d42c4baestevel stxa %g0, [%g2]ASI_DTLB_DEMAP
03831d35f7499c87d51205817c93e9a8d42c4baestevel stxa %g0, [%g2]ASI_ITLB_DEMAP
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Zero LPA by clearing CBASE and CBND. Following
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! this, all transactions to cachable address space
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! will be of the remote flavor.
03831d35f7499c87d51205817c93e9a8d42c4baestevel SET_NULL_LPA(%g1, %g2)
03831d35f7499c87d51205817c93e9a8d42c4baestevel HERE(%g6, 136, %g1) ! preparation complete (for debug)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Clear byte to signal finished.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! NOTE: This store will allocate in the E$. It is
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! vitally important that this line is demoted to
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! state I before removing this processor from the
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! coherency. The demotion is ensured by a synchronous
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! "steal back" that takes place in drmach_cpu_poweroff.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ldx [%g6 + 40], %g1
03831d35f7499c87d51205817c93e9a8d42c4baestevel stba %g0, [%g1]ASI_MEM
03831d35f7499c87d51205817c93e9a8d42c4baestevel HERE(%g6, 144, %g1) ! spin indicator (for debug)
03831d35f7499c87d51205817c93e9a8d42c4baestevel .asciz "drmach_shutdown_asm" ! for debug
03831d35f7499c87d51205817c93e9a8d42c4baestevel .global drmach_shutdown_asm_end
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_shutdown_asm_end:
03831d35f7499c87d51205817c93e9a8d42c4baestevel SET_SIZE(drmach_shutdown_asm)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! lddsafconfig
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Configuration Register.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ENTRY(lddsafconfig)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ldxa [%g0]ASI_SAFARI_CONFIG, %o0
03831d35f7499c87d51205817c93e9a8d42c4baestevel SET_SIZE(lddsafconfig)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! drmach_rename
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! %o0 pointer to register address/value compound list
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! %o1 address for setting error code if rename did not
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! complete. Unmodified if no error.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! %o2 address for returning opaque memory controller id
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! in case of error. Unmodified if no error.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Global drmach_xt_mb[cpuid] is expected to be the new LPA.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! [%o1] = 1 if failed to idle memory controller, otherwise unmodified.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! [%o2] = id of failed memory controller, otherwise unmodified.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Perform HW register reprogramming. This is the "rename" step for
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! the copy-rename process. drmach_rename is copied to a cpu's sram
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! followed by register address/value pairs -- the text and data are
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! sourced from the sram while drmach_rename is executed.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! The parameter is assumed to point to a concatenation of six
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! zero-terminated lists located in non-cachable storage. The assumed
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! 1) a copy of drmach_bus_sync_list. A list of PA for each
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! active memory bank in the domain. Used to infer the
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! the completion of all pending coherent transactions
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! does not implement read bypass. This is true of Cheetah,
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Cheetah+, and Jaguar processors. Panther does support
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! read bypass, so for Panther MCs with read-bypass-write
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! enabled, the read is issued but it does not guarantee
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! 2) address/id pair for the local Panther EMU Activity Status
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Register of this processor. The register address is assumed
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! to be a VA which is polled via ASI_SAFARI_CONFIG until the
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! MC queues are empty. The id is an opaque identifier which
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! must be returned along with an error code if the MCU status
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! does not go idle. See the parameter description above.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! This section will be empty if this processor is not a Panther.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Both the address and id are assumed to be 64 bit values.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! 3) address/id pairs for non-local Panther EMU Activity Status
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Registers on other source and target processors. The register
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! address is assumed to be a PIO address which is polled via
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! ASI_IO to drain/idle the MCs on other Panther procs. The
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! id is an opaque identifier which must be returned along with
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! an error code if a MC fails to go idle. This section will
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! empty if there are no non-local Panther processors on the
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! source and target expanders. Both the address and id are
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! 4) address/value pairs for the Memory Address Decoder
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! register of this processor. The register address is
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! address and value elements are assumed to 64 bit values.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! 5) address/value pairs for any 64 bit register accessible
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! via ASI_IO. The address and value fields are assumed to
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! This list is typically used for reprogramming the Memory
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Address Decoder Register of other cpus and for reprogram-
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! ming the Safari Configuration Register of I/O controllers.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! 6) address/value pairs for any 32 bit register accessible
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! via ASI_IO. The address element is assumed to be a 64 bit
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! value. The value element is assumed to be a 64 bit word
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! This list typically contains address/value pairs for
03831d35f7499c87d51205817c93e9a8d42c4baestevel SET_NULL_LPA(%o1, %o2) ! prep for cachable transactions
03831d35f7499c87d51205817c93e9a8d42c4baestevel ldxa [%o1]ASI_MC_DECODE, %g0 ! read back to insure written
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! drmach_rename_wait is a cross-trap function used to move a
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! cpu's execution out of coherent space while a copy-rename
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! operation is in progress.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! In each CPU SRAM exists an area (16KB on Cheetah+ boards,
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! 32KB on Jaguar/Panther boards) reserved for DR. This area is
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! logically divided by DR into 8KB pages, one page per CPU (or
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! core) in a port pair. (Two Safari ports share HW resources on
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! a CPU/MEM board. These are referred to as a port pair.)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! This routine begins by mapping the appropriate SRAM page,
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! transferring the machine code (between the labels
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! drmach_rename_wait_asm and drmach_rename_wait_asm_end), then
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! jumping to SRAM. After returning from SRAM, the page is
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! demapped before the cross-call is exited (sic).
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! The machine code flushes all caches, waits for a special
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! interrupt vector, then updates the processor's LPA and
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! The special interrupt vector is assumed to be a cross-call to
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! drmach_rename_done sent by the master processor upon completing
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! the copy-rename operation. The interrupt is received and discarded;
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! The cross-call to drmach_rename_done is never executed. Instead
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! the Interrupt Receive Status Register is employed, temporarily,
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! as a semaphore. This avoids unwanted bus traffic during the critical
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! copy drmach_rename_wait_asm block to SRAM. Preserve entry
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! point in %g1. After the code has been copied, align %g6
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! (the destination pointer) to the next highest 16 byte
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! boundary. This will define the start of the data area.
03831d35f7499c87d51205817c93e9a8d42c4baestevel set drmach_cpu_sram_va, %g1 ! vtab_flushpage_tl1(drmach_cpu_sram_va,
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! the following code is copied to a cpu's sram and executed
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! from there.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! %g5 is cpuid
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! %g6 is data area (follows text)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! %g7 is link address back to caller
03831d35f7499c87d51205817c93e9a8d42c4baestevel st %g5, [%g6 + 4] ! save cpuid (for debug)
03831d35f7499c87d51205817c93e9a8d42c4baestevel set dcache_size, %g1
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g1], %g1
03831d35f7499c87d51205817c93e9a8d42c4baestevel st %g1, [%g6 + 8] ! save dcache_size
03831d35f7499c87d51205817c93e9a8d42c4baestevel set dcache_linesize, %g1
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g1], %g1
03831d35f7499c87d51205817c93e9a8d42c4baestevel st %g1, [%g6 + 12] ! save dcache_linesize
03831d35f7499c87d51205817c93e9a8d42c4baestevel GET_ICACHE_PARAMS(%g1, %g2)
03831d35f7499c87d51205817c93e9a8d42c4baestevel st %g1, [%g6 + 16] ! save icache_size
03831d35f7499c87d51205817c93e9a8d42c4baestevel st %g2, [%g6 + 20] ! save icache_linesize
03831d35f7499c87d51205817c93e9a8d42c4baestevel set drmach_iocage_paddr, %g1
03831d35f7499c87d51205817c93e9a8d42c4baestevel ldx [%g1], %g1
03831d35f7499c87d51205817c93e9a8d42c4baestevel stx %g1, [%g6 + 24] ! save *ecache_flushadr
03831d35f7499c87d51205817c93e9a8d42c4baestevel mulx %g5, CPU_NODE_SIZE, %g1 ! %g4 = &cpunodes[cpuid]
03831d35f7499c87d51205817c93e9a8d42c4baestevel set cpunodes, %g4
03831d35f7499c87d51205817c93e9a8d42c4baestevel add %g4, %g1, %g4
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g4 + ECACHE_SIZE], %g1
03831d35f7499c87d51205817c93e9a8d42c4baestevel st %g1, [%g6 + 32] ! save ecache_size
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g4 + ECACHE_LINESIZE], %g1
03831d35f7499c87d51205817c93e9a8d42c4baestevel st %g1, [%g6 + 36] ! save ecache_linesize
03831d35f7499c87d51205817c93e9a8d42c4baestevel LOAD_MB(%g5, %g1, %g2) ! save mailbox data
03831d35f7499c87d51205817c93e9a8d42c4baestevel stb %g1, [%g6 + 40]
03831d35f7499c87d51205817c93e9a8d42c4baestevel membar #Sync ! Complete any pending processing.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Flush E$. The purpose of this flush is to rid the E$ of
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! lines in states O or Os. Implicitly flushes W$.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! NOTE: Reading the bus sync list and r/w ops on drmach_xt_ready
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! will disturb the E$. The lines of the bus sync list will be
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! in state S. The line containing drmach_xt_ready will be in
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! state O. Before proceeding with the copy-rename, the master
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! processor will "steal back" the drmach_xt_ready (sic) line.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! This will demote the state of the line in E$ to I.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! However, the lines containing the bus sync list must be
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! victimized before returning to the OS. This is vital because
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! following copy-rename the corresponding lines in the new home
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! memory will be in state gM. The resulting S,gM state pair is
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! invalid and does represent a loss of coherency. Flushing the
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! E$ after the bus sync list is read will be sufficient to
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! avoid the invalid condition.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! For Panther, there is redundancy as both cores flush the shared
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! L2 and L3 caches. As an optimization, only one core could do the
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! flush of the shared caches, however care must be taken that the
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! sibling core does not install owned lines once the flush begins.
03831d35f7499c87d51205817c93e9a8d42c4baestevel PN_L2_FLUSHALL(%g1, %g2, %g3)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ldx [%g6 + 24], %g1 ! *ecache_flushaddr
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g6 + 32], %g2 ! ecache_size
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g6 + 36], %g3 ! ecache_linesize
03831d35f7499c87d51205817c93e9a8d42c4baestevel ECACHE_FLUSHALL(%g2, %g3, %g1, %g4)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Make sure all outstanding transactions for this processor
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! have retired. See E$ note above.
03831d35f7499c87d51205817c93e9a8d42c4baestevel set drmach_bus_sync_list, %g1
03831d35f7499c87d51205817c93e9a8d42c4baestevel BUS_SYNC(%g1, %g2)
03831d35f7499c87d51205817c93e9a8d42c4baestevel HERE(%g6, 128, %g4) ! preparation complete (for debug)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Signal this processor is ready for rename operation to begin.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! See E$ note above.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ATOMIC_ADD_LONG(drmach_xt_ready, 1, %g2, %g3, %g4)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Loop on IRSR waiting for interrupt. The expected interrupt
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! is a cross-trap to drmach_wait_done. It is sent by the master
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! processor when the copy-rename operation is complete. The
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! received cross-trap is used only as a signal. It is not executed.
03831d35f7499c87d51205817c93e9a8d42c4baestevel HERE(%g6, 136, %g4) ! last poll tick (for debug)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ldxa [%g0]ASI_INTR_RECEIVE_STATUS, %g4 ! wait for xt
03831d35f7499c87d51205817c93e9a8d42c4baestevel btst IRSR_BUSY, %g4
03831d35f7499c87d51205817c93e9a8d42c4baestevel stx %g4, [%g6 + 64] ! save status and payload
03831d35f7499c87d51205817c93e9a8d42c4baestevel set IRDR_0, %g2
03831d35f7499c87d51205817c93e9a8d42c4baestevel ldxa [%g2]ASI_INTR_RECEIVE, %g2
03831d35f7499c87d51205817c93e9a8d42c4baestevel stx %g2, [%g6 + 72]
03831d35f7499c87d51205817c93e9a8d42c4baestevel set IRDR_1, %g2
03831d35f7499c87d51205817c93e9a8d42c4baestevel ldxa [%g2]ASI_INTR_RECEIVE, %g2
03831d35f7499c87d51205817c93e9a8d42c4baestevel stx %g2, [%g6 + 80]
03831d35f7499c87d51205817c93e9a8d42c4baestevel set IRDR_2, %g2
03831d35f7499c87d51205817c93e9a8d42c4baestevel ldxa [%g2]ASI_INTR_RECEIVE, %g2
03831d35f7499c87d51205817c93e9a8d42c4baestevel stx %g2, [%g6 + 88]
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! clear rcv status
03831d35f7499c87d51205817c93e9a8d42c4baestevel stxa %g0, [%g0]ASI_INTR_RECEIVE_STATUS
03831d35f7499c87d51205817c93e9a8d42c4baestevel membar #Sync
03831d35f7499c87d51205817c93e9a8d42c4baestevel HERE(%g6, 144, %g4) ! signal rcvd tick (for debug)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Check for copy-rename abort signal. If this signal is received,
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! the LPA change is skipped since the rename step was not done.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! The cache flushes are still done as paranoia.
03831d35f7499c87d51205817c93e9a8d42c4baestevel set drmach_rename_abort, %g1
03831d35f7499c87d51205817c93e9a8d42c4baestevel ldx [%g6 + 72], %g2
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmp %g1, %g2
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Resume waiting if this is not drmach_rename_done.
03831d35f7499c87d51205817c93e9a8d42c4baestevel set drmach_rename_done, %g1
03831d35f7499c87d51205817c93e9a8d42c4baestevel cmp %g1, %g2
03831d35f7499c87d51205817c93e9a8d42c4baestevel ldub [%g6 + 40], %g1 ! get saved mailbox data
03831d35f7499c87d51205817c93e9a8d42c4baestevel SET_LPA(%g1, %g2, %g3) ! set LPA as indicated by the mb data
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Flush all caches (E, D, I and P) to ensure each is resynchronized
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! with the corresponding states in the new home memory. (W$ is
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! implicitly flushed when the E$ is flushed.)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Panther needs to flush the L2 cache before the L3
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! cache is flushed by the ecache flushall macro.
03831d35f7499c87d51205817c93e9a8d42c4baestevel PN_L2_FLUSHALL(%g1, %g2, %g3)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ldx [%g6 + 24], %g1 ! *ecache_flushaddr
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g6 + 32], %g2 ! ecache_size
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g6 + 36], %g3 ! ecache_linesize
03831d35f7499c87d51205817c93e9a8d42c4baestevel ECACHE_FLUSHALL(%g2, %g3, %g1, %g4)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g6 + 8], %g1 ! flush dcache
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g6 + 12], %g2
03831d35f7499c87d51205817c93e9a8d42c4baestevel CH_DCACHE_FLUSHALL(%g1, %g2, %g3)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g6 + 16], %g1 ! flush icache
03831d35f7499c87d51205817c93e9a8d42c4baestevel ld [%g6 + 20], %g2
03831d35f7499c87d51205817c93e9a8d42c4baestevel CH_ICACHE_FLUSHALL(%g1, %g2, %g3, %g4)
03831d35f7499c87d51205817c93e9a8d42c4baestevel PCACHE_FLUSHALL(%g1, %g2, %g3) ! flush pcache (no parameters)
03831d35f7499c87d51205817c93e9a8d42c4baestevel HERE(%g6, 152, %g4) ! done tick (for debug)
03831d35f7499c87d51205817c93e9a8d42c4baestevel jmpl %g7+8, %g0
03831d35f7499c87d51205817c93e9a8d42c4baestevel .asciz "drmach_rename_wait" ! for debug
03831d35f7499c87d51205817c93e9a8d42c4baesteveldrmach_rename_wait_asm_end:
03831d35f7499c87d51205817c93e9a8d42c4baestevel SET_SIZE(drmach_rename_wait)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! drmach_rename_done
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Used as signal data. See drmach_rename_wait.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ENTRY_NP(drmach_rename_done)
03831d35f7499c87d51205817c93e9a8d42c4baestevel SET_SIZE(drmach_rename_done)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! drmach_rename_abort
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Used as signal data. See drmach_rename_wait.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ENTRY_NP(drmach_rename_abort)
03831d35f7499c87d51205817c93e9a8d42c4baestevel SET_SIZE(drmach_rename_abort)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! drmach_set_lpa
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Globals: drmach_xt_mb[cpuid] contains new LPA data
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Sets the executing processor's LPA as indicated by the command
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! stored in drmach_xt_mb, a byte array indexed by cpuid. Assumes
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! the caller is preventing illegal LPA settings and transistions.
03831d35f7499c87d51205817c93e9a8d42c4baestevel CPU_INDEX(%g1, %g2)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Get LPA message from mailbox, leave in %g5.
03831d35f7499c87d51205817c93e9a8d42c4baestevel LOAD_MB(%g1, %g5, %g2)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Set LPA, mailbox data in %g5.
03831d35f7499c87d51205817c93e9a8d42c4baestevel SET_LPA(%g5, %g1, %g2)
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! Signal work is done.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ATOMIC_ADD_LONG(drmach_xt_ready, 1, %g1, %g2, %g3)
03831d35f7499c87d51205817c93e9a8d42c4baestevel SET_SIZE(drmach_set_lpa)
03831d35f7499c87d51205817c93e9a8d42c4baestevel! drmach_bc_bzero
03831d35f7499c87d51205817c93e9a8d42c4baestevel! %o0 = base vaddr of area to clear (must be 64-byte aligned)
03831d35f7499c87d51205817c93e9a8d42c4baestevel! %o1 = size of area to clear (must be multiple of 256 bytes)
03831d35f7499c87d51205817c93e9a8d42c4baestevel! 0 (success)
03831d35f7499c87d51205817c93e9a8d42c4baestevel! 1 (size too small or not modulo 256)
03831d35f7499c87d51205817c93e9a8d42c4baestevel! 2 (vaddr not 64-byte aligned)
03831d35f7499c87d51205817c93e9a8d42c4baestevel! Zero a block of storage using block commit stores.
03831d35f7499c87d51205817c93e9a8d42c4baestevel ! stda %d0, [%o0+192]%asi ! in dly slot of branch that got us here
03831d35f7499c87d51205817c93e9a8d42c4baestevel#endif /* lint */