1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * CDDL HEADER START
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * The contents of this file are subject to the terms of the
986fd29a0dc13f7608ef7f508f6e700bd7bc2720setje * Common Development and Distribution License (the "License").
986fd29a0dc13f7608ef7f508f6e700bd7bc2720setje * You may not use this file except in compliance with the License.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * See the License for the specific language governing permissions
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * and limitations under the License.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * When distributing Covered Code, include this CDDL HEADER in each
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * If applicable, add the following below this CDDL HEADER, with the
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * fields enclosed by brackets "[]" replaced with your own identifying
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * information: Portions Copyright [yyyy] [name of copyright owner]
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * CDDL HEADER END
986fd29a0dc13f7608ef7f508f6e700bd7bc2720setje * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * Use is subject to license terms.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson#pragma ident "%Z%%M% %I% %E% SMI"
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelsonint (*p2get_mem_unum)(int, uint64_t, char *, int, int *);
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson return (0);
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * Definitions for accessing the pci config space of the isa node
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * of Southbridge.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson#define SCHUMACHER_ISA_PATHNAME "/pci@1e,600000/isa@7"
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelsonstatic ddi_acc_handle_t isa_handle; /* handle for isa pci space */
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * Install 'us' driver.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * mc-us3i must stay loaded for plat_get_mem_unum()
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson if (i_ddi_attach_hw_nodes("mc-us3i") != DDI_SUCCESS)
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson cmn_err(CE_WARN, "mc-us3i driver failed to install");
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson (void) ddi_hold_driver(ddi_name_to_major("mc-us3i"));
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * Install Isa driver. This is required for the southbridge IDE
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * workaround - to reset the IDE channel during IDE bus reset.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * Panic the system in case ISA driver could not be loaded or
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * any problem in accessing its pci config space. Since the register
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * to reset the channel for IDE is in ISA config space!.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson dip = e_ddi_hold_devi_by_path(SCHUMACHER_ISA_PATHNAME, 0);
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson cmn_err(CE_PANIC, "Could not install the isa driver\n");
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson if (pci_config_setup(dip, &isa_handle) != DDI_SUCCESS) {
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson cmn_err(CE_PANIC, "Could not get the config space of isa\n");
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * This routine provides a workaround for a bug in the SB chip which
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * can cause data corruption. Will be invoked from the IDE HBA driver for
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * Acer SouthBridge at the time of IDE bus reset.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson/*ARGSUSED*/
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * The dip passed as the argument is not used here.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * This will be needed for platforms which have multiple on-board SB,
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * The dip passed will be used to match the corresponding ISA node.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * First disable the primary channel then re-enable it.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * As per ALI no wait should be required in between have
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * given 1ms delay in between to be on safer side.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * bit 2 of register 0x58 when 0 disable the channel 0.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * bit 2 of register 0x58 when 1 enables the channel 0.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * bit 3 of register 0x58 when 0 disable the channel 1.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * bit 3 of register 0x58 when 1 enables the channel 1.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * Unknown channel number passed. Return failure.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson/*ARGSUSED*/
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson return (ENOTSUP); /* not supported on this platform */
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson/*ARGSUSED*/
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson return (ENOTSUP); /* not supported on this platform */
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson/*ARGSUSED*/
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson/*ARGSUSED*/
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson/*ARGSUSED*/
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelsonplat_get_mem_unum(int synd_code, uint64_t flt_addr, int flt_bus_id,
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson int flt_in_memory, ushort_t flt_status, char *buf, int buflen, int *lenp)
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson return (p2get_mem_unum(synd_code, P2ALIGN(flt_addr, 8),
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson/*ARGSUSED*/
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelsonplat_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp)
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson return (0);
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * Fiesta support for lgroups.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * On fiesta platform, an lgroup platform handle == CPU id
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * Macro for extracting the CPU number from the CPU id
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * Return the platform handle for the lgroup containing the given CPU
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * Platform specific lgroup initialization
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * Count the number of CPUs installed to determine if
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * NUMA optimization should be enabled or not.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * All CPU nodes reside in the root node and have a
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * device type "cpu".
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson if (prom_getprop(curnode, OBP_NAME, (caddr_t)tmp_name) == -1 ||
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson prom_getprop(curnode, OBP_DEVICETYPE, tmp_name) == -1 ||
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson if (prom_getprop(curnode, "portid", (caddr_t)&portid) != -1 &&
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson else if (max_portid >= 0 && max_portid < MAX_MEM_NODES)
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * Set tuneables for fiesta architecture
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * lgrp_expand_proc_thresh is the minimum load on the lgroups
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * this process is currently running on before considering
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * expanding threads to another lgroup.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * lgrp_expand_proc_diff determines how much less the remote lgroup
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * must be loaded before expanding to it.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * Optimize for memory bandwidth by spreading multi-threaded
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * program to different lgroups.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson lgrp_expand_proc_thresh = lgrp_loadavg_max_effect - 1;
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson lgrp_expand_proc_diff = lgrp_loadavg_max_effect / 2;
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson lgrp_loadavg_tolerance = lgrp_loadavg_max_effect / 2;
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson lgrp_mem_free_thresh = 1; /* home lgrp must have some memory */
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson lgrp_expand_proc_thresh = lgrp_loadavg_max_effect - 1;
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson mem_node_pfn_shift = SCHUMACHER_MC_SHIFT - MMU_PAGESHIFT;
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * Return latency between "from" and "to" lgroups
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * This latency number can only be used for relative comparison
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * between lgroups on the running system, cannot be used across platforms,
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * and may not reflect the actual latency. It is platform and implementation
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * specific, so platform gets to decide its value. It would be nice if the
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * number was at least proportional to make comparisons more meaningful though.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * NOTE: The numbers below are supposed to be load latencies for uncached
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * memory divided by 10.
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelsonplat_lgrp_latency(lgrp_handle_t from, lgrp_handle_t to)
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * Return remote latency when there are more than two lgroups
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * (root and child) and getting latency between two different
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * lgroups or root is involved
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson from == LGRP_DEFAULT_HANDLE || to == LGRP_DEFAULT_HANDLE))
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson return (17);
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson return (12);
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * Assign memnode to lgroups
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson * Schumacher memory controller portid == global CPU id
1cb6af97c6f66f456d4f726ef056e1ebc0f73305wnelson if ((prom_getprop(nodeid, "portid", (caddr_t)&portid) == -1) ||