pcmu_cb.h revision 25cf1a301a396c38e8adf52c15f537b80d2483f7
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25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Use is subject to license terms.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#pragma ident "%Z%%M% %I% %E% SMI"
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern "C" {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * control block soft state structure:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl kmutex_t pcb_intr_lock; /* guards add/rem intr and intr dist */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint32_t pcb_no_of_inos; /* # of actual inos, including PBM */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint32_t pcb_inos[CBNINTR_MAX]; /* subset of pcmu_p->pcmu_inos array */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Prototypes.
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern void pcmu_cb_enable_nintr(pcmu_t *pcmu_p, pcmu_cb_nintr_index_t idx);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern void pcmu_cb_clear_nintr(pcmu_cb_t *cb_p, pcmu_cb_nintr_index_t idx);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#endif /* _SYS_PCMU_CB_H */