25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CDDL HEADER START
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25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Common Development and Distribution License (the "License").
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25cf1a301a396c38e8adf52c15f537b80d2483f7jl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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25cf1a301a396c38e8adf52c15f537b80d2483f7jl * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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25cf1a301a396c38e8adf52c15f537b80d2483f7jl * information: Portions Copyright [yyyy] [name of copyright owner]
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CDDL HEADER END
c9b6d37c673213b7ad91d849a105790cb469f95bfherard * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Use is subject to license terms.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#pragma ident "%Z%%M% %I% %E% SMI"
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern "C" {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The following typedef is used to represent a
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * 1275 "bus-range" property of a PCI Bus node.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Structure to represent an entry in the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * "ranges" property of a device node.
25cf1a301a396c38e8adf52c15f537b80d2483f7jltypedef enum {
25cf1a301a396c38e8adf52c15f537b80d2483f7jltypedef enum {
25cf1a301a396c38e8adf52c15f537b80d2483f7jltypedef enum {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * pcicmu soft state structure.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * State flags and mutex:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Links to other state structures:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * other state info:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * pci device node properties:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * register mapping:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Performance counters kstat.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl kmutex_t pcmu_err_mutex; /* per chip error handling mutex */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* Fault Management support */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * pcmu_soft_state values.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CMU-CH and PBM soft state macros:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define DEV_TO_SOFTSTATE(dev) ((pcmu_t *)ddi_get_soft_state(per_pcmu_state, \
25cf1a301a396c38e8adf52c15f537b80d2483f7jl ((err) ? (obj) << 8 | (op) << 4 | (err) & 0xf : DDI_SUCCESS)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Performance counters information.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CMU-CH-specific register offsets & bit field positions.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Offsets of global registers:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define PCMU_CB_DEVICE_ID_REG_OFFSET 0x00000000 /* RAGS */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CMU-CH performance counters offsets.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Offsets of registers in the interrupt block:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Offsets of registers in the PBM block:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CMU-CH control register bit definitions:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CMU-CH ECC UE AFSR bit definitions:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CMU-CH pci control register bits:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CMU-CH PCI asynchronous fault status register bit definitions:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CMU-CH PCI diagnostic register bit definitions:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define PCMU_ID_TO_IGN(pcmu_id) ((pcmu_ign_t)UPAID_TO_IGN(pcmu_id))
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Number of dispatch target entries.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Offsets of registers in the Interrupt Dispatch Table:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Mode Status register bit definitions:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define U2U_MS_IEV 0x00000040 /* bit-6: Interrupt Extension enable */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Index number of U2U registers in OBP's "regs-property" of CMU-CH
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The following two difinitions are used to control target id
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * for Interrupt dispatch data by software.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl volatile uint64_t *u2u_ino_map_reg; /* u2u intr. map register */
c9b6d37c673213b7ad91d849a105790cb469f95bfherard * Driver binding name for OPL DC system
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Offsets of registers in the interrupt block:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Offsets of registers in the ECC block:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CMU-CH control register bit definitions:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define PCMU_CB_CONTROL_STATUS_APCKEN 0x0000000000000008ull
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define PCMU_CB_CONTROL_STATUS_APERR 0x0000000000000004ull
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CMU-CH interrupt mapping register bit definitions:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CMU-CH clear interrupt register bit definitions:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define PCMU_CLEAR_INTR_REG_RECEIVED 0x0000000000000001ull
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CMU-CH ECC control register bit definitions:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CMU-CH ECC UE AFSR bit definitions:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CMU-CH PCI diagnostic register bit definitions:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define NAMEINST(dip) ddi_driver_name(dip), ddi_get_instance(dip)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define NAMEADDR(dip) ddi_node_name(dip), ddi_get_name_addr(dip)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CMU-CH Tunables
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern uint32_t pcmu_spurintr_duration; /* spurious interupt duration */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern ushort_t pcmu_command_default; /* default command */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern uint_t pcmu_ecc_afsr_retries; /* num ECC afsr retries */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern uint_t pcmu_intr_retry_intv; /* intr retry interval */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern uint_t pcmu_panic_on_fatal_errors; /* PANIC on fatal errors */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern uint_t pcmu_unclaimed_intr_max; /* Max unclaimed interrupts */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern hrtime_t pcmu_intrpend_timeout; /* intr pending timeout */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern void *per_pcmu_state; /* per-pbm soft state pointer */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern kmutex_t pcmu_global_mutex; /* attach/detach common struct lock */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Prototypes.
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern void pcmu_kstat_init(void);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern void pcmu_kstat_fini(void);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern uint64_t *ib_intr_map_reg_addr(pcmu_ib_t *, pcmu_ib_ino_t);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern uint64_t *ib_clear_intr_reg_addr(pcmu_ib_t *, pcmu_ib_ino_t);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern uint64_t cb_ino_to_map_pa(pcmu_cb_t *, pcmu_ib_ino_t);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern uint64_t cb_ino_to_clr_pa(pcmu_cb_t *, pcmu_ib_ino_t);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern int cb_remove_xintr(pcmu_t *, dev_info_t *, dev_info_t *,
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern uint32_t pcmu_intr_dist_cpuid(pcmu_ib_t *, pcmu_ib_ino_info_t *);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern int pcmu_ecc_add_intr(pcmu_t *, int, pcmu_ecc_intr_info_t *);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern void pcmu_ecc_rem_intr(pcmu_t *, int, pcmu_ecc_intr_info_t *);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern int pcmu_pbm_err_handler(dev_info_t *, ddi_fm_error_t *,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl const void *, int);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern void pcmu_ecc_classify(uint64_t, pcmu_ecc_errstate_t *);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern int pcmu_add_intr(dev_info_t *dip, dev_info_t *rdip,
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern int pcmu_remove_intr(dev_info_t *dip, dev_info_t *rdip,
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern int u2u_translate_tgtid(pcmu_t *, uint_t, volatile uint64_t *);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern void u2u_ittrans_cleanup(u2u_ittrans_data_t *, volatile uint64_t *);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#endif /* _SYS_PCICMU_H */