mc-opl.h revision cfb9e06246189a19958ae6c1a6f3bcb07f06c191
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CDDL HEADER START
25cf1a301a396c38e8adf52c15f537b80d2483f7jl *
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The contents of this file are subject to the terms of the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Common Development and Distribution License (the "License").
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * You may not use this file except in compliance with the License.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl *
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * or http://www.opensolaris.org/os/licensing.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * See the License for the specific language governing permissions
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * and limitations under the License.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl *
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * When distributing Covered Code, include this CDDL HEADER in each
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * If applicable, add the following below this CDDL HEADER, with the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * fields enclosed by brackets "[]" replaced with your own identifying
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * information: Portions Copyright [yyyy] [name of copyright owner]
25cf1a301a396c38e8adf52c15f537b80d2483f7jl *
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CDDL HEADER END
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Use is subject to license terms.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#ifndef _SYS_MC_OPL_H
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define _SYS_MC_OPL_H
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#pragma ident "%Z%%M% %I% %E% SMI"
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#ifdef __cplusplus
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern "C" {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#endif
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#include <sys/note.h>
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#ifdef DEBUG
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_LOG if (oplmc_debug) printf
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern int oplmc_debug;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#else
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_LOG _NOTE(CONSTANTCONDITION) if (0) printf
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#endif
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MC_PATROL_INTERVAL_SEC 10
0cc8ae8667155d352d327b5c92b62899a7e05bcdav
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MC_POLL_EXIT 0x01
0cc8ae8667155d352d327b5c92b62899a7e05bcdav
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * load/store MAC register
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern uint32_t mc_ldphysio(uint64_t);
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern void mc_stphysio(uint64_t, uint32_t);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define LD_MAC_REG(paddr) mc_ldphysio(paddr)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define ST_MAC_REG(paddr, data) mc_stphysio((paddr), (data))
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define BANKNUM_PER_SB 8
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
0cc8ae8667155d352d327b5c92b62899a7e05bcdavtypedef struct {
0cc8ae8667155d352d327b5c92b62899a7e05bcdav uint32_t cs_num;
0cc8ae8667155d352d327b5c92b62899a7e05bcdav uint32_t cs_status;
0cc8ae8667155d352d327b5c92b62899a7e05bcdav uint32_t cs_avail_hi;
0cc8ae8667155d352d327b5c92b62899a7e05bcdav uint32_t cs_avail_low;
0cc8ae8667155d352d327b5c92b62899a7e05bcdav uint32_t dimm_capa_hi;
0cc8ae8667155d352d327b5c92b62899a7e05bcdav uint32_t dimm_capa_low;
0cc8ae8667155d352d327b5c92b62899a7e05bcdav uint32_t ndimms;
0cc8ae8667155d352d327b5c92b62899a7e05bcdav} cs_status_t;
0cc8ae8667155d352d327b5c92b62899a7e05bcdav
25cf1a301a396c38e8adf52c15f537b80d2483f7jltypedef struct scf_log {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl struct scf_log *sl_next;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl int sl_bank;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint32_t sl_err_add;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint32_t sl_err_log;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl} scf_log_t;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
0cc8ae8667155d352d327b5c92b62899a7e05bcdav/*
0cc8ae8667155d352d327b5c92b62899a7e05bcdav * Current max serial number size is 12, but keep enough room
0cc8ae8667155d352d327b5c92b62899a7e05bcdav * to accomodate any future changes.
0cc8ae8667155d352d327b5c92b62899a7e05bcdav *
0cc8ae8667155d352d327b5c92b62899a7e05bcdav * Current max part number size is 18 + 18(Sun's partnumber + FJ's partnumber),
0cc8ae8667155d352d327b5c92b62899a7e05bcdav * but keep enough room to accomodate any future changes.
0cc8ae8667155d352d327b5c92b62899a7e05bcdav */
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MCOPL_MAX_DIMMNAME 3
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MCOPL_MAX_SERIAL 20
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MCOPL_MAX_PARTNUM 44
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MCOPL_MAX_SERIALID (MCOPL_MAX_SERIAL + MCOPL_MAX_PARTNUM)
0cc8ae8667155d352d327b5c92b62899a7e05bcdav
0cc8ae8667155d352d327b5c92b62899a7e05bcdavtypedef struct mc_dimm_info {
0cc8ae8667155d352d327b5c92b62899a7e05bcdav struct mc_dimm_info *md_next;
0cc8ae8667155d352d327b5c92b62899a7e05bcdav char md_dimmname[MCOPL_MAX_DIMMNAME + 1];
0cc8ae8667155d352d327b5c92b62899a7e05bcdav char md_serial[MCOPL_MAX_SERIAL + 1];
0cc8ae8667155d352d327b5c92b62899a7e05bcdav char md_partnum[MCOPL_MAX_PARTNUM + 1];
0cc8ae8667155d352d327b5c92b62899a7e05bcdav} mc_dimm_info_t;
0cc8ae8667155d352d327b5c92b62899a7e05bcdav
25cf1a301a396c38e8adf52c15f537b80d2483f7jltypedef struct mc_opl_state {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl struct mc_opl_state *next;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl dev_info_t *mc_dip;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint32_t mc_status;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_POLL_RUNNING 0x1
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_SOFT_SUSPENDED 0x2 /* suspended by DR */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_DRIVER_SUSPENDED 0x4 /* DDI_SUSPEND */
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MC_MEMORYLESS 0x8
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint32_t mc_board_num; /* board# */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint64_t mc_start_address; /* sb-mem-ranges */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint64_t mc_size;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl struct mc_bank {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint32_t mcb_status;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define BANK_INSTALLED 0x80000000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define BANK_MIRROR_MODE 0x40000000 /* 0: normal 1: mirror */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define BANK_PTRL_RUNNING 0x00000001
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint64_t mcb_reg_base;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint32_t mcb_ptrl_cntl;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl } mc_bank[BANKNUM_PER_SB];
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uchar_t mc_trans_table[2][64]; /* csX-mac-pa-trans-table */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl kmutex_t mc_lock;
0cc8ae8667155d352d327b5c92b62899a7e05bcdav scf_log_t *mc_scf_log[BANKNUM_PER_SB];
0cc8ae8667155d352d327b5c92b62899a7e05bcdav scf_log_t *mc_scf_log_tail[BANKNUM_PER_SB];
0cc8ae8667155d352d327b5c92b62899a7e05bcdav int mc_scf_total[BANKNUM_PER_SB];
25cf1a301a396c38e8adf52c15f537b80d2483f7jl struct memlist *mlist;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl int mc_scf_retry[BANKNUM_PER_SB];
25cf1a301a396c38e8adf52c15f537b80d2483f7jl int mc_last_error;
0cc8ae8667155d352d327b5c92b62899a7e05bcdav /* number of times memory scanned */
0cc8ae8667155d352d327b5c92b62899a7e05bcdav uint64_t mc_period[BANKNUM_PER_SB];
0cc8ae8667155d352d327b5c92b62899a7e05bcdav uint32_t mc_speed;
0cc8ae8667155d352d327b5c92b62899a7e05bcdav int mc_speedup_period[BANKNUM_PER_SB];
0cc8ae8667155d352d327b5c92b62899a7e05bcdav int mc_tick_left;
0cc8ae8667155d352d327b5c92b62899a7e05bcdav mc_dimm_info_t *mc_dimm_list;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl} mc_opl_t;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define IS_MIRROR(mcp, bn) ((mcp)->mc_bank[bn].mcb_status\
25cf1a301a396c38e8adf52c15f537b80d2483f7jl & BANK_MIRROR_MODE)
25cf1a301a396c38e8adf52c15f537b80d2483f7jltypedef struct mc_addr {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl int ma_bd; /* board number */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl int ma_bank; /* bank number */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint32_t ma_dimm_addr; /* DIMM address (same format as ERR_ADD) */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl} mc_addr_t;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jltypedef struct mc_addr_info {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl struct mc_addr mi_maddr;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl int mi_valid;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl int mi_advance;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl} mc_addr_info_t;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jltypedef struct mc_flt_stat {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint32_t mf_type; /* fault type */
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define FLT_TYPE_INTERMITTENT_CE 0x0001
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define FLT_TYPE_PERMANENT_CE 0x0002
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define FLT_TYPE_UE 0x0003
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define FLT_TYPE_SUE 0x0004
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define FLT_TYPE_MUE 0x0005
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define FLT_TYPE_CMPE 0x0006
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint32_t mf_cntl; /* MAC_BANKm_PTRL_CNTL Register */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint32_t mf_err_add; /* MAC_BANKm_{PTRL|MI}_ERR_ADD Register */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint32_t mf_err_log; /* MAC_BANKm_{PTRL|MI}_ERR_LOG Register */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint32_t mf_synd;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uchar_t mf_errlog_valid;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uchar_t mf_dimm_slot;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uchar_t mf_dram_place;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint64_t mf_flt_paddr; /* faulty physical address */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl mc_addr_t mf_flt_maddr; /* faulty DIMM address */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl} mc_flt_stat_t;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jltypedef struct mc_aflt {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint64_t mflt_id; /* gethrtime() at time of fault */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl mc_opl_t *mflt_mcp; /* mc-opl structure */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl char *mflt_erpt_class; /* ereport class name */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl int mflt_is_ptrl; /* detected by PTRL or MI */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl int mflt_nflts; /* 1 or 2 */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl int mflt_pr; /* page retire flags */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl mc_flt_stat_t *mflt_stat[2]; /* fault status */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl} mc_aflt_t;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_PTRL_STAT(mcp, i) (mcp->mc_bank[i].mcb_reg_base)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_PTRL_CNTL(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x10)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_PTRL_ERR_ADD(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x20)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_PTRL_ERR_LOG(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x24)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_MI_ERR_ADD(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x28)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_MI_ERR_LOG(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x2c)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_STATIC_ERR_ADD(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x30)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_STATIC_ERR_LOG(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x34)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_RESTART_ADD(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x40)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_REWRITE_ADD(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x44)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_EG_ADD(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x48)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_EG_CNTL(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x4c)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_MIRR(mcp, i) (mcp->mc_bank[i].mcb_reg_base + 0x50)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* use PA[37:6] */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_RESTART_PA(pa) ((pa >> 6) & 0xffffffff)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * MAC_BANKm_PTRL_STAT_Register
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_STAT_PTRL_CE 0x00000020
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_STAT_PTRL_UE 0x00000010
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_STAT_PTRL_CMPE 0x00000008
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_STAT_MI_CE 0x00000004
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_STAT_MI_UE 0x00000002
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_STAT_MI_CMPE 0x00000001
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_STAT_PTRL_ERRS (MAC_STAT_PTRL_CE|MAC_STAT_PTRL_UE\
25cf1a301a396c38e8adf52c15f537b80d2483f7jl |MAC_STAT_PTRL_CMPE)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_STAT_MI_ERRS (MAC_STAT_MI_CE|MAC_STAT_MI_UE\
25cf1a301a396c38e8adf52c15f537b80d2483f7jl |MAC_STAT_MI_CMPE)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * MAC_BANKm_PTRL_CTRL_Register
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_PTRL_START 0x80000000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_USE_RESTART_ADD 0x40000000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_PTRL_STOP 0x20000000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_PTRL_INTERVAL 0x1c000000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_PTRL_RESET 0x02000000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_PTRL_STATUS 0x01000000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_REW_REQ 0x00800000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_REW_RESET 0x00400000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_CS0_DEG_MODE 0x00200000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_PTRL_CE 0x00008000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_PTRL_UE 0x00004000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_PTRL_CMPE 0x00002000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_MI_CE 0x00001000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_MI_UE 0x00000800
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_MI_CMPE 0x00000400
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_REW_CE 0x00000200
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_REW_UE 0x00000100
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_REW_END 0x00000080
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_PTRL_ADD_MAX 0x00000040
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_REW_CMPE 0x00000020
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MAC_CNTL_PTRL_ERR_SHIFT 13
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MAC_CNTL_MI_ERR_SHIFT 10
0cc8ae8667155d352d327b5c92b62899a7e05bcdav
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_PTRL_PRESERVE_BITS (MAC_CNTL_PTRL_INTERVAL)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_PTRL_ERRS (MAC_CNTL_PTRL_CE|MAC_CNTL_PTRL_UE\
25cf1a301a396c38e8adf52c15f537b80d2483f7jl |MAC_CNTL_PTRL_CMPE)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_MI_ERRS (MAC_CNTL_MI_CE|MAC_CNTL_MI_UE\
25cf1a301a396c38e8adf52c15f537b80d2483f7jl |MAC_CNTL_MI_CMPE)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_REW_ERRS (MAC_CNTL_REW_CE|MAC_CNTL_REW_CMPE|\
25cf1a301a396c38e8adf52c15f537b80d2483f7jl MAC_CNTL_REW_UE|MAC_CNTL_REW_END)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CNTL_ALL_ERRS (MAC_CNTL_PTRL_ERRS|\
25cf1a301a396c38e8adf52c15f537b80d2483f7jl MAC_CNTL_MI_ERRS|MAC_CNTL_REW_ERRS)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_ERRLOG_SYND_SHIFT 16
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_ERRLOG_SYND_MASK 0xffff
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_ERRLOG_DIMMSLOT_SHIFT 13
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_ERRLOG_DIMMSLOT_MASK 0x7
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_ERRLOG_DRAM_PLACE_SHIFT 8
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_ERRLOG_DRAM_PLACE_MASK 0x1f
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_SET_ERRLOG_INFO(flt_stat) \
25cf1a301a396c38e8adf52c15f537b80d2483f7jl (flt_stat)->mf_errlog_valid = 1; \
25cf1a301a396c38e8adf52c15f537b80d2483f7jl (flt_stat)->mf_synd = ((flt_stat)->mf_err_log >> \
25cf1a301a396c38e8adf52c15f537b80d2483f7jl MAC_ERRLOG_SYND_SHIFT) & \
25cf1a301a396c38e8adf52c15f537b80d2483f7jl MAC_ERRLOG_SYND_MASK; \
25cf1a301a396c38e8adf52c15f537b80d2483f7jl (flt_stat)->mf_dimm_slot = ((flt_stat)->mf_err_log >> \
25cf1a301a396c38e8adf52c15f537b80d2483f7jl MAC_ERRLOG_DIMMSLOT_SHIFT) & \
25cf1a301a396c38e8adf52c15f537b80d2483f7jl MAC_ERRLOG_DIMMSLOT_MASK; \
25cf1a301a396c38e8adf52c15f537b80d2483f7jl (flt_stat)->mf_dram_place = ((flt_stat)->mf_err_log >> \
25cf1a301a396c38e8adf52c15f537b80d2483f7jl MAC_ERRLOG_DRAM_PLACE_SHIFT) & \
25cf1a301a396c38e8adf52c15f537b80d2483f7jl MAC_ERRLOG_DRAM_PLACE_MASK;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern void mc_write_cntl(mc_opl_t *, int, uint32_t);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CMD(mcp, i, cmd) mc_write_cntl(mcp, i, cmd)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MAC_PTRL_START(mcp, i) { if (!(ldphysio(MAC_PTRL_CNTL(mcp, i)) \
0cc8ae8667155d352d327b5c92b62899a7e05bcdav & MAC_CNTL_PTRL_START)) \
0cc8ae8667155d352d327b5c92b62899a7e05bcdav MAC_CMD((mcp), (i), MAC_CNTL_PTRL_START); }
0cc8ae8667155d352d327b5c92b62899a7e05bcdav
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_PTRL_START_ADD(mcp, i) MAC_CMD((mcp), (i),\
25cf1a301a396c38e8adf52c15f537b80d2483f7jl MAC_CNTL_PTRL_START|MAC_CNTL_USE_RESTART_ADD)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_PTRL_STOP(mcp, i) MAC_CMD((mcp), (i), MAC_CNTL_PTRL_STOP)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_PTRL_RESET(mcp, i) MAC_CMD((mcp), (i), MAC_CNTL_PTRL_RESET)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_REW_REQ(mcp, i) MAC_CMD((mcp), (i), MAC_CNTL_REW_REQ)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_REW_RESET(mcp, i) MAC_CMD((mcp), (i), MAC_CNTL_REW_RESET)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CLEAR_ERRS(mcp, i, errs) MAC_CMD((mcp), (i), errs)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CLEAR_ALL_ERRS(mcp, i) MAC_CMD((mcp), (i),\
25cf1a301a396c38e8adf52c15f537b80d2483f7jl MAC_CNTL_ALL_ERRS)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_CLEAR_MAX(mcp, i) \
25cf1a301a396c38e8adf52c15f537b80d2483f7jl MAC_CMD((mcp), (i), MAC_CNTL_PTRL_ADD_MAX)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * MAC_BANKm_PTRL/MI_ERR_ADD/LOG_Register
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_ERR_ADD_INVALID 0x80000000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_ERR_LOG_INVALID 0x00000080
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * MAC_BANKm_STATIC_ERR_ADD_Register
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_STATIC_ERR_VLD 0x80000000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * MAC_BANKm_MIRR_Register
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_MIRR_MIRROR_MODE 0x80000000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_MIRR_BANK_EXCLUSIVE 0x40000000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define OPL_BOARD_MAX 16
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define OPL_BANK_MAX 8
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * MAC_BANKm_EG_ADD_Register
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_EG_ADD_MASK 0x7ffffffc
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * To set the EG_CNTL register, bit[26-25] and
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * bit[21-20] must be cleared. Then the other
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * control bit should be set. Then the bit[26-25]
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * and bit[21-20] should be set while other bits
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * should be the same as before.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_EG_CNTL_MASK 0x06300000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_EG_ADD_FIX 0x80000000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_EG_FORCE_DERR00 0x40000000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_EG_FORCE_DERR16 0x20000000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_EG_FORCE_DERR64 0x10000000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_EG_FORCE_DERR80 0x08000000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_EG_DERR_ALWAYS 0x02000000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_EG_DERR_ONCE 0x04000000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_EG_DERR_NOP 0x06000000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_EG_FORCE_READ00 0x00800000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_EG_FORCE_READ16 0x00400000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_EG_RDERR_ALWAYS 0x00100000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_EG_RDERR_ONCE 0x00200000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_EG_RDERR_NOP 0x00300000
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MAC_EG_SETUP_MASK 0xf9cfffff
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* For MAC-PA translation */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_ADDRESS_BITS 31
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define PA_BITS_FOR_MAC 39
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define INDEX_OF_BANK_SUPPLEMENT_BIT 39
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MP_NONE 128
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MP_BANK_0 129
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MP_BANK_1 130
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MP_BANK_2 131
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define CS_SHIFT 29
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_TT_ENTRIES 64
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_TT_CS 2
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* export interface for error injection */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlextern int mc_inject_error(int error_type, uint64_t pa, uint32_t flags);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_INJECT_NOP 0x0
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_INJECT_INTERMITTENT_CE 0x1
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_INJECT_PERMANENT_CE 0x2
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_INJECT_UE 0x3
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_INJECT_INTERMITTENT_MCE 0x11
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_INJECT_PERMANENT_MCE 0x12
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_INJECT_SUE 0x13
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_INJECT_MUE 0x14
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_INJECT_CMPE 0x15
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_INJECT_MIRROR_MODE 0x10
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_INJECT_MIRROR(x) (x & MC_INJECT_MIRROR_MODE)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
cfb9e06246189a19958ae6c1a6f3bcb07f06c191hyw#define MC_INJECT_FLAG_PREFETCH 0x1
cfb9e06246189a19958ae6c1a6f3bcb07f06c191hyw#define MC_INJECT_FLAG_NO_TRAP MC_INJECT_FLAG_PREFETCH
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_INJECT_FLAG_RESTART 0x2
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_INJECT_FLAG_POLL 0x4
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_INJECT_FLAG_RESET 0x8
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_INJECT_FLAG_OTHER 0x10
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_INJECT_FLAG_LD 0x20
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_INJECT_FLAG_ST 0x40
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#define MC_INJECT_FLAG_PATH 0x80
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#ifdef DEBUG
0cc8ae8667155d352d327b5c92b62899a7e05bcdav
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MCI_NOP 0x0
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MCI_CE 0x1
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MCI_PERM_CE 0x2
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MCI_UE 0x3
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MCI_SHOW_ALL 0x4
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MCI_SHOW_NONE 0x5
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MCI_CMP 0x6
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MCI_ALLOC 0x7
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MCI_M_CE 0x8
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MCI_M_PCE 0x9
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MCI_M_UE 0xA
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MCI_SUSPEND 0xB
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#define MCI_RESUME 0xC
0cc8ae8667155d352d327b5c92b62899a7e05bcdav
0cc8ae8667155d352d327b5c92b62899a7e05bcdav#endif
0cc8ae8667155d352d327b5c92b62899a7e05bcdav
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#ifdef __cplusplus
25cf1a301a396c38e8adf52c15f537b80d2483f7jl}
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#endif
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#endif /* _SYS_MC_OPL_H */