opl.c revision 6b990117eca1cdf7ad1f4424209791ad38be9791
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <sys/sysmacros.h>
#include <sys/platform_module.h>
#include <sys/machsystm.h>
#include <sys/bootconf.h>
#include <sys/mem_cage.h>
#include <sys/cpu_sgnblk_defs.h>
#include <sys/sysmacros.h>
int (*opl_get_mem_unum)(int, uint64_t, char *, int, int *);
/* Memory for fcode claims. 16k times # maximum possible IO units */
int efcode_size = EFCODE_SIZE;
/* Set the maximum number of boards for DR */
int opl_boards = OPL_MAX_BOARDS;
extern int tsb_lgrp_affinity;
static opl_model_info_t opl_models[] = {
};
/*
* opl_cur_model
*/
/*
* single cycle to execute each spin loop
* for comparison, Panther takes 6 cycles for same loop
* 1500 approx nsec for OPL sleep instruction
* if spin count = OPL_BOFF_SLEEP*OPL_BOFF_SPIN then
* spin time should be equal to OPL_BOFF_TM nsecs
* Listed values tuned for 2.15GHz to 2.4GHz systems
* Value may change for future systems
*/
#define OPL_BOFF_SPIN 720
#define OPL_BOFF_BASE 1
#define OPL_BOFF_SLEEP 5
#define OPL_BOFF_CAP1 20
#define OPL_BOFF_CAP2 60
#define OPL_BOFF_TM 1500
int
set_platform_max_ncpus(void)
{
return (OPL_MAX_CPU_PER_BOARD * OPL_MAX_BOARDS);
}
int
set_platform_tsb_spares(void)
{
}
static void
{
extern int ts_dispatch_extended;
char name[MAXSYSNAME];
int i;
/*
* Get model name from the root node.
*
* We are using the prom device tree since, at this point,
* the Solaris device tree is not yet setup.
*/
for (i = 0; i < opl_num_models; i++) {
opl_cur_model = &opl_models[i];
break;
}
}
if (i == opl_num_models)
halt("No valid OPL model is found!");
(ts_dispatch_extended == -1)) {
/*
* Based on a platform model, select a dispatch table.
* TS dispatch table.
* FF1, FF2 and DC1 systems used standard dispatch tables.
*/
ts_dispatch_extended = 1;
}
}
static void
{
extern uint_t max_mmu_ctxdoms;
int max_boards;
/*
* From the model, get the maximum number of boards
* supported and set the value accordingly. If the model
* could not be determined or recognized, we assume the max value.
*/
if (opl_cur_model == NULL)
else
/*
* On OPL, cores and MMUs are one-to-one.
*/
}
#pragma weak mmu_init_large_pages
void
set_platform_defaults(void)
{
extern char *tod_module_name;
extern void mmu_init_large_pages(size_t);
/* Set the CPU signature function pointer */
/* Set appropriate tod module for OPL platform */
tod_module_name = "todopl";
if ((mmu_page_sizes == max_mmu_page_sizes) &&
(mmu_ism_pagesize != DEFAULT_ISM_PAGESIZE)) {
if (&mmu_init_large_pages)
}
tsb_lgrp_affinity = 1;
}
/*
* Convert logical a board number to a physical one.
*/
#define LSBPROP "board#"
#define PSBPROP "physical-board#"
int
opl_get_physical_board(int id)
{
int circ;
char pname[MAXSYSNAME] = {0};
int lsb_id; /* Logical System Board ID */
int psb_id; /* Physical System Board ID */
/*
* This function is called on early stage of bootup when the
* kernel device tree is not initialized yet, and also
* later on when the device tree is up. We want to try
* the fast track first.
*/
root_dip = ddi_root_node();
if (root_dip) {
/* Get from devinfo node */
continue;
continue;
== -1) {
return (-1);
} else {
return (psb_id);
}
}
}
}
/*
* We do not have the kernel device tree, or we did not
* find the node for some reason (let's say the kernel
* device tree was modified), let's try the OBP tree.
*/
pnode = prom_rootnode();
continue;
continue;
return (-1);
} else {
return (psb_id);
}
}
}
return (-1);
}
/*
* For OPL it's possible that memory from two or more successive boards
* will be contiguous across the boards, and therefore represented as a
* single chunk.
* This function splits such chunks down the board boundaries.
*/
static struct memlist *
{
if (tail) {
}
}
}
return (head);
}
void
set_platform_cage_params(void)
{
extern pgcnt_t total_pages;
extern struct memlist *phys_avail;
int ret;
if (kernel_cage_enable) {
/*
* Note: we are assuming that post has load the
* whole show in to the high end of memory. Having
* taken this leap, we copy the whole of phys_avail
* the glist and arrange for the cage to grow
* downward (descending pfns).
*/
/* free the memlist */
do {
if (ret == 0)
}
if (kcage_on)
else
}
/*ARGSUSED*/
int
{
if (opl_cpu_poweron == NULL)
return (ENOTSUP);
else
return ((opl_cpu_poweron)(cp));
}
/*ARGSUSED*/
int
{
if (opl_cpu_poweroff == NULL)
return (ENOTSUP);
else
return ((opl_cpu_poweroff)(cp));
}
int
plat_max_boards(void)
{
return (OPL_MAX_BOARDS);
}
int
{
return (OPL_MAX_CPU_PER_BOARD);
}
int
{
return (OPL_MAX_MEM_UNITS_PER_BOARD);
}
int
{
return (OPL_MAX_IO_UNITS_PER_BOARD);
}
int
{
return (OPL_MAX_CMP_UNITS_PER_BOARD);
}
int
{
return (OPL_MAX_CORE_UNITS_PER_BOARD);
}
int
{
return (pfn >> mem_node_pfn_shift);
}
/* ARGSUSED */
void
{
/*
* OPL mem slices are always aligned on a 256GB boundary.
*/
mem_node_physalign = 0;
/*
* Boot install lists are arranged <addr, len>, <addr, len>, ...
*/
}
}
}
/*
* Find the CPU associated with a slice at boot-time.
*/
void
{
int board;
int memnode;
struct {
} mem_range;
}
panic("Can not find sb-mem-ranges property in mc node %x",
nodeid);
}
}
/*
* Return the platform handle for the lgroup containing the given CPU
*
* For OPL, lgroup platform handle == board #.
*/
extern int mpo_disabled;
extern lgrp_handle_t lgrp_default_handle;
{
/*
* Return the real platform handle for the CPU until
* such time as we know that MPO should be disabled.
* At that point, we set the "mpo_disabled" flag to true,
* and from that point on, return the default handle.
*
* By the time we know that MPO should be disabled, the
* first CPU will have already been added to a leaf
* lgroup, but that's ok. The common lgroup code will
* double check that the boot CPU is in the correct place,
* and in the case where mpo should be disabled, will move
* it to the root if necessary.
*/
if (mpo_disabled) {
/* If MPO is disabled, return the default (UMA) handle */
} else
return (plathand);
}
/*
* Platform specific lgroup initialization
*/
void
plat_lgrp_init(void)
{
extern uint32_t lgrp_expand_proc_thresh;
extern uint32_t lgrp_expand_proc_diff;
/*
* Set tuneables for the OPL architecture
*
* lgrp_expand_proc_thresh is the minimum load on the lgroups
* this process is currently running on before considering
* expanding threads to another lgroup.
*
* lgrp_expand_proc_diff determines how much less the remote lgroup
* must be loaded before expanding to it.
*
* Since remote latencies can be costly, attempt to keep 3 threads
* within the same lgroup before expanding to the next lgroup.
*/
}
/*
* Platform notification of lgroup (re)configuration changes
*/
/*ARGSUSED*/
void
{
if (mpo_disabled)
return;
switch (evt) {
case LGRP_CONFIG_MEM_ADD:
/*
* Establish the lgroup handle to memnode translation.
*/
break;
case LGRP_CONFIG_MEM_DEL:
/*
* Special handling for possible memory holes.
*/
}
}
break;
case LGRP_CONFIG_MEM_RENAME:
/*
* During a DR copy-rename operation, all of the memory
* on one board is moved to another board -- but the
* the memory has changed locations without changing identity.
*
* Source is where we are copying from and target is where we
* are copying to. After source memnode is copied to target
* memnode, the physical addresses of the target memnode are
* renamed to match what the source memnode had. Then target
* memnode can be removed and source memnode can take its
* place.
*
* To do this, swap the lgroup handle to memnode mappings for
* the boards, so target lgroup will have source memnode and
* source lgroup will have empty target memnode which is where
* its memory will go (if any is added to it later).
*
* Then source memnode needs to be removed from its lgroup
* and added to the target lgroup where the memory was living
* target memnode and now lives in the source memnode with
* different physical addresses even though it is the same
* memory.
*/
/*
* Special handling for possible memory holes.
*/
}
/*
* Remove source memnode of copy rename from its lgroup
* and add it to its new target lgroup
*/
break;
default:
break;
}
}
/*
* Return latency between "from" and "to" lgroups
*
* This latency number can only be used for relative comparison
* between lgroups on the running system, cannot be used across platforms,
* and may not reflect the actual latency. It is platform and implementation
* specific, so platform gets to decide its value. It would be nice if the
* number was at least proportional to make comparisons more meaningful though.
* NOTE: The numbers below are supposed to be load latencies for uncached
* memory divided by 10.
*
*/
int
{
/*
* Return min remote latency when there are more than two lgroups
* (root and child) and getting latency between two different lgroups
* or root is involved
*/
return (42);
else
return (35);
}
/*
* Return platform handle for root lgroup
*/
plat_lgrp_root_hand(void)
{
if (mpo_disabled)
return (lgrp_default_handle);
return (LGRP_DEFAULT_HANDLE);
}
/*ARGSUSED*/
void
{
}
void
load_platform_drivers(void)
{
(void) i_ddi_attach_pseudo_node("dr");
}
/*
* No platform drivers on this platform
*/
char *platform_module_list[] = {
(char *)0
};
/*ARGSUSED*/
void
{
}
/*ARGSUSED*/
void
{
static void (*scf_panic_callback)(int);
static void (*scf_shutdown_callback)(int);
/*
* In case of shutdown and panic, SCF call back
* function should be called.
* <SCF call back functions>
* scf_panic_callb() : panicsys()->panic_quiesce_hw()
* scf_shutdown_callb(): halt() or power_down() or reboot_machine()
* cpuid should be -1 and state should be SIGST_EXIT.
*/
/*
* find the symbol for the SCF panic callback routine in driver
*/
if (scf_panic_callback == NULL)
scf_panic_callback = (void (*)(int))
modgetsymvalue("scf_panic_callb", 0);
if (scf_shutdown_callback == NULL)
scf_shutdown_callback = (void (*)(int))
modgetsymvalue("scf_shutdown_callb", 0);
switch (sub_state) {
case SIGSUBST_PANIC:
if (scf_panic_callback == NULL) {
"scf_panic_callb not found\n");
return;
}
break;
case SIGSUBST_HALT:
if (scf_shutdown_callback == NULL) {
"scf_shutdown_callb not found\n");
return;
}
break;
case SIGSUBST_ENVIRON:
if (scf_shutdown_callback == NULL) {
"scf_shutdown_callb not found\n");
return;
}
break;
case SIGSUBST_REBOOT:
if (scf_shutdown_callback == NULL) {
"scf_shutdown_callb not found\n");
return;
}
break;
}
}
}
/*ARGSUSED*/
int
{
/*
* check if it's a Memory error.
*/
if (flt_in_memory) {
if (opl_get_mem_unum != NULL) {
} else {
return (ENOTSUP);
}
} else {
return (ENOTSUP);
}
}
/*ARGSUSED*/
int
{
int ret = 0;
int plen;
if (sb == -1) {
return (ENXIO);
}
/*
* opl_cur_model is assigned here
*/
if (opl_cur_model == NULL) {
}
switch (opl_cur_model->model_type) {
case FF1:
break;
case FF2:
break;
case DC1:
case DC2:
case DC3:
break;
default:
/* This should never happen */
return (ENODEV);
}
} else {
if (lenp)
}
return (ret);
}
#define SCF_PUTINFO(f, s, p) \
f(KEY_ESCF, 0x01, 0, s, p)
void
plat_nodename_set(void)
{
void *datap;
int counter = 5;
/*
* find the symbol for the SCF put routine in driver
*/
if (scf_service_function == NULL)
modgetsymvalue("scf_service_putinfo", 0);
/*
* If the symbol was found, call it. Otherwise, log a note (but not to
* the console).
*/
if (scf_service_function == NULL) {
"!plat_nodename_set: scf_service_putinfo not found\n");
return;
}
datap =
return;
}
while ((SCF_PUTINFO(scf_service_function,
}
if (counter == 0)
"!plat_nodename_set: "
"scf_service_putinfo not responding\n");
}
/*
* Preallocate enough memory for fcode claims.
*/
{
/*
* allocate the physical memory for the Oberon fcode.
*/
return (efcode_alloc_base + efcode_size);
}
{
return (tmp_alloc_base);
}
void
startup_platform(void)
{
}
void
{
int impl;
if (IS_OLYMPUS_C(impl)) {
} else {
}
}
int
{
if (opl_get_mem_sid == NULL) {
return (ENOTSUP);
}
}
int
{
if (opl_get_mem_offset == NULL) {
return (ENOTSUP);
}
}
int
{
if (opl_get_mem_addr == NULL) {
return (ENOTSUP);
}
}
void
plat_lock_delay(int *backoff)
{
int i;
int cnt;
int flag;
int ctr;
/*
* Platform specific lock delay code for OPL
*
* Using staged linear increases in the delay.
* The sleep instruction is the preferred method of delay,
* but is too large of granularity for the initial backoff.
*/
if (*backoff < OPL_BOFF_CAP1) {
/*
* If desired backoff is long enough,
* use sleep for most of it
*/
cnt >= OPL_BOFF_SLEEP;
cnt -= OPL_BOFF_SLEEP) {
}
/*
* spin for small remainder of backoff
*
* fake call to nulldev included to prevent
* compiler from optimizing out the spin loop
*/
}
} else {
/* backoff is very large. Fill it by sleeping */
delay_start = gethrtime();
/*
* use sleep instructions for delay
*/
for (i = 0; i < cnt; i++) {
}
/*
* Note: if the other strand executes a sleep instruction,
* then the sleep ends immediately with a minimum time of
* 42 clocks. We check gethrtime to insure we have
* waited long enough. And we include both a short
* spin loop and a sleep for any final delay time.
*/
}
}
}
/*
* We adjust the backoff in three linear stages
* The initial stage has small increases as this phase is
* usually handle locks with light contention. We don't want
* to have a long backoff on a lock that is available.
*
* In the second stage, we are in transition, unsure whether
* the lock is under heavy contention. As the failures to
* obtain the lock increase, we back off further.
*
* For the final stage, we are in a heavily contended or
* long held long so we want to reduce the number of tries.
*/
if (*backoff < OPL_BOFF_CAP1) {
*backoff += 1;
} else {
if (*backoff < OPL_BOFF_CAP2) {
*backoff += OPL_BOFF_SLEEP;
} else {
}
if (*backoff > OPL_BOFF_MAX) {
*backoff = OPL_BOFF_MAX;
}
}
}