25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CDDL HEADER START
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The contents of this file are subject to the terms of the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Common Development and Distribution License (the "License").
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * You may not use this file except in compliance with the License.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * See the License for the specific language governing permissions
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * and limitations under the License.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * When distributing Covered Code, include this CDDL HEADER in each
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * If applicable, add the following below this CDDL HEADER, with the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * fields enclosed by brackets "[]" replaced with your own identifying
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * information: Portions Copyright [yyyy] [name of copyright owner]
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CDDL HEADER END
07d06da50d310a325b457d6330165aebab1e0064Surya Prakki * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Use is subject to license terms.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * This file is through cpp before being used as
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * an inline. It contains support routines used
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * only by DR for the copy-rename sequence.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#if defined(lint)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#endif /* lint */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#if !defined(lint)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * turn off speculative mode to prevent unwanted memory access
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * when we are in the FMEM loops
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#if defined(lint)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jldrmach_fmem_loop_script(caddr_t critical, int size, caddr_t stat)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl{ return; }
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#else /* lint */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* turn off speculative mode */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* read the critical region to get everything in the cache */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* clear L2_CTRL_UGE_TRAP error bit */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* now tell the master CPU that we are ready */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * note that we branch to 5f, which branches right back to 2 here.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The trick is that when that branch instruction has already been
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * patched to a branch to itself - an infinite loop.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The master thread will patch it back to "ba 2b" when it
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * completes.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* Once we are back, we first check if there has been any
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * L2_CTRL_UGE_TRAP errors, if so we have to fail the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * operation. This will cause a panic because the system
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * is already in inconsistent state.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* set error code and stat code */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* turn on speculative mode again */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * busy wait will affect sibling strands so
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * we put sleep instruction in the delay slot
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#endif /* lint */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#if defined(lint)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jl{ return; }
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#else /* lint */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#if defined(lint)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jl{ return (0); }
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#else /* lint */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* turn off speculative mode */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* save locals to save area */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* l7 is set only when FMEM cmd is issued to SCF */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* read the critical region to put everything in the cache */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* we branch to 4f but eventually we branch back here to finish up */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * save some registers for debugging
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * l0 - SCF_REG_BASE
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * l1 - SCF_TD
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * l2 - SCF_TD + 8
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * l5 - DELAY
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* Check for L2_CTRL_UGE_TRAP error */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* restore all locals */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* turn on speculative mode */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* return error code here */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* clear L2_CTRL_UGE_TRAP error bit */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* set up the register locations and parameters */
4fe85d41bb4eb0db41934722f4b06c8acec2d25aJames Anderson /* check if SCF is ONLINE */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* check if SCF is busy */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* clear STATUS bit */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* clear CMD_COMPLETE bit */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * o1 points to SCFBASE.SCF_TDATA[0xe]
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * l0 points to SCFBASE
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * crticial->SCF_TD[0] = source board #
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * crticial->SCF_TD[1] = target board #
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * l1 = critical->SCF_TD[0 - 7]
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * l2 = 0xffff
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * o4 = critical->SCF_TD[8 - 15]
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * o3 = (*o4) & 0xffff
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Because there is no parity protection on the ebus
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * we read the data back after the write to verify
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * we write 2 bytes at a time.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * If the data read is not the same as data written
b307f191031b69156225d50e36c406311441051abm * we retry up to a limit of SCF_RETRY_CNT
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* if we have reach TDATA+8, we switch to l1 */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* XXX: Why we need 2 loops??? */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* if we reach TDATA, we are done */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* read from SCF back to our buffer for debugging */
b307f191031b69156225d50e36c406311441051abm /* The following code conforms to the FMEM
b307f191031b69156225d50e36c406311441051abm sequence (4) as described in the Columbus2
b307f191031b69156225d50e36c406311441051abm logical spec section 4.6
b307f191031b69156225d50e36c406311441051abm /* read from SCF SB INFO register */
b307f191031b69156225d50e36c406311441051abm /* If BUSY bit is set, abort */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* Now tell SCF to do it */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* 0x10A6 is the magic command */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* read STATUS_READY bit and clear it only if it is set */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* XXX: this STATUS_READY checking seems meaningless */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* check CMD_COMPLETE bit and clear */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* timeout delay checking */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* we are done or timed out */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#endif /* lint */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#if defined(lint)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
25cf1a301a396c38e8adf52c15f537b80d2483f7jl{ return; }
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#else /* lint */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#endif /* lint */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#if defined(lint)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (0);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#else /* lint */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#endif /* lint */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#if defined(lint)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#else /* lint */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#endif /* lint */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#if defined(lint)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (0);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#else /* lint */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#endif /* lint */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#if defined(lint)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*ARGSUSED*/
07d06da50d310a325b457d6330165aebab1e0064Surya Prakkidrmach_flush(drmach_copy_rename_critical_t *x, uint_t y)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#else /* lint */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#endif /* lint */