scfreg.c revision 25cf1a301a396c38e8adf52c15f537b80d2483f7
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* All Rights Reserved, Copyright (c) FUJITSU LIMITED 2006
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* SCF command send control area save
*/
struct scf_cmd scfcmd_save;
/*
* Function list
*/
/*
* External function
*/
/*
* scf_map_regs()
*
* Description: Register and SRAM map processing.
*
*/
int
{
#define SCF_FUNC_NAME "scf_map_regs() "
int ret = 1;
};
/* map register 1 : SCF register */
"%s: scf_map_regs: ddi_regs_map_setup failed.\n",
goto END_map_regs;
}
/* map register 2 : SCF contorol register */
"%s: scf_map_regs: ddi_regs_map_setup failed.\n",
goto END_map_regs;
}
/* get size of register 3 : SCF DSCP SRAM */
"%s: scf_map_regs: ddi_dev_regsize failed.\n",
goto END_map_regs;
}
/* check size */
"%s: scf_map_regs: ddi_dev_regsize failed.\n",
goto END_map_regs;
}
/* map register 3 : SCF DSCP SRAM */
"%s: scf_map_regs: ddi_regs_map_setup failed.\n",
goto END_map_regs;
}
/* get size of register 4 : SCF system SRAM */
"%s: scf_map_regs: ddi_dev_regsize failed.\n",
goto END_map_regs;
}
/* check size */
"%s: scf_map_regs: ddi_dev_regsize failed.\n",
goto END_map_regs;
}
/* map register 4 : SCF system SRAM */
"%s: scf_map_regs: ddi_regs_map_setup failed.\n",
goto END_map_regs;
}
/* get size of register 5 : SCF interface block */
"%s: scf_map_regs: ddi_dev_regsize failed.\n",
goto END_map_regs;
}
/* check size */
"%s: scf_map_regs: ddi_dev_regsize failed.\n",
goto END_map_regs;
} else {
}
/* map register 5 : SCF interface block */
"%s: scf_map_regs: ddi_regs_map_setup failed.\n",
goto END_map_regs;
}
/* get size of register : SRAM driver trace */
/* map register : SRAM driver trace */
"%s: scf_map_regs: "
"ddi_regs_map_setup failed.\n",
goto END_map_regs;
}
}
/* SRAM trace initialize */
ret = 0;
/*
* END_map_regs
*/
return (ret);
}
/*
* scf_unmap_regs()
*
* Description: Register and SRAM un-map processing.
*
*/
void
{
#define SCF_FUNC_NAME "scf_unmap_regs() "
/* Register and SRAM un-map */
}
}
}
}
}
}
}
/*
* scf_send_cmd_check_bufful()
*
* Description: SCF command send and buffer busy check processing.
*
*/
int
{
#define SCF_FUNC_NAME "scf_send_cmd_check_bufful() "
int ret = 0;
int buf_ful_cnt = scf_buf_ful_rcnt;
int rci_busy_cnt = scf_rci_busy_rcnt;
int cv_ret;
buf_ful_cnt--;
lb = ddi_get_lbolt();
cv_ret = 0;
while (cv_ret != (-1)) {
sizeof (kcondvar_t));
if ((cv_ret =
sizeof (kcondvar_t));
}
}
rci_busy_cnt--;
lb = ddi_get_lbolt();
cv_ret = 0;
while (cv_ret != (-1)) {
sizeof (kcondvar_t));
if ((cv_ret =
sizeof (kcondvar_t));
}
}
} else {
break;
}
}
if (scf_comtbl.scf_exec_p) {
} else if (scf_comtbl.scf_path_p) {
}
"%s,Buffer busy occurred in XSCF. "
"SCF command = 0x%02x%02x\n",
(rci_busy_cnt == 0)) {
"%s,RCI busy occurred in XSCF. "
"SCF command = 0x%02x%02x\n",
}
}
/*
* END_send_cmd_check_bufful
*/
return (ret);
}
/*
* scf_send_cmd()
*
* Description: Synchronized SCF command send processing.
*
*/
int
{
#define SCF_FUNC_NAME "scf_send_cmd() "
int ret = 0;
int offline_ret;
int cmdbusy_ret;
/* Check SCF command send sync re-start */
if (scf_comtbl.path_stop_flag != 0) {
/* Check path stop */
scf_comtbl.path_stop_flag = 0;
goto END_scf_send_cmd;
}
goto END_scf_send_cmd99;
}
/* Check SCF command send sync re-stop */
(scf_comtbl.path_stop_flag != 0)) {
goto STOP_scf_send_cmd;
}
/* Check SCF command send sync stop status */
goto SP_scf_send_cmd;
}
while (scf_comtbl.cmd_busy != 0) {
sizeof (kcondvar_t));
&scf_comtbl.all_mutex) == 0) {
sizeof (kcondvar_t));
goto END_scf_send_cmd99;
}
}
/*
* STOP_scf_send_cmd
*/
/* Check SUSPEND flag */
if (scf_comtbl.suspend_flag) {
goto END_scf_send_cmd;
}
(void) scf_path_check(&statep);
/* not exec SCF device */
goto END_scf_send_cmd;
}
/* send comannd for interrupt */
while ((scf_comtbl.scf_cmd_exec_flag != 0) ||
(offline_ret != SCF_PATH_ONLINE) ||
(cmdbusy_ret != SCF_COMMAND_READY)) {
sizeof (kcondvar_t));
&scf_comtbl.all_mutex) == 0) {
scf_comtbl.cmd_busy_wait = 0;
goto END_scf_send_cmd;
}
scf_comtbl.cmd_busy_wait = 0;
(void) scf_path_check(&statep);
/* not exec SCF device */
goto END_scf_send_cmd;
}
if ((scf_comtbl.scf_cmd_exec_flag == 0) &&
(offline_ret != SCF_PATH_ONLINE)) {
goto END_scf_send_cmd;
}
}
/*
* SP_scf_send_cmd
*/
/* Check SUSPEND flag */
if (scf_comtbl.suspend_flag) {
goto END_scf_send_cmd;
}
goto END_scf_send_cmd;
}
/* SCF command send sync stop */
goto END_scf_send_cmd99;
}
}
}
}
while (scf_comtbl.cmd_end_wait != 0) {
sizeof (kcondvar_t));
&scf_comtbl.all_mutex) == 0) {
scf_comtbl.cmd_end_wait = 0;
goto END_scf_send_cmd;
}
}
} else {
}
}
scf_comtbl.cmd_end_wait = 0;
case NORMAL_END:
break;
case E_NOT_SUPPORT:
case RCI_NS:
break;
default:
}
goto END_scf_send_cmd99;
}
/*
* END_scf_send_cmd
*/
scf_comtbl.cmd_busy = 0;
if (scf_comtbl.cmd_wait) {
sizeof (kcondvar_t));
}
scf_comtbl.path_stop_flag = 0;
}
/*
* END_scf_send_cmd99
*/
return (ret);
}
/*
* scf_i_send_cmd()
*
* Description: SCF command send processing. (for hard access)
*
*/
void
{
#define SCF_FUNC_NAME "scf_i_send_cmd() "
int scount;
int wkleng;
int ii;
case SCF_USE_S_BUF:
case SCF_USE_SSBUF:
case SCF_USE_SLBUF:
/*
* Use Tx data register, Not use Tx buffer data
*/
/* Set Tx data register memo */
} else {
}
}
/* Set CMD_SPARE data */
}
break;
case SCF_USE_L_BUF:
case SCF_USE_LSBUF:
/*
* Use Tx data register, Use Tx buffer data
*/
/* Make Tx buffer data sum */
}
}
/* Set Tx data register memo : data length */
}
/* Set Tx data register memo : sum */
}
/* Set CMD_SPARE data */
}
/* SRAM data write */
}
break;
}
/* Make Tx data sum */
}
/* Set Tx data sum */
/* TxDATA register set */
/* SCF command extendedregister set */
if (scf_comtbl.scf_cmd_resend_flag == 0) {
} else {
}
sizeof (statep->reg_command_exr));
/* SCF command register set */
/* Set sub command code */
/* Set command code : SCF interrupt */
sizeof (statep->reg_command));
/* Register read sync */
/* SCF command timer start */
/* SRAM trace */
} else {
}
while (scount != 0) {
} else {
}
}
}
}
/*
* panic send cmd function
*/
void
{
#define SCF_FUNC_NAME "scf_p_send_cmd() "
int scount;
int ii;
case SCF_USE_S_BUF:
case SCF_USE_SSBUF:
case SCF_USE_SLBUF:
/*
* Use Tx data register, Not use Tx buffer data
*/
/* Set Tx data register memo */
} else {
}
}
break;
case SCF_USE_L_BUF:
case SCF_USE_LSBUF:
/*
* Use Tx data register, Use Tx buffer data
*/
/* Make Tx buffer data sum */
}
}
/* Set Tx data register memo : data length */
}
/* Set Tx data register memo : sum */
}
/* Set CMD_SPARE data */
}
/* SRAM data write */
}
break;
}
/* Make Tx data sum */
}
/* Set Tx data sum */
/* TxDATA register set */
/* SCF command extendedregister set */
/* SCF command register set */
/* Register read sync */
}
/*
* SCF path status check
*/
int
{
#define SCF_FUNC_NAME "scf_path_check() "
int ret;
/* SCF path exec status */
}
/* SCF path change status */
}
if (ret == SCF_PATH_ONLINE) {
}
} else {
/* SCF path halt status */
}
ret = SCF_PATH_HALT;
}
return (ret);
}
/*
* ESCF offline check
*/
int
{
#define SCF_FUNC_NAME "scf_offline_check() "
int ret;
/* Get SCF Status extended register */
sizeof (statep->reg_status_exr));
/* Check SCF online */
}
if (timer_exec_flag == FLAG_ON) {
/* Check online wait timer exec */
if (scf_timer_check(SCF_TIMERCD_ONLINE) ==
} else {
}
} else {
}
} else {
scf_unit = 1;
} else {
scf_unit = 0;
}
"%s: SCF went to offline mode. unit=%d",
}
if (timer_exec_flag == FLAG_ON) {
/* Check online wait timer exec */
if (scf_timer_check(SCF_TIMERCD_ONLINE) ==
/* DCSP interface stop */
/* SCF online timer start */
statep->online_to_rcnt = 0;
}
}
}
return (ret);
}
/*
* SCF command busy check
*/
int
{
#define SCF_FUNC_NAME "scf_cmdbusy_check() "
int ret;
/* Get SCF command register */
sizeof (statep->reg_command));
sizeof (statep->reg_command_exr));
/* Check busy flag */
/* Check busy timer exec */
if (scf_timer_check(SCF_TIMERCD_CMDBUSY) ==
} else {
}
} else {
/* Check busy timer exec */
if (scf_timer_check(SCF_TIMERCD_CMDBUSY) ==
/* busy timer start */
statep->devbusy_to_rcnt = 0;
}
}
}
return (ret);
}
void
{
#define SCF_FUNC_NAME "scf_alivecheck_start() "
/* Check alive check exec */
/* Alive check value initialize */
scf_acr_phase_code = 0;
/* Alive timer register initialize */
/* Register read sync */
/* Alive Interrupt enable */
sizeof (statep->reg_control));
/* Register read sync */
/* Alive timer register set */
/* Register read sync */
/* Alive check register set */
/* Register read sync */
}
}
void
{
#define SCF_FUNC_NAME "scf_alivecheck_stop() "
/* Alive Interrupt disable */
sizeof (statep->reg_control));
/* Register read sync */
/* Alive timer register clear */
/* Register read sync */
}
/*
* forbid SCF interrupt
*/
void
{
#define SCF_FUNC_NAME "scf_forbid_intr() "
/* Interrupt disable */
sizeof (statep->reg_control));
/* Register read sync */
}
/*
* permit SCF interrupt
*/
void
{
#define SCF_FUNC_NAME "scf_permit_intr() "
if (flag) {
/* SCF Status register interrupt clear */
/* Register read sync */
/* SCF Status extended register interrupt clear */
/* Register read sync */
/* DSCP buffer status register interrupt clear */
/* Register read sync */
/* SCF interrupt status register interrupt clear */
/* Register read sync */
}
/* Interrupt enable */
sizeof (statep->reg_control));
/* Register read sync */
}
/*
* Path status check
*/
int
{
#define SCF_FUNC_NAME "scf_check_state() "
int ret;
/* PATH_STAT_ACTIVE status */
} else {
while (wkstatep) {
/* PATH_STAT_STANDBY status */
goto END_check_state;
} else {
}
}
while (wkstatep) {
/* PATH_STAT_STOP status */
goto END_check_state;
} else {
}
}
while (wkstatep) {
/* PATH_STAT_FAIL status */
goto END_check_state;
} else {
}
}
while (wkstatep) {
/* PATH_STAT_DISCON status */
goto END_check_state;
} else {
}
}
/* scf_comtbl.scf_suspend_p queue */
/* PATH_STAT_DISCON status */
}
} else {
/* PATH_STAT_DISCON status */
}
/*
* END_check_state
*/
return (ret);
}
/*
* Multi path status change and queue change
*/
void
{
#define SCF_FUNC_NAME "scf_chg_scf() "
SCF_FUNC_NAME ": start instance = %d status = %d",
/* Set path status */
}
switch (status) {
case PATH_STAT_ACTIVE:
/* Not queue change */
break;
case PATH_STAT_EMPTY:
/* Change empty queue */
if (scf_comtbl.scf_suspend_p) {
}
} else {
}
break;
case PATH_STAT_STANDBY:
/* Change standby queue */
if (scf_comtbl.scf_wait_p) {
}
} else {
}
break;
case PATH_STAT_STOP:
/* Change stop queue */
if (scf_comtbl.scf_stop_p) {
}
} else {
}
break;
case PATH_STAT_FAIL:
/* Change fail queue */
if (scf_comtbl.scf_err_p) {
}
} else {
}
break;
case PATH_STAT_DISCON:
/* Change disconnect queue */
if (scf_comtbl.scf_disc_p) {
}
} else {
}
break;
}
}
/*
* Multi path queue check and delete queue
*/
void
{
#define SCF_FUNC_NAME "scf_del_queue() "
/* Delete active(exec) queue */
return;
/* Delete active(path change) queue */
return;
} else {
/* Delete empty(suspend) queue */
return;
} else {
return;
}
}
}
}
/* Delete standby(wait) queue */
return;
} else {
return;
}
}
}
}
/* Delete fail(error) queue */
return;
} else {
return;
}
}
}
}
/* Delete stop queue */
return;
} else {
return;
}
}
}
}
/* Delete disconnect queue */
return;
} else {
return;
}
}
}
}
}
}
/*
* SCF command send sync
*/
int
{
#define SCF_FUNC_NAME "scf_make_send_cmd() "
/* falg = SCF_USE_STOP : SCF command stop wait */
/* falg = SCF_USE_START : SCF_USE_STOP signal */
int ret;
flag);
return (ret);
}
/*
* scf_sram_trace_init()
*
* SRAM trace initialize processing.
*
*/
void
{
#define SCF_FUNC_NAME "scf_sram_trace_init() "
int wk_leng;
int ii;
/* Check SRAM map */
if ((wk_drv_id == 0) ||
((wk_data_write >= wk_data_top) &&
(wk_data_write <= wk_data_last))) {
/* Make SRAM driver trace header */
sizeof (scf_drvtrc_ent_t));
(uint32_t)(sizeof (scf_if_drvtrc_t));
(uint32_t)(sizeof (scf_if_drvtrc_t));
sizeof (scf_drvtrc_ent_t));
} else {
statep->memo_DATA_TOP = 0;
statep->memo_DATA_WRITE = 0;
statep->memo_DATA_LAST = 0;
}
} else {
}
wk_leng = sizeof (SCF_DRIVER_VERSION);
if (wk_leng > DRV_ID_SIZE) {
}
}
*wk_out_p = ' ';
}
}
} else {
statep->memo_DATA_TOP = 0;
statep->memo_DATA_WRITE = 0;
statep->memo_DATA_LAST = 0;
}
}
/*
* scf_sram_trace()
*
* SRAM trace get processing.
*
*/
void
{
#define SCF_FUNC_NAME "scf_sram_trace() "
int ii;
if (statep->memo_DATA_WRITE) {
clock_val = ddi_get_lbolt();
} else {
}
/* Check log id */
switch (wk_log_id) {
case DTC_ONLINETO: /* SCF online timeout */
case DTC_ONLINE: /* SCF online start */
case DTC_OFFLINE: /* SCF offline start */
statep->reg_int_st);
statep->reg_status);
break;
case DTC_SENDDATA: /* SCF send command data */
break;
case DTC_RECVDATA: /* SCF recv command data */
break;
case DTC_ERRRTN: /* SCF command retuen error */
break;
case DTC_RSUMERR: /* SCF command receive sum error */
break;
case DTC_DSCP_TXREQ: /* DSCP TxREQ request */
statep->reg_int_st);
break;
case DTC_DSCP_RXACK: /* DSCP RxACK request */
statep->reg_int_st);
break;
case DTC_DSCP_RXEND: /* DSCP RxEND request */
statep->reg_int_st);
break;
case DTC_DSCP_RXREQ:
statep->reg_int_st);
break;
case DTC_DSCP_TXACK: /* DSCP TxACK interrupt */
case DTC_DSCP_ACKTO: /* DSCP ACK timeout */
case DTC_DSCP_ENDTO: /* DSCP END timeout */
statep->reg_int_st);
break;
case DTC_DSCP_TXEND: /* DSCP TxEND interrupt */
statep->reg_int_st);
break;
case DTC_SENDDATA_SRAM: /* SCF send command data for SRAM */
case DTC_RECVDATA_SRAM: /* SCF recv command data for SRAM */
case DTC_DSCP_SENDDATA: /* DSCP send data */
case DTC_DSCP_RECVDATA: /* DSCP send data */
/* Information is already set */
break;
case DTC_CMD: /* SCF command start */
case DTC_INT: /* SCF interrupt */
case DTC_CMDTO: /* SCF command timeout */
case DTC_CMDBUSYTO: /* SCF command busy timeout */
default:
statep->reg_int_st);
statep->reg_status);
break;
}
/* Set trace data */
}
/* Next offset update */
}
}
}