25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CDDL HEADER START
25cf1a301a396c38e8adf52c15f537b80d2483f7jl *
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * The contents of this file are subject to the terms of the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Common Development and Distribution License (the "License").
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * You may not use this file except in compliance with the License.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl *
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * or http://www.opensolaris.org/os/licensing.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * See the License for the specific language governing permissions
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * and limitations under the License.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl *
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * When distributing Covered Code, include this CDDL HEADER in each
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * If applicable, add the following below this CDDL HEADER, with the
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * fields enclosed by brackets "[]" replaced with your own identifying
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * information: Portions Copyright [yyyy] [name of copyright owner]
25cf1a301a396c38e8adf52c15f537b80d2483f7jl *
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CDDL HEADER END
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Use is subject to license terms.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#pragma ident "%Z%%M% %I% %E% SMI"
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * CMU-CH PBM implementation:
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * initialization
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Bus error interrupt handler
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#include <sys/types.h>
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#include <sys/kmem.h>
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#include <sys/spl.h>
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#include <sys/sysmacros.h>
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#include <sys/sunddi.h>
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#include <sys/fm/protocol.h>
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#include <sys/fm/util.h>
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#include <sys/machsystm.h>
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#include <sys/async.h>
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#include <sys/ddi_impldefs.h>
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#include <sys/ontrap.h>
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#include <sys/pcicmu/pcicmu.h>
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#include <sys/membar.h>
25cf1a301a396c38e8adf52c15f537b80d2483f7jl#include <sys/ivintr.h>
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic uint_t pcmu_pbm_error_intr(caddr_t a);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/* The nexus interrupt priority values */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlint pcmu_pil[] = {14, 14, 14, 14, 14, 14};
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jlvoid
25cf1a301a396c38e8adf52c15f537b80d2483f7jlpcmu_pbm_create(pcmu_t *pcmu_p)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl{
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_pbm_t *pcbm_p;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl int len;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl dev_info_t *dip = pcmu_p->pcmu_dip;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Allocate a state structure for the PBM and cross-link it
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * to its per pci node state structure.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcbm_p = (pcmu_pbm_t *)kmem_zalloc(sizeof (pcmu_pbm_t), KM_SLEEP);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_p->pcmu_pcbm_p = pcbm_p;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcbm_p->pcbm_pcmu_p = pcmu_p;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl len = snprintf(pcbm_p->pcbm_nameinst_str,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl sizeof (pcbm_p->pcbm_nameinst_str), "%s%d", NAMEINST(dip));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcbm_p->pcbm_nameaddr_str = pcbm_p->pcbm_nameinst_str + ++len;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl (void) snprintf(pcbm_p->pcbm_nameaddr_str,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl sizeof (pcbm_p->pcbm_nameinst_str) - len, "%s@%s", NAMEADDR(dip));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_pbm_setup(pcbm_p);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl PCMU_DBG4(PCMU_DBG_ATTACH, dip,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl "pcmu_pbm_create: ctrl=%x, afsr=%x, afar=%x, diag=%x\n",
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcbm_p->pcbm_ctrl_reg, pcbm_p->pcbm_async_flt_status_reg,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcbm_p->pcbm_async_flt_addr_reg, pcbm_p->pcbm_diag_reg);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl PCMU_DBG1(PCMU_DBG_ATTACH, dip, "pcmu_pbm_create: conf=%x\n",
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcbm_p->pcbm_config_header);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Register a function to disable pbm error interrupts during a panic.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl bus_func_register(BF_TYPE_ERRDIS,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl (busfunc_t)pcmu_pbm_disable_errors, pcbm_p);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * create the interrupt-priorities property if it doesn't
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * already exist to provide a hint as to the PIL level for
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * our interrupt.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (ddi_getproplen(DDI_DEV_T_ANY, dip,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl DDI_PROP_DONTPASS, "interrupt-priorities",
25cf1a301a396c38e8adf52c15f537b80d2483f7jl &len) != DDI_PROP_SUCCESS) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* Create the interrupt-priorities property. */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl (void) ddi_prop_create(DDI_DEV_T_NONE, dip,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl DDI_PROP_CANSLEEP, "interrupt-priorities",
25cf1a301a396c38e8adf52c15f537b80d2483f7jl (caddr_t)pcmu_pil, sizeof (pcmu_pil));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl }
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_pbm_configure(pcbm_p);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl}
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jlint
25cf1a301a396c38e8adf52c15f537b80d2483f7jlpcmu_pbm_register_intr(pcmu_pbm_t *pcbm_p)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl{
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_t *pcmu_p = pcbm_p->pcbm_pcmu_p;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint32_t mondo;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl int r = DDI_SUCCESS;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_ib_nintr_clear(pcmu_p->pcmu_ib_p, pcmu_p->pcmu_inos[CBNINTR_PBM]);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Install the PCI error interrupt handler.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl mondo = PCMU_IB_INO_TO_MONDO(pcmu_p->pcmu_ib_p,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_p->pcmu_inos[CBNINTR_PBM]);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
b0fc0e77220f1fa4c933fd58a4e1dedcd650b0f1govinda VERIFY(add_ivintr(mondo, pcmu_pil[CBNINTR_PBM],
b0fc0e77220f1fa4c933fd58a4e1dedcd650b0f1govinda (intrfunc)pcmu_pbm_error_intr, (caddr_t)pcmu_p, NULL, NULL) == 0);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcbm_p->pcbm_iblock_cookie = (void *)(uintptr_t)pcmu_pil[CBNINTR_PBM];
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Create the pokefault mutex at the PIL below the error interrupt.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl mutex_init(&pcbm_p->pcbm_pokeflt_mutex, NULL, MUTEX_DRIVER,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl (void *)(uintptr_t)ipltospl(spltoipl(
25cf1a301a396c38e8adf52c15f537b80d2483f7jl (int)(uintptr_t)pcbm_p->pcbm_iblock_cookie) - 1));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (PCMU_ATTACH_RETCODE(PCMU_PBM_OBJ, PCMU_OBJ_INTR_ADD, r));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl}
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jlvoid
25cf1a301a396c38e8adf52c15f537b80d2483f7jlpcmu_pbm_destroy(pcmu_t *pcmu_p)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl{
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_pbm_t *pcbm_p = pcmu_p->pcmu_pcbm_p;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_ib_t *pib_p = pcmu_p->pcmu_ib_p;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl uint32_t mondo;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl PCMU_DBG0(PCMU_DBG_DETACH, pcmu_p->pcmu_dip, "pcmu_pbm_destroy:\n");
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl mondo = PCMU_IB_INO_TO_MONDO(pcmu_p->pcmu_ib_p,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_p->pcmu_inos[CBNINTR_PBM]);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Free the pokefault mutex.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl mutex_destroy(&pcbm_p->pcbm_pokeflt_mutex);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Remove the error interrupt.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl intr_dist_rem(pcmu_pbm_intr_dist, pcbm_p);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_ib_intr_disable(pib_p,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_p->pcmu_inos[CBNINTR_PBM], PCMU_IB_INTR_WAIT);
b0fc0e77220f1fa4c933fd58a4e1dedcd650b0f1govinda
b0fc0e77220f1fa4c933fd58a4e1dedcd650b0f1govinda VERIFY(rem_ivintr(mondo, pcmu_pil[CBNINTR_PBM]) == 0);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Remove the error disable function.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl bus_func_unregister(BF_TYPE_ERRDIS,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl (busfunc_t)pcmu_pbm_disable_errors, pcbm_p);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_pbm_teardown(pcbm_p);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Free the pbm state structure.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl kmem_free(pcbm_p, sizeof (pcmu_pbm_t));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_p->pcmu_pcbm_p = NULL;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl}
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jlstatic uint_t
25cf1a301a396c38e8adf52c15f537b80d2483f7jlpcmu_pbm_error_intr(caddr_t a)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl{
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_t *pcmu_p = (pcmu_t *)a;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_pbm_t *pcbm_p = pcmu_p->pcmu_pcbm_p;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl ddi_fm_error_t derr;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl int err = DDI_FM_OK;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl on_trap_data_t *otp = pcbm_p->pcbm_ontrap_data;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl bzero(&derr, sizeof (ddi_fm_error_t));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl derr.fme_version = DDI_FME_VERSION;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl mutex_enter(&pcmu_p->pcmu_err_mutex);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if ((otp != NULL) && (otp->ot_prot & OT_DATA_ACCESS)) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * ddi_poke protection, check nexus and children for
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * expected errors.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl otp->ot_trap |= OT_DATA_ACCESS;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl membar_sync();
25cf1a301a396c38e8adf52c15f537b80d2483f7jl derr.fme_flag = DDI_FM_ERR_POKE;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl err = pcmu_pbm_err_handler(pcmu_p->pcmu_dip, &derr,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl (void *)pcmu_p, PCI_INTR_CALL);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl } else if (pcmu_check_error(pcmu_p) != 0) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * unprotected error, check for all errors.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (pcmu_errtrig_pa) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl (void) ldphysio(pcmu_errtrig_pa);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl }
25cf1a301a396c38e8adf52c15f537b80d2483f7jl derr.fme_flag = DDI_FM_ERR_UNEXPECTED;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl err = pcmu_pbm_err_handler(pcmu_p->pcmu_dip, &derr,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl (void *)pcmu_p, PCI_INTR_CALL);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl }
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (err == DDI_FM_FATAL) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (pcmu_panic_on_fatal_errors) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl mutex_exit(&pcmu_p->pcmu_err_mutex);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl cmn_err(CE_PANIC, "%s-%d: Fatal PCI bus error(s)\n",
25cf1a301a396c38e8adf52c15f537b80d2483f7jl ddi_driver_name(pcmu_p->pcmu_dip),
25cf1a301a396c38e8adf52c15f537b80d2483f7jl ddi_get_instance(pcmu_p->pcmu_dip));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl }
25cf1a301a396c38e8adf52c15f537b80d2483f7jl }
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl mutex_exit(&pcmu_p->pcmu_err_mutex);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_ib_nintr_clear(pcmu_p->pcmu_ib_p, pcmu_p->pcmu_inos[CBNINTR_PBM]);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (DDI_INTR_CLAIMED);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl}
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jlvoid
25cf1a301a396c38e8adf52c15f537b80d2483f7jlpcmu_pbm_suspend(pcmu_pbm_t *pcbm_p)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl{
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_t *pcmu_p = pcbm_p->pcbm_pcmu_p;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_ib_ino_t ino = pcmu_p->pcmu_inos[CBNINTR_PBM];
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcbm_p->pcbm_imr_save = *ib_intr_map_reg_addr(pcmu_p->pcmu_ib_p, ino);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl}
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jlvoid
25cf1a301a396c38e8adf52c15f537b80d2483f7jlpcmu_pbm_resume(pcmu_pbm_t *pcbm_p)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl{
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_t *pcmu_p = pcbm_p->pcbm_pcmu_p;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_ib_ino_t ino = pcmu_p->pcmu_inos[CBNINTR_PBM];
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_ib_nintr_clear(pcmu_p->pcmu_ib_p, ino);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl *ib_intr_map_reg_addr(pcmu_p->pcmu_ib_p, ino) = pcbm_p->pcbm_imr_save;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl}
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jlvoid
25cf1a301a396c38e8adf52c15f537b80d2483f7jlpcmu_pbm_intr_dist(void *arg)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl{
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_pbm_t *pcbm_p = (pcmu_pbm_t *)arg;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_t *pcmu_p = pcbm_p->pcbm_pcmu_p;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_ib_t *pib_p = pcmu_p->pcmu_ib_p;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_ib_ino_t ino =
25cf1a301a396c38e8adf52c15f537b80d2483f7jl PCMU_IB_MONDO_TO_INO(pcmu_p->pcmu_inos[CBNINTR_PBM]);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl mutex_enter(&pib_p->pib_intr_lock);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_ib_intr_dist_nintr(pib_p, ino, ib_intr_map_reg_addr(pib_p, ino));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl mutex_exit(&pib_p->pib_intr_lock);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl}
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl/*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * Function used to log PBM AFSR register bits and to lookup and fault
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * handle associated with PBM AFAR register. Called by
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * pcmu_pbm_err_handler with pcmu_err_mutex held.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jlint
25cf1a301a396c38e8adf52c15f537b80d2483f7jlpcmu_pbm_afsr_report(dev_info_t *dip, uint64_t fme_ena,
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_pbm_errstate_t *pbm_err_p)
25cf1a301a396c38e8adf52c15f537b80d2483f7jl{
25cf1a301a396c38e8adf52c15f537b80d2483f7jl int fatal = 0;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /* LINTED variable */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_t *pcmu_p = get_pcmu_soft_state(ddi_get_instance(dip));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl ASSERT(MUTEX_HELD(&pcmu_p->pcmu_err_mutex));
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pbm_err_p->pcbm_pri = PBM_PRIMARY;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl (void) pcmu_pbm_classify(pbm_err_p);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl /*
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * We are currently not dealing with the multiple error
25cf1a301a396c38e8adf52c15f537b80d2483f7jl * case, for any secondary errors we will panic.
25cf1a301a396c38e8adf52c15f537b80d2483f7jl */
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pbm_err_p->pcbm_pri = PBM_SECONDARY;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (pcmu_pbm_classify(pbm_err_p)) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl fatal++;
25cf1a301a396c38e8adf52c15f537b80d2483f7jl pcmu_pbm_ereport_post(dip, fme_ena, pbm_err_p);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl }
25cf1a301a396c38e8adf52c15f537b80d2483f7jl
25cf1a301a396c38e8adf52c15f537b80d2483f7jl if (fatal) {
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (DDI_FM_FATAL);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl }
25cf1a301a396c38e8adf52c15f537b80d2483f7jl return (DDI_FM_NONFATAL);
25cf1a301a396c38e8adf52c15f537b80d2483f7jl}