cpr_resume_setup.s revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#if defined(lint)
#else /* lint */
#include "assym.h"
#endif /* lint */
#include <sys/asm_linkage.h>
#include <sys/privregs.h>
#include <sys/machparam.h>
#include <vm/hat_sfmmu.h>
#include <sys/cpr_impl.h>
/*
* resume kernel entry point from cprboot
* 1. restore I/D TSB registers
* 2. restore primary and secondary context registers
* 3. initialize cpu state registers
* 4. set up the thread and lwp registers for the cpr process
* 5. switch to kernel trap
* 6. restore checkpoint pc and stack pointer
* 7. longjmp back to kernel
*
* registers from cprboot:exit_to_kernel()
* %o0 prom cookie
* %o1 struct sun4u_machdep *mdp
*
* Any change to this register assignment
* require changes to cprboot_srt0.s
*/
#if defined(lint)
/* ARGSUSED */
void
{}
/* ARGSUSED */
int
i_cpr_cif_wrapper(void *args)
{ return (0); }
/* ARGSUSED */
void
{}
/* ARGSUSED */
void
{}
#else /* lint */
!
!
.seg ".data"
.skip 4096
.word 0
.word 4096
.align 8
.word 0, 0
.nword 0
.nword 0
!
!
.seg ".text"
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
!
! Don't need to flushw
!
mov %l7, %i7 ! i7 = saved pc
mov %l6, %fp ! i6 = saved sp
ret ! return 1
restore %g0, 1, %o0 ! takes underflow, switches stack
SET_SIZE(i_cpr_resume_setup)
!
!
! restore the original %tba.
!
! a call stack looks like this:
!
! current prom cookie
! [i_cpr_cif_wrapper]
! client_handler
! p1275_sparc_cif_handler
! prom_xxx
!
ENTRY(i_cpr_cif_wrapper)
save %sp, -SA64(MINFRAME64 + 8), %sp
rdpr %tba, %o5 ! read original %tba
stx %o5, [%fp + V9BIAS64 - 8]
set prom_tba, %l4
ldx [%l4], %o4 ! read prom_tba
wrpr %o4, %tba ! switch to prom trap table
ldn [%g3], %g4
jmpl %g4, %o7 ! call prom service
mov %i0, %o0
ldx [%l4], %o4 ! read prom_tba
rdpr %tba, %o3 ! read current %tba
cmp %o3, %o4 ! did prom change %tba ?
bne,pn %xcc, 1f ! yes, dont reset %tba
nop
ldx [%fp + V9BIAS64 - 8], %o5
wrpr %o5, %tba ! no change, restore orignal
1:
ret
restore %g0, %o0, %o0
SET_SIZE(i_cpr_cif_wrapper)
!
! write dtlb entry at index
!
ENTRY(dtlb_wr_entry)
sllx %o0, 3, %o0 ! index << 3
ldx [%o1], %o5 ! o5 = tte.ll
ldx [%o2], %o4 ! o4 = va_tag
srlx %o4, MMU_PAGESHIFT, %o4 ! clear any page offset
sllx %o4, MMU_PAGESHIFT, %o4 ! o4 = va_tag & PAGEMASK
set MMU_TAG_ACCESS, %o3
stxa %o4, [%o3]ASI_DMMU
stxa %o5, [%o0]ASI_DTLB_ACCESS
membar #Sync
retl
nop
SET_SIZE(dtlb_wr_entry)
!
! write itlb entry at index
!
ENTRY(itlb_wr_entry)
sllx %o0, 3, %o0 ! index << 3
ldx [%o1], %o5 ! o5 = tte.ll
ldx [%o2], %o4 ! o4 = va_tag
srlx %o4, MMU_PAGESHIFT, %o4 ! clear any page offset
sllx %o4, MMU_PAGESHIFT, %o4 ! o4 = va_tag & PAGEMASK
set MMU_TAG_ACCESS, %o3
stxa %o4, [%o3]ASI_IMMU
stxa %o5, [%o0]ASI_ITLB_ACCESS
membar #Sync
retl
nop
SET_SIZE(itlb_wr_entry)
#endif /* !lint */