todbq4802.c revision 8461248208fabd3a8230615f8615e5bf1b4dcdcb
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* tod driver module for TI BQ4802 part
*
* Note: The way to access the bq4802's RTC registers is different than
* the previous RTC devices (m5823, m5819p, ds1287, etc) that we used.
* The address returns from OBP is mapped directly to the bq4802's RTC
* just add the register offset to the base address.
* To access the previous RTC devices, we write the register index to
* the data port (v_rtc_data_reg).
*/
#include <sys/sysmacros.h>
#include <sys/todbq4802.h>
#include <sys/machsystm.h>
/*
* tod_ops entry routines
*/
static timestruc_t todbq4802_get(void);
static void todbq4802_set(timestruc_t);
static uint_t todbq4802_clear_watchdog_timer(void);
static void todbq4802_set_power_alarm(timestruc_t);
static void todbq4802_clear_power_alarm(void);
static uint64_t todbq4802_get_cpufrequency(void);
/*
* External variables
*/
extern int watchdog_enable;
extern int watchdog_available;
extern int boothowto;
/*
* Global variables
*/
int bq4802_debug_flags;
uint_t bq4802_uip_count = 0;
/*
* Module linkage information for the kernel.
*/
&mod_miscops, "tod module for TI BQ4802"
};
static struct modlinkage modlinkage = {
};
static void write_rtc_time(struct rtc_t *);
static void write_rtc_alarm(struct rtc_t *);
int
_init(void)
{
if (v_rtc_addr_reg == NULL)
/* Clear AF flag by reading reg Flags (D) */
(void) BQ4802_DATA_REG(RTC_FLAGS);
/*
* check if hardware watchdog timer is available and user
* enabled it.
*/
if (watchdog_enable) {
if (!watchdog_available) {
"unavailable");
" disabled [debugger]");
}
}
}
return (mod_install(&modlinkage));
}
int
_fini(void)
{
return (EBUSY);
return (mod_remove(&modlinkage));
}
/*
* The loadable-module _info(9E) entry point
*/
int
{
}
/*
* Read the current time from the clock chip and convert to UNIX form.
* Assumes that the year in the clock chip is valid.
* Must be called with tod_lock held.
*/
static timestruc_t
todbq4802_get(void)
{
DPRINTF("todbq4802_get: century=%d year=%d dom=%d hrs=%d min=%d"
/*
* tod_year is base 1900 so this code needs to adjust the true
* year retrieved from the rtc's century and year fields.
*/
return (ts);
}
/*
* locations are updated simultaneously from the internal
* real-time counters. To prevent reading data in transition,
* updates to the bq4802 clock registers should be halted.
* Updating is halted by setting the Update Transfer Inhibit
* (UTI) bit D3 of the control register E. As long as the
* UTI bit is 1, updates to user-accessible clock locations are
* inhibited. Once the frozen clock information is retrieved by
* reading the appropriate clock memory locations, the UTI
* bit should be reset to 0 in order to allow updates to occur
* from the internal counters. Because the internal counters
* are not halted by setting the UTI bit, reading the clock
* locations has no effect on clock accuracy. Once the UTI bit
* is reset to 0, the internal registers update within one
* second the user-accessible registers with the correct time.
* A halt command issued during a clock update allows the
* update to occur before freezing the data.
*/
static void
{
/*
* Freeze
*/
/*
* Unfreeze
*/
}
/*
* Write the specified time into the clock chip.
* Must be called with tod_lock held.
*/
static void
{
int year;
/* tod_year is base 1900 so this code needs to adjust */
DPRINTF("todbq4802_set: year=%d dom=%d hrs=%d min=%d sec=%d\n",
}
/*
* The UTI bit must be used to set the bq4802 clock.
* Once set, the locations can be written with the desired
* information in BCD format. Resetting the UTI bit to 0 causes
* the written values to be transferred to the internal clock
* counters and allows updates to the user-accessible registers
* to resume within one second.
*/
void
{
/*
* Freeze
*/
/*
* Unfreeze
*/
}
void
{
}
/*
* program the rtc registers for alarm to go off at the specified time
*/
static void
{
/*
* disable alarms and clear AF flag by reading reg Flags (D)
*/
(void) BQ4802_DATA_REG(RTC_FLAGS);
DPRINTF("todbq4802_set_alarm: dom=%d hrs=%d min=%d sec=%d\n",
/*
* Write alarm values and enable alarm
*/
}
/*
* clear alarm interrupt
*/
static void
{
}
/*
* Determine the cpu frequency by watching the TOD chip rollover twice.
* Cpu clock rate is determined by computing the ticks added (in tick register)
* during one second interval on TOD.
*/
{
}
/*ARGSUSED*/
static uint_t
{
return (0);
}
static uint_t
{
return (0);
}