px_lib4u.c revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <sys/ddi_impldefs.h>
#include <sys/iommutsb.h>
#include <px_obj.h>
#include <pcie_pwr.h>
#include "px_tools_var.h"
#include <px_regs.h>
#include <px_csr.h>
#include "px_lib4u.h"
#pragma weak jbus_stst_order
extern void jbus_stst_order();
int
{
return (DDI_FAILURE);
switch (chip_id) {
case FIRE_VER_10:
break;
case FIRE_VER_20:
break;
default:
return (DDI_FAILURE);
}
/*
* Allocate platform specific structure and link it to
* the px state structure.
*/
"portid", -1);
/*
* XXX - Move all ddi_regs_map_setup() from px_util.c
* to to this file before complete virtualization.
*/
/*
* Create "virtual-dma" property to support child devices
* needing to know DVMA range.
*/
sizeof (px_dvma_range_prop_t));
/*
* Initilize all fire hardware specific blocks.
*/
/* Initilize device handle */
return (DDI_SUCCESS);
}
int
{
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
*sysino);
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
ret);
return (DDI_FAILURE);
}
*intr_state);
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
/* Reset all Interrupts */
&sysino) != DDI_SUCCESS)
return (BF_FATAL);
return (BF_FATAL);
}
return (BF_NONE);
}
/*ARGSUSED*/
int
int flag)
{
"pages 0x%x atrr 0x%x addr 0x%p pfn_index 0x%llx, flag 0x%x\n",
"px_lib_iommu_map failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
!= H_EOK) {
"px_lib_iommu_demap failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_iommu_getmap failed, ret 0x%lx\n", ret);
}
*attributes_p, *r_addr_p);
return (DDI_SUCCESS);
}
/*
* Checks dma attributes against system bypass ranges
* The bypass range is determined by the hardware. Return them so the
* common code can do generic checking against them.
*/
/*ARGSUSED*/
int
{
*lo_p = MMU_BYPASS_BASE;
*hi_p = MMU_BYPASS_END;
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_iommu_getbypass failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
*io_addr_p);
return (DDI_SUCCESS);
}
/*
* bus dma sync entry point.
*/
/*ARGSUSED*/
int
{
"handle 0x%llx off 0x%x len 0x%x flags 0x%x\n",
/*
* jbus_stst_order is found only in certain cpu modules.
* Just return success if not present.
*/
if (&jbus_stst_order == NULL)
return (DDI_SUCCESS);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
/*
* No flush needed when sending data from memory to device.
* Nothing to do to "sync" memory to what device would already see.
*/
return (DDI_SUCCESS);
/*
* Perform necessary cpu workaround to ensure jbus ordering.
* CPU's internal "invalidate FIFOs" are flushed.
*/
#if !defined(lint)
#endif
#if !defined(lint)
#endif
return (DDI_SUCCESS);
}
/*
* MSIQ Functions:
*/
/*ARGSUSED*/
int
{
int ret;
/*
* Map the EQ memory into the Fire MMU (has to be 512KB aligned)
* and then initialize the base address register.
*
* Allocate entries from Fire IOMMU so that the resulting address
* is properly aligned. Calculate the index of the first allocated
* entry. Note: The size of the mapping is assumed to be a multiple
* of the page size.
*/
return (DDI_FAILURE);
MMU_MAP_BUF)) != DDI_SUCCESS) {
"hvio_msiq_init failed, ret 0x%lx\n", ret);
(void) px_lib_msiq_fini(dip);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
/*
* Unmap and free the EQ memory that had been mapped
* into the Fire IOMMU.
*/
/* Free the entries from the Fire MMU */
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
ra_p, *msiq_rec_cnt_p);
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msiq_getvalid failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msiq_setvalid failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msiq_getstate failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
*msiq_state);
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msiq_setstate failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msiq_gethead failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
*msiq_head);
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msiq_sethead failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msiq_gettail failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
*msiq_tail);
return (DDI_SUCCESS);
}
/*ARGSUSED*/
void
{
if (!eq_rec_p->eq_rec_rid) {
/* Set msiq_rec_rid to zero */
msiq_rec_p->msiq_rec_rid = 0;
return;
}
"eq_rec_rid 0x%llx eq_rec_fmt_type 0x%llx "
"eq_rec_len 0x%llx eq_rec_addr0 0x%llx "
"eq_rec_addr1 0x%llx eq_rec_data0 0x%llx "
/*
* Only upper 4 bits of eq_rec_fmt_type is used
* to identify the EQ record type.
*/
case EQ_REC_MSI32:
} else {
/* Default case is FIRE2.0 */
}
break;
case EQ_REC_MSI64:
} else {
/* Default case is FIRE2.0 */
}
break;
case EQ_REC_MSG:
break;
default:
"0x%lx is an unknown EQ record type",
break;
}
/* Zero out eq_rec_rid field */
eq_rec_p->eq_rec_rid = 0;
}
/*
* MSI Functions:
*/
/*ARGSUSED*/
int
{
ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msi_getmsiq failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
*msiq_id);
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msi_setmsiq failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msi_getvalid failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msi_setvalid failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msi_getstate failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
*msi_state);
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msi_setstate failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*
* MSG Functions:
*/
/*ARGSUSED*/
int
{
"hvio_msg_getmsiq failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
*msiq_id);
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msg_setmsiq failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
msg_valid_state)) != H_EOK) {
"hvio_msg_getvalid failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
msg_valid_state)) != H_EOK) {
"hvio_msg_setvalid failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*
* Currently unsupported by hypervisor
*/
int
{
!= H_EOK)
}
}
void
{
}
/*
* PCI tool Functions:
* Currently unsupported by hypervisor
*/
/*ARGSUSED*/
int
{
}
/*ARGSUSED*/
int
{
}
/*ARGSUSED*/
int
{
}
/*
* Misc Functions:
* Currently unsupported by hypervisor
*/
{
}
void
{
}
/*ARGSUSED*/
int
{
/*
* No special config space access services in this layer.
*/
return (DDI_FAILURE);
}
#ifdef DEBUG
int px_peekfault_cnt = 0;
int px_pokefault_cnt = 0;
#endif /* DEBUG */
/*ARGSUSED*/
static int
{
int err = DDI_SUCCESS;
/* Set up protected environment. */
} else
err = DDI_FAILURE;
/*
* Read the async fault register for the PEC to see it sees
* a master-abort.
*
* XXX check if we need to clear errors at this point.
*/
err = DDI_FAILURE;
/* Take down protected environment. */
no_trap();
#ifdef DEBUG
if (err == DDI_FAILURE)
#endif
return (err);
}
/*ARGSUSED*/
static int
{
int err = DDI_SUCCESS;
/* Use ontrap data in handle set up by FMA */
switch (size) {
case sizeof (uint8_t):
break;
case sizeof (uint16_t):
break;
case sizeof (uint32_t):
break;
case sizeof (uint64_t):
break;
}
if (flags == DDI_DEV_AUTOINCR)
/*
* Read the async fault register for the PEC to see it
* sees a master-abort.
*
* XXX check if we need to clear errors at this point.
*/
err = DDI_FAILURE;
#ifdef DEBUG
#endif
break;
}
}
}
return (err);
}
int
{
}
/*ARGSUSED*/
static int
{
int err = DDI_SUCCESS;
} else
err = DDI_FAILURE;
no_trap();
#ifdef DEBUG
if (err == DDI_FAILURE)
#endif
return (err);
}
static int
{
int err = DDI_SUCCESS;
if (repcount == 1) {
(void *)host_addr);
} else {
int i;
for (i = 0; i < size; i++)
*ff_addr++ = 0xff;
err = DDI_FAILURE;
#ifdef DEBUG
#endif
}
} else {
(void *)host_addr);
if (flags == DDI_DEV_AUTOINCR)
}
} else {
err = DDI_FAILURE;
#ifdef DEBUG
#endif
}
}
return (err);
}
/*ARGSUSED*/
int
{
}
/*
* implements PPM interface
*/
int
{
switch (cmd) {
case PPMREQ_PRE_PWR_OFF:
/*
* Currently there is no device power management for
* the root complex (fire). When there is we need to make
* sure that it is at full power before trying to send the
* PME_Turn_Off message.
*/
"ioctl: request to send PME_Turn_Off\n");
return (px_goto_l23ready(px_p));
case PPMREQ_PRE_PWR_ON:
case PPMREQ_POST_PWR_ON:
/* code to be written for Fire 2.0. return failure for now */
return (DDI_FAILURE);
default:
return (DDI_FAILURE);
}
}
/*
* called by px_ioctl.
* returns DDI_SUCCESS or DDI_FAILURE
* 1. Wait for link to be in L1 state (link status reg)
* 2. write to PME_Turn_off reg to boradcast
* 3. set timeout
* 4. If timeout, return failure.
*/
static int
{
int ret = DDI_SUCCESS;
/* If no PM info, return failure */
return (DDI_FAILURE);
/* Clear the PME_To_ACK receieved flag */
ret = DDI_FAILURE;
goto l23ready_done;
}
/*
* if cv_timedwait returns -1, it is either
* 1) timed out or
* 2) there was a pre-mature wakeup but by the time
* cv_timedwait is called again end < lbolt i.e.
* end is in the past.
* 3) By the time we make first cv_timedwait call,
* end < lbolt is true.
*/
if (timeleft == -1)
break;
}
/*
* Either timedout or interrupt didn't get a
* chance to grab the mutex and set the flag.
* release the mutex and delay for sometime.
* This will 1) give a chance for interrupt to
* set the flag 2) creates a delay between two
* consequetive requests.
*/
delay(5);
ret = DDI_FAILURE;
" for PME_TO_ACK\n");
}
}
/* PME_To_ACK receieved */
return (ret);
}
/*
* Extract the drivers binding name to identify which chip we're binding to.
* Whenever a new bus bridge is created, the driver alias entry should be
* added here to identify the device if needed. If a device isn't added,
* the identity defaults to PX_CHIP_UNIDENTIFIED.
*/
static uint32_t
{
"module-revision#", 0);
/* Check for Fire driver binding name */
}
return (PX_CHIP_UNIDENTIFIED);
}