px_lib4u.c revision 25cf1a301a396c38e8adf52c15f537b80d2483f7
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <sys/ddi_impldefs.h>
#include <sys/iommutsb.h>
#include <sys/byteorder.h>
#include <px_obj.h>
#include <pcie_pwr.h>
#include "px_tools_var.h"
#include <px_regs.h>
#include <px_csr.h>
#include <sys/machsystm.h>
#include "px_lib4u.h"
#include "px_err.h"
#include "oberon_regs.h"
#pragma weak jbus_stst_order
extern void jbus_stst_order();
/*
* px_lib_map_registers
*
* This function is called from the attach routine to map the registers
* accessed by this driver.
*
* used by: px_attach()
*
* return value: DDI_FAILURE on failure
*/
int
{
/*
* PCI CSR Base
*/
goto fail;
}
reg_bank++;
/*
* XBUS CSR Base
*/
goto fail;
}
done:
}
return (DDI_SUCCESS);
fail:
}
return (DDI_FAILURE);
}
/*
* px_lib_unmap_regs:
*
* This routine unmaps the registers mapped by map_px_registers.
*
* used by: px_detach(), and error conditions in px_attach()
*
* return value: none
*/
void
{
int i;
for (i = 0; i < PX_REG_MAX; i++) {
}
}
int
{
return (DDI_FAILURE);
switch (chip_id) {
case FIRE_VER_10:
return (DDI_FAILURE);
case FIRE_VER_20:
break;
case OBERON_VER_10:
break;
default:
return (DDI_FAILURE);
}
/*
* Allocate platform specific structure and link it to
* the px state structure.
*/
"portid", -1);
/* Map in the registers */
return (DDI_FAILURE);
}
/*
* Create "virtual-dma" property to support child devices
* needing to know DVMA range.
*/
sizeof (px_dvma_range_prop_t));
/*
* Initilize all fire hardware specific blocks.
*/
/*
* Initialize all the interrupt handlers
*/
switch (PX_CHIP_TYPE(pxu_p)) {
case PX_CHIP_OBERON:
break;
case PX_CHIP_FIRE:
break;
default:
return (DDI_FAILURE);
}
/* Initilize device handle */
return (DDI_SUCCESS);
}
int
{
/*
* Deinitialize all the interrupt handlers
*/
switch (PX_CHIP_TYPE(pxu_p)) {
case PX_CHIP_OBERON:
break;
case PX_CHIP_FIRE:
break;
default:
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
*sysino);
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
ret);
return (DDI_FAILURE);
}
*intr_state);
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
/* Reset all Interrupts */
&sysino) != DDI_SUCCESS)
return (BF_FATAL);
return (BF_FATAL);
}
return (BF_NONE);
}
/*ARGSUSED*/
int
{
"pages 0x%x attr 0x%x addr 0x%p pfn_index 0x%llx flags 0x%x\n",
"px_lib_iommu_map failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
!= H_EOK) {
"px_lib_iommu_demap failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_iommu_getmap failed, ret 0x%lx\n", ret);
}
return (DDI_SUCCESS);
}
/*
* Checks dma attributes against system bypass ranges
* The bypass range is determined by the hardware. Return them so the
* common code can do generic checking against them.
*/
/*ARGSUSED*/
int
{
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_iommu_getbypass failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
*io_addr_p);
return (DDI_SUCCESS);
}
/*
* bus dma sync entry point.
*/
/*ARGSUSED*/
int
{
"handle 0x%llx off 0x%x len 0x%x flags 0x%x\n",
/*
* No flush needed for Oberon
*/
return (DDI_SUCCESS);
/*
* jbus_stst_order is found only in certain cpu modules.
* Just return success if not present.
*/
if (&jbus_stst_order == NULL)
return (DDI_SUCCESS);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
/*
* No flush needed when sending data from memory to device.
* Nothing to do to "sync" memory to what device would already see.
*/
return (DDI_SUCCESS);
/*
* Perform necessary cpu workaround to ensure jbus ordering.
* CPU's internal "invalidate FIFOs" are flushed.
*/
#if !defined(lint)
#endif
#if !defined(lint)
#endif
return (DDI_SUCCESS);
}
/*
* MSIQ Functions:
*/
/*ARGSUSED*/
int
{
int ret;
/*
* Map the EQ memory into the Fire MMU (has to be 512KB aligned)
* and then initialize the base address register.
*
* Allocate entries from Fire IOMMU so that the resulting address
* is properly aligned. Calculate the index of the first allocated
* entry. Note: The size of the mapping is assumed to be a multiple
* of the page size.
*/
return (DDI_FAILURE);
MMU_MAP_BUF)) != DDI_SUCCESS) {
"hvio_msiq_init failed, ret 0x%lx\n", ret);
(void) px_lib_msiq_fini(dip);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
/*
* Unmap and free the EQ memory that had been mapped
* into the Fire IOMMU.
*/
/* Free the entries from the Fire MMU */
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
ra_p, *msiq_rec_cnt_p);
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msiq_getvalid failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msiq_setvalid failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msiq_getstate failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
*msiq_state);
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msiq_setstate failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msiq_gethead failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
*msiq_head);
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msiq_sethead failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msiq_gettail failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
*msiq_tail);
return (DDI_SUCCESS);
}
/*ARGSUSED*/
void
{
if (!eq_rec_p->eq_rec_fmt_type) {
/* Set msiq_rec_type to zero */
msiq_rec_p->msiq_rec_type = 0;
return;
}
"eq_rec_rid 0x%llx eq_rec_fmt_type 0x%llx "
"eq_rec_len 0x%llx eq_rec_addr0 0x%llx "
"eq_rec_addr1 0x%llx eq_rec_data0 0x%llx "
/*
* Only upper 4 bits of eq_rec_fmt_type is used
* to identify the EQ record type.
*/
case EQ_REC_MSI32:
break;
case EQ_REC_MSI64:
break;
case EQ_REC_MSG:
break;
default:
"0x%x is an unknown EQ record type",
(int)eq_rec_p->eq_rec_fmt_type);
break;
}
/* Zero out eq_rec_fmt_type field */
eq_rec_p->eq_rec_fmt_type = 0;
}
/*
* MSI Functions:
*/
/*ARGSUSED*/
int
{
ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msi_getmsiq failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
*msiq_id);
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msi_setmsiq failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msi_getvalid failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msi_setvalid failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msi_getstate failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
*msi_state);
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msi_setstate failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*
* MSG Functions:
*/
/*ARGSUSED*/
int
{
"hvio_msg_getmsiq failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
*msiq_id);
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"hvio_msg_setmsiq failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
msg_valid_state)) != H_EOK) {
"hvio_msg_getvalid failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
msg_valid_state)) != H_EOK) {
"hvio_msg_setvalid failed, ret 0x%lx\n", ret);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*
* Currently unsupported by hypervisor
*/
int
{
goto fail;
}
fail:
}
void
{
}
/*
* Generate a unique Oberon UBC ID based on the Logicial System Board and
* the IO Channel from the portid property field.
*/
static uint64_t
{
/*
* Generate a unique 6 bit UBC ID using the 2 IO_Channel#[1:0] bits and
* the 4 LSB_ID[3:0] bits from the Oberon's portid property.
*/
<< OBERON_UBC_ID_LSB));
return (ubc_id);
}
/*
* Oberon does not have a UBC scratch register, so alloc an array of scratch
* registers when needed and use a unique UBC ID as an index. This code
* can be simplified if we use a pre-allocated array. They are currently
* being dynamically allocated because it's only needed by the Oberon.
*/
static void
{
if (px_oberon_ubc_scratch_regs == NULL)
/*
* Check if any scratch registers are still in use. If all scratch
* registers are currently set to zero, then deallocate the scratch
* register array.
*/
return;
}
/*
* All scratch registers are set to zero so deallocate the scratch
* register array and set the pointer to NULL.
*/
(sizeof (uint64_t)*OBERON_UBC_ID_MAX));
}
/*
* Oberon does not have a UBC scratch register, so use an allocated array of
* scratch registers and use the unique UBC ID as an index into that array.
*/
static uint64_t
{
if (px_oberon_ubc_scratch_regs == NULL)
return (0);
return (px_oberon_ubc_scratch_regs[ubc_id]);
}
/*
* Misc Functions:
* Currently unsupported by hypervisor
*/
static uint64_t
{
/*
* Oberon does not currently have Scratchpad registers.
*/
return (oberon_get_cb(dip));
}
static void
{
/*
* Oberon does not currently have Scratchpad registers.
*/
return;
}
}
/*ARGSUSED*/
int
{
/*
* No special config space access services in this layer.
*/
return (DDI_FAILURE);
}
void
{
/* fire does not accept byte masks from PIO store merge */
}
void
{
/* Create the derr */
if (acctype == DDI_FM_ERR_EXPECTED) {
}
/* Check all child devices for errors */
/*
* PX_FATAL_HW indicates a condition recovered from Fatal-Reset,
* therefore it does not cause panic.
*/
PX_FM_PANIC("Fatal System Port Error has occurred\n");
}
#ifdef DEBUG
int px_peekfault_cnt = 0;
int px_pokefault_cnt = 0;
#endif /* DEBUG */
/*ARGSUSED*/
static int
{
int err = DDI_SUCCESS;
/* Set up protected environment. */
} else
err = DDI_FAILURE;
err = DDI_FAILURE;
/* Take down protected environment. */
no_trap();
#ifdef DEBUG
if (err == DDI_FAILURE)
#endif
return (err);
}
/*ARGSUSED*/
static int
{
int err = DDI_SUCCESS;
/*
* Note that i_ndi_busop_access_enter ends up grabbing the pokefault
* mutex.
*/
switch (size) {
case sizeof (uint8_t):
break;
case sizeof (uint16_t):
break;
case sizeof (uint32_t):
break;
case sizeof (uint64_t):
break;
}
if (flags == DDI_DEV_AUTOINCR)
err = DDI_FAILURE;
#ifdef DEBUG
#endif
break;
}
}
}
return (err);
}
int
{
}
/*ARGSUSED*/
static int
{
int err = DDI_SUCCESS;
} else
err = DDI_FAILURE;
no_trap();
#ifdef DEBUG
if (err == DDI_FAILURE)
#endif
return (err);
}
static int
{
int err = DDI_SUCCESS;
/*
* Note that i_ndi_busop_access_enter ends up grabbing the pokefault
* mutex.
*/
if (repcount == 1) {
(void *)host_addr);
} else {
int i;
for (i = 0; i < size; i++)
*ff_addr++ = 0xff;
err = DDI_FAILURE;
#ifdef DEBUG
#endif
}
} else {
(void *)host_addr);
if (flags == DDI_DEV_AUTOINCR)
}
} else {
err = DDI_FAILURE;
#ifdef DEBUG
#endif
}
}
return (err);
}
/*ARGSUSED*/
int
{
}
/*
* implements PPM interface
*/
int
{
switch (cmd) {
case PPMREQ_PRE_PWR_OFF:
/*
* Currently there is no device power management for
* the root complex (fire). When there is we need to make
* sure that it is at full power before trying to send the
* PME_Turn_Off message.
*/
"ioctl: request to send PME_Turn_Off\n");
return (px_goto_l23ready(px_p));
case PPMREQ_PRE_PWR_ON:
return (px_pre_pwron_check(px_p));
case PPMREQ_POST_PWR_ON:
return (px_goto_l0(px_p));
default:
return (DDI_FAILURE);
}
}
/*
* called by px_ioctl.
* returns DDI_SUCCESS or DDI_FAILURE
* 1. Wait for link to be in L1 state (link status reg)
* 2. write to PME_Turn_off reg to boradcast
* 3. set timeout
* 4. If timeout, return failure.
*/
static int
{
int ret = DDI_SUCCESS;
int mutex_held = 1;
/* If no PM info, return failure */
return (DDI_FAILURE);
/* Clear the PME_To_ACK receieved flag */
/*
* When P25 is the downstream device, after receiving
* PME_To_ACK, fire will go to Detect state, which causes
* the link down event. Inform FMA that this is expected.
* In case of all other cards complaint with the pci express
* spec, this will happen when the power is re-applied. FMA
* code will clear this flag after one instance of LDN. Since
* there will not be a LDN event for the spec compliant cards,
* we need to clear the flag after receiving PME_To_ACK.
*/
ret = DDI_FAILURE;
goto l23ready_done;
}
/*
* if cv_timedwait returns -1, it is either
* 1) timed out or
* 2) there was a pre-mature wakeup but by the time
* cv_timedwait is called again end < lbolt i.e.
* end is in the past.
* 3) By the time we make first cv_timedwait call,
* end < lbolt is true.
*/
if (timeleft == -1)
break;
}
/*
* Either timedout or interrupt didn't get a
* chance to grab the mutex and set the flag.
* release the mutex and delay for sometime.
* This will 1) give a chance for interrupt to
* set the flag 2) creates a delay between two
* consequetive requests.
*/
mutex_held = 0;
ret = DDI_FAILURE;
" for PME_TO_ACK\n");
}
}
px_p->px_pm_flags &=
if (mutex_held)
/*
* Wait till link is in L1 idle, if sending PME_Turn_Off
* was succesful.
*/
if (ret == DDI_SUCCESS) {
" even though we received PME_To_ACK.\n");
/*
* Workaround for hardware bug with P25.
* Due to a hardware bug with P25, link state
* will be Detect state rather than L1 after
* link is transitioned to L23Ready state. Since
* we don't know whether link is L23ready state
* without Fire's state being L1_idle, we delay
* here just to make sure that we wait till link
* is transitioned to L23Ready state.
*/
}
}
return (ret);
}
/*
* Message interrupt handler intended to be shared for both
* PME and PME_TO_ACK msg handling, currently only handles
* PME_To_ACK message.
*/
{
} else {
/*
* This maybe the second ack received. If so then,
* we should be receiving it during wait4L1 stage.
*/
}
return (DDI_INTR_CLAIMED);
}
static int
{
/* If no PM info, return failure */
return (DDI_FAILURE);
/*
* For the spec compliant downstream cards link down
* is expected when the device is powered on.
*/
}
static int
{
int ret = DDI_SUCCESS;
uint64_t time_spent = 0;
/* If no PM info, return failure */
return (DDI_FAILURE);
/*
* The following link retrain activity will cause LDN and LUP event.
* Receiving LDN prior to receiving LUP is expected, not an error in
* this case. Receiving LUP indicates link is fully up to support
* powering up down stream device, and of course any further LDN and
* LUP outside this context will be error.
*/
ret = DDI_FAILURE;
goto l0_done;
}
/* LUP event takes the order of 15ms amount of time to occur */
if (px_p->px_lup_pending)
ret = DDI_FAILURE;
if (ret == DDI_SUCCESS)
return (ret);
}
/*
* Extract the drivers binding name to identify which chip we're binding to.
* Whenever a new bus bridge is created, the driver alias entry should be
* added here to identify the device if needed. If a device isn't added,
* the identity defaults to PX_CHIP_UNIDENTIFIED.
*/
static uint32_t
{
"module-revision#", 0);
/* Check for Fire driver binding name */
}
/* Check for Oberon driver binding name */
}
return (PX_CHIP_UNIDENTIFIED);
}
int
{
return (DDI_SUCCESS);
}
void
{
}
/*
* px_cb_add_intr() - Called from attach(9E) to create CB if not yet
* created, to add CB interrupt vector always, but enable only once.
*/
int
{
} else
cpuid = intr_dist_cpuid(),
} else {
/*
* Find the last pxl or
* stop short at encoutering a redundent, or
* both.
*/
return (DDI_FAILURE);
}
/* add to linked list */
}
return (DDI_SUCCESS);
}
/*
* px_cb_rem_intr() - Called from detach(9E) to remove its CB
* interrupt vector, to shift proxy to the next available px,
* or disable CB interrupt when itself is the last.
*/
void
{
/* De-list the target px, move the next px up */
} else {
if (!pxl) {
"in registered CB list.", (void *)px_p);
return;
}
}
}
}
return;
}
}
/*
* px_cb_intr() - sun4u only, CB interrupt dispatcher
*/
{
}
if (pxp) {
} else
return (DDI_INTR_UNCLAIMED);
}
/*
* px_cb_intr_redist() - sun4u only, CB interrupt redistribution
*/
void
{
return;
}
}
#ifdef FMA
void
{
/* populate the rc_status by reading the registers - TBD */
}
#endif /* FMA */
/*
* Only used for temporary PCI-E Fabric Error Handling.
*/
{
/* Get Fire's Physical Base Address */
/* Get config space first. */
}
void
/* Get Fire's Physical Base Address */
/* Get config space first. */
}
/*
* cpr callback
*
* disable fabric error msg interrupt prior to suspending
* all device drivers; re-enable fabric error msg interrupt
* after all devices are resumed.
*/
static boolean_t
{
switch (code) {
case CB_CODE_CPR_CHKPT:
imu_log_enable & (~imu_log_mask));
imu_intr_enable & (~imu_intr_mask));
/* disable CORR intr mapping */
/* disable NON FATAL intr mapping */
/* disable FATAL intr mapping */
break;
case CB_CODE_CPR_RESUME:
/* enable CORR intr mapping */
if (ce_ino_p)
else
"reenable PCIe Correctable msg intr.\n");
/* enable NON FATAL intr mapping */
if (nf_ino_p)
else
"reenable PCIe Non Fatal msg intr.\n");
/* enable FATAL intr mapping */
if (f_ino_p)
else
"reenable PCIe Fatal msg intr.\n");
(imu_log_mask & px_imu_log_mask)));
(imu_intr_mask & px_imu_intr_mask)));
break;
}
return (B_TRUE);
}
/*
* fetch chip's range propery's value
*/
{
switch (PX_CHIP_TYPE(pxu_p)) {
case PX_CHIP_OBERON:
break;
case PX_CHIP_FIRE:
break;
default:
}
return (range_prop);
}
/*
* add cpr callback
*/
void
{
CB_CL_CPR_POST_USER, "px_cpr");
}
/*
* remove cpr callback
*/
void
{
}
/*ARGSUSED*/
static uint_t
{
int rval;
#ifdef DEBUG
if (rval == DDI_INTR_UNCLAIMED)
#endif
return (rval);
}
int
{
DDI_SUCCESS) {
#ifdef DEBUG
#endif
return (DDI_FAILURE);
}
}
return (ret);
}
void
{
DDI_SUCCESS) {
#ifdef DEBUG
#endif
return;
}
}
}