px_hlib.c revision 1f4643f9130cd5a36ddbe698eb88302e44570813
0N/A * The contents of this file are subject to the terms of the 0N/A * Common Development and Distribution License (the "License"). 919N/A * You may not use this file except in compliance with the License. 919N/A * See the License for the specific language governing permissions 919N/A * and limitations under the License. 919N/A * When distributing Covered Code, include this CDDL HEADER in each 919N/A * If applicable, add the following below this CDDL HEADER, with the 919N/A * fields enclosed by brackets "[]" replaced with your own identifying 919N/A * information: Portions Copyright [yyyy] [name of copyright owner] 919N/A * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 0N/A * Use is subject to license terms. 493N/A#
pragma ident "%Z%%M% %I% %E% SMI" 970N/A * Registers in the PEC Module. 970N/A * LPU_RESET should be set to 0ull during resume 851N/A * This array is in reg,chip form. PX_CHIP_UNIDENTIFIED is for all chips 851N/A * or PX_CHIP_FIRE for Fire only, or PX_CHIP_OBERON for Oberon only. 0N/A * Registers for the MMU module. 493N/A * MMU_TTE_CACHE_INVALIDATE needs to be cleared. (-1ull) 493N/A * Registers for the IB Module 493N/A * Registers for the JBC module. 591N/A * JBC_ERROR_STATUS_CLEAR needs to be cleared. (-1ull) 922N/A * Registers for the UBC module. 810N/A * UBC_ERROR_STATUS_CLEAR needs to be cleared. (-1ull) 922N/A/* OPL tuning variables for link unstable issue */ 493N/A * Initialize the bus, but do not enable interrupts. 970N/A * Initialize the JBC module, but do not enable interrupts. 963N/A /* Check if we need to enable inverted parity */ 911N/A * Enable merge, jbc and dmc interrupts. 493N/A "jbc_init, JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE: 0x%llx\n",
911N/A * CSR_V JBC's interrupt regs (log, enable, status, clear) 1061N/A * Initialize the UBC module, but do not enable interrupts. 1061N/A * Enable Uranus bus error log bits. 935N/A * Clear Uranus bus errors. 911N/A * CSR_V UBC's interrupt regs (log, enable, status, clear) 1179N/A * Initialize the module, but do not enable interrupts. 935N/A * CSR_V IB's interrupt regs (log, enable, status, clear) 911N/A * Initialize the module, but do not enable interrupts. 493N/A * CSR_V ILU's interrupt regs (log, enable, status, clear) 1088N/A * Initialize the module, but do not enable interrupts. 1088N/A * CSR_V TLU_CONTROL Expect OBP ??? 1088N/A * L0s entry default timer value - 7.0 us 1088N/A * Completion timeout select default value - 67.1 ms and 1088N/A * Configuration - Bit 0 should always be 0 for upstream port. 1088N/A * Bit 1 is clock - how is this related to the clock bit in TLU 1088N/A * Link Control register? Both are hardware dependent and likely 1088N/A * NOTE: Do not set the NPWR_EN bit. The desired value of this bit 0N/A * For Oberon, NPWR_EN is set to 0 to prevent PIO reads from blocking 963N/A * behind non-posted PIO writes. This blocking could cause a master or 963N/A * slave timeout on the host bus if multiple serialized PIOs were to 963N/A * suffer Completion Timeouts because the CTO delays for each PIO ahead 935N/A * of the read would accumulate. Since the Olympus processor can have 935N/A * only 1 PIO outstanding, there is no possibility of PIO accesses from 935N/A * a given CPU to a given device being re-ordered by the PCIe fabric; 935N/A * therefore turning off serialization should be safe from a PCIe 935N/A * ordering perspective. 935N/A * Set Detect.Quiet. This will disable automatic link 935N/A * re-training, if the link goes down e.g. power management 493N/A * turns off power to the downstream device. This will enable 493N/A * Fire to go to Drain state, after link down. The drain state 1228N/A * forces a reset to the FC state machine, which is required for 493N/A * proper link re-training. 935N/A * CSR_V TLU_STATUS Expect HW 0x4 935N/A * Only bit [7:0] are currently defined. Bits [2:0] 935N/A * are the state, which should likely be in state active, 935N/A * 100b. Bit three is 'recovery', which is not understood. 935N/A * All other bits are reserved. 935N/A * CSR_V TLU_PME_TURN_OFF_GENERATE Expect HW 0x0 935N/A * CSR_V TLU_INGRESS_CREDITS_INITIAL Expect HW 0x10000200C0 935N/A * Ingress credits initial register. Bits [39:32] should be 935N/A * 0x10, bits [19:12] should be 0x20, and bits [11:0] should 935N/A * be 0xC0. These are the reset values, and should be set by 922N/A * CSR_V TLU_DIAGNOSTIC Expect HW 0x0 922N/A * Diagnostic register - always zero unless we are debugging. 935N/A * CSR_V TLU_EGRESS_CREDITS_CONSUMED Expect HW 0x0 935N/A * CSR_V TLU_EGRESS_CREDIT_LIMIT Expect HW 0x0 947N/A * CSR_V TLU_EGRESS_RETRY_BUFFER Expect HW 0x0 947N/A * CSR_V TLU_INGRESS_CREDITS_ALLOCATED Expected HW 0x0 967N/A "tlu_init - TLU_INGRESS_CREDITS_ALLOCATED: 0x%llx\n",
935N/A * CSR_V TLU_INGRESS_CREDITS_RECEIVED Expected HW 0x0 935N/A "tlu_init - TLU_INGRESS_CREDITS_RECEIVED: 0x%llx\n",
935N/A * CSR_V TLU's interrupt regs (log, enable, status, clear) 935N/A "tlu_init - TLU_OTHER_EVENT_LOG_ENABLE: 0x%llx\n",
935N/A "tlu_init - TLU_OTHER_EVENT_INTERRUPT_ENABLE: 0x%llx\n",
935N/A "tlu_init - TLU_OTHER_EVENT_INTERRUPT_STATUS: 0x%llx\n",
935N/A "tlu_init - TLU_OTHER_EVENT_STATUS_CLEAR: 0x%llx\n",
191N/A * CSR_V TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG Expect HW 0x0 1298N/A "tlu_init - TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG: 0x%llx\n",
599N/A * CSR_V TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG Expect HW 0x0 493N/A "tlu_init - TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG: 0x%llx\n",
493N/A * CSR_V TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG Expect HW 0x0 810N/A "tlu_init - TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG: 0x%llx\n",
493N/A * CSR_V TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG Expect HW 0x0 494N/A "tlu_init - TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG: 0x%llx\n",
493N/A * CSR_V TLU_PERFORMANCE_COUNTER_SELECT Expect HW 0x0 191N/A "tlu_init - TLU_PERFORMANCE_COUNTER_SELECT: 0x%llx\n",
1111N/A * CSR_V TLU_PERFORMANCE_COUNTER_ZERO Expect HW 0x0 493N/A "tlu_init - TLU_PERFORMANCE_COUNTER_ZERO: 0x%llx\n",
1276N/A * CSR_V TLU_PERFORMANCE_COUNTER_ONE Expect HW 0x0 1276N/A * CSR_V TLU_PERFORMANCE_COUNTER_TWO Expect HW 0x0 1276N/A * CSR_V TLU_DEBUG_SELECT_A Expect HW 0x0 493N/A * CSR_V TLU_DEBUG_SELECT_B Expect HW 0x0 493N/A * CSR_V TLU_DEVICE_CAPABILITIES Expect HW 0xFC2 493N/A * CSR_V TLU_DEVICE_CONTROL Expect HW 0x0 493N/A * Bits [14:12] are the Max Read Request Size, which is always 64 493N/A * bytes which is 000b. Bits [7:5] are Max Payload Size, which 493N/A * start at 128 bytes which is 000b. This may be revisited if 493N/A * init_child finds greater values. 1296N/A * CSR_V TLU_DEVICE_STATUS Expect HW 0x0 1354N/A * CSR_V TLU_LINK_CAPABILITIES Expect HW 0x15C81 1296N/A * CSR_V TLU_LINK_CONTROL Expect OBP 0x40 493N/A * The CLOCK bit should be set by OBP if the hardware dictates, 1124N/A * and if it is set then ASPM should be used since then L0s exit 1124N/A * latency should be lower than L1 exit latency. 493N/A * Note that we will not enable power management during bringup 1124N/A * since it has not been test and is creating some problems in 493N/A * CSR_V TLU_LINK_STATUS Expect OBP 0x1011 1124N/A * Not sure if HW or OBP will be setting this read only 1132N/A * register. Bit 12 is Clock, and it should always be 1 493N/A * signifying that the component uses the same physical 1124N/A * clock as the platform. Bits [9:4] are for the width, 1124N/A * with the expected value above signifying a x1 width. 493N/A * Bits [3:0] are the speed, with 1b signifying 2.5 Gb/s, 935N/A * the only speed as yet supported by the PCI-E spec. 705N/A * CSR_V TLU_SLOT_CAPABILITIES Expect OBP ??? 837N/A * Power Limits for the slots. Will be platform 606N/A * dependent, and OBP will need to set after consulting 910N/A * Bits [16:15] are power limit scale, which most likely 910N/A * will be 0b signifying 1x. Bits [14:7] are the Set 606N/A * Power Limit Value, which is a number which is multiplied 606N/A * by the power limit scale to get the actual power limit. 935N/A * CSR_V TLU_UNCORRECTABLE_ERROR_LOG_ENABLE Expect Kernel 0x17F011 606N/A "tlu_init - TLU_UNCORRECTABLE_ERROR_LOG_ENABLE: 0x%llx\n",
970N/A * CSR_V TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE Expect 970N/A * Kernel 0x17F0110017F011 970N/A "tlu_init - TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE: 0x%llx\n",
970N/A * CSR_V TLU_UNCORRECTABLE_ERROR_INTERRUPT_STATUS Expect HW 0x0 970N/A "tlu_init - TLU_UNCORRECTABLE_ERROR_INTERRUPT_STATUS: 0x%llx\n",
970N/A * CSR_V TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR Expect HW 0x0 970N/A "tlu_init - TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR: 0x%llx\n",
591N/A * CSR_V TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG HW 0x0 1071N/A "tlu_init - TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG: 0x%llx\n",
1071N/A * CSR_V TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG HW 0x0 1071N/A "tlu_init - TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG: 0x%llx\n",
810N/A * CSR_V TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG HW 0x0 591N/A "tlu_init - TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG: 0x%llx\n",
970N/A * CSR_V TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG HW 0x0 970N/A "tlu_init - TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG: 0x%llx\n",
970N/A * CSR_V TLU's CE interrupt regs (log, enable, status, clear) 970N/A * CSR_V TLU_CORRECTABLE_ERROR_LOG_ENABLE Expect Kernel 0x11C1 970N/A "tlu_init - TLU_CORRECTABLE_ERROR_LOG_ENABLE: 0x%llx\n",
1172N/A * CSR_V TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE Kernel 0x11C1000011C1 970N/A "tlu_init - TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE: 0x%llx\n",
970N/A * CSR_V TLU_CORRECTABLE_ERROR_INTERRUPT_STATUS Expect HW 0x0 970N/A "tlu_init - TLU_CORRECTABLE_ERROR_INTERRUPT_STATUS: 0x%llx\n",
970N/A * CSR_V TLU_CORRECTABLE_ERROR_STATUS_CLEAR Expect HW 0x0 493N/A "tlu_init - TLU_CORRECTABLE_ERROR_STATUS_CLEAR: 0x%llx\n",
1201N/A /* Variables used to set the ACKNAK Latency Timer and Replay Timer */ 1201N/A * ACKNAK Latency Threshold Table. 1201N/A * See Fire PRM 2.0 section 1.2.12.2, table 1-17. 1201N/A {
0x42F,
0x11A,
0x96,
0x96},
1201N/A {
0x82F,
0x21A,
0x116,
0x116},
1201N/A {
0x102F,
0x41A,
0x216,
0x216}
90N/A * TxLink Replay Timer Latency Table 90N/A * See Fire PRM 2.0 sections 1.2.12.3, table 1-18. 47N/A {
0x379,
0x112,
0xFC,
0xB4},
47N/A {
0x618,
0x1BA,
0x192,
0x10E},
47N/A {
0x831,
0x242,
0x143,
0x143},
47N/A {
0xFB1,
0x422,
0x233,
0x233},
47N/A {
0x1EB0,
0x7E1,
0x412,
0x412},
935N/A {
0x3CB0,
0xF61,
0x7D2,
0x7D2}
47N/A * Get the Link Width. See table above LINK_WIDTH_ARR_SIZE #define 47N/A * Only Link Widths of x1, x4, and x8 are supported. 922N/A * If any width is reported other than x8, set default to x8. 935N/A * Convert link_width to match timer array configuration. 606N/A * Get the Max Payload Size. 606N/A * See table above LINK_MAX_PKT_ARR_SIZE #define 970N/A /* Make sure the packet size is not greater than 4096 */ 970N/A * CSR_V LPU_ID Expect HW 0x0 970N/A * This register has link id, phy id and gigablaze id. 1123N/A * CSR_V LPU_RESET Expect Kernel 0x0 1123N/A * No reason to have any reset bits high until an error is 1123N/A * CSR_V LPU_DEBUG_STATUS Expect HW 0x0 1105N/A * Bits [15:8] are Debug B, and bit [7:0] are Debug A. 970N/A * They are read-only. What do the 8 bits mean, and 970N/A * how do they get set if they are read only? 970N/A * CSR_V LPU_DEBUG_CONFIG Expect Kernel 0x0 970N/A * CSR_V LPU_LTSSM_CONTROL Expect HW 0x0 1162N/A * CSR_V LPU_LINK_STATUS Expect HW 0x101 970N/A * This register has bits [9:4] for link width, and the 970N/A * default 0x10, means a width of x16. The problem is 970N/A * this width is not supported according to the TLU 970N/A * link status register. 970N/A * CSR_V LPU_INTERRUPT_STATUS Expect HW 0x0 1302N/A * CSR_V LPU_INTERRUPT_MASK Expect HW 0x0 387N/A * CSR_V LPU_LINK_PERFORMANCE_COUNTER_SELECT Expect HW 0x0 355N/A "lpu_init - LPU_LINK_PERFORMANCE_COUNTER_SELECT: 0x%llx\n",
1003N/A * CSR_V LPU_LINK_PERFORMANCE_COUNTER_CONTROL Expect HW 0x0 1003N/A "lpu_init - LPU_LINK_PERFORMANCE_COUNTER_CONTROL: 0x%llx\n",
1302N/A * CSR_V LPU_LINK_PERFORMANCE_COUNTER1 Expect HW 0x0 1302N/A "lpu_init - LPU_LINK_PERFORMANCE_COUNTER1: 0x%llx\n",
1302N/A * CSR_V LPU_LINK_PERFORMANCE_COUNTER1_TEST Expect HW 0x0 1302N/A "lpu_init - LPU_LINK_PERFORMANCE_COUNTER1_TEST: 0x%llx\n",
1302N/A * CSR_V LPU_LINK_PERFORMANCE_COUNTER2 Expect HW 0x0 1003N/A "lpu_init - LPU_LINK_PERFORMANCE_COUNTER2: 0x%llx\n",
1003N/A * CSR_V LPU_LINK_PERFORMANCE_COUNTER2_TEST Expect HW 0x0 1003N/A "lpu_init - LPU_LINK_PERFORMANCE_COUNTER2_TEST: 0x%llx\n",
1003N/A * CSR_V LPU_LINK_LAYER_CONFIG Expect HW 0x100 1003N/A * This is another place where Max Payload can be set, 1003N/A * this time for the link layer. It will be set to 1003N/A * 128B, which is the default, but this will need to 1003N/A * CSR_V LPU_LINK_LAYER_STATUS Expect OBP 0x5 970N/A * Another R/W status register. Bit 3, DL up Status, will 922N/A * be set high. The link state machine status bits [2:0] 1302N/A * are set to 0x1, but the status bits are not defined in the 922N/A * PRM. What does 0x1 mean, what others values are possible 970N/A * and what are thier meanings? 970N/A * This register has been giving us problems in simulation. 1003N/A * It has been mentioned that software should not program 493N/A * any registers with WE bits except during debug. So 1003N/A * this register will no longer be programmed. 1296N/A * CSR_V LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST Expect HW 0x0 1296N/A "lpu_init - LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST: 0x%llx\n",
* CSR_V LPU Link Layer interrupt regs (mask, status) "lpu_init - LPU_LINK_LAYER_INTERRUPT_MASK: 0x%llx\n",
"lpu_init - LPU_LINK_LAYER_INTERRUPT_AND_STATUS: 0x%llx\n",
* CSR_V LPU_FLOW_CONTROL_UPDATE_CONTROL Expect OBP 0x7 * The PRM says that only the first two bits will be set * high by default, which will enable flow control for * posted and non-posted updates, but NOT completetion "lpu_init - LPU_FLOW_CONTROL_UPDATE_CONTROL: 0x%llx\n",
* CSR_V LPU_LINK_LAYER_FLOW_CONTROL_UPDATE_TIMEOUT_VALUE * This should be set by OBP. We'll check to make sure. "LPU_LINK_LAYER_FLOW_CONTROL_UPDATE_TIMEOUT_VALUE: 0x%llx\n",
* CSR_V LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER0 Expect OBP ??? * This register has Flow Control Update Timer values for * non-posted and posted requests, bits [30:16] and bits * [14:0], respectively. These are read-only to SW so * either HW or OBP needs to set them. "LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER0: 0x%llx\n",
* CSR_V LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER1 Expect OBP ??? * Same as timer0 register above, except for bits [14:0] * have the timer values for completetions. Read-only to * SW; OBP or HW need to set it. "LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER1: 0x%llx\n",
* CSR_V LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD "LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD: 0x%llx\n",
* CSR_V LPU_TXLINK_ACKNAK_LATENCY_TIMER Expect HW 0x0 "lpu_init - LPU_TXLINK_ACKNAK_LATENCY_TIMER: 0x%llx\n",
* CSR_V LPU_TXLINK_REPLAY_TIMER_THRESHOLD "lpu_init - LPU_TXLINK_REPLAY_TIMER_THRESHOLD: 0x%llx\n",
* CSR_V LPU_TXLINK_REPLAY_TIMER Expect HW 0x0 * CSR_V LPU_TXLINK_REPLAY_NUMBER_STATUS Expect OBP 0x3 "lpu_init - LPU_TXLINK_REPLAY_NUMBER_STATUS: 0x%llx\n",
* CSR_V LPU_REPLAY_BUFFER_MAX_ADDRESS Expect OBP 0xB3F "lpu_init - LPU_REPLAY_BUFFER_MAX_ADDRESS: 0x%llx\n",
* CSR_V LPU_TXLINK_RETRY_FIFO_POINTER Expect OBP 0xFFFF0000 "lpu_init - LPU_TXLINK_RETRY_FIFO_POINTER: 0x%llx\n",
* CSR_V LPU_TXLINK_RETRY_FIFO_R_W_POINTER Expect OBP 0x0 "lpu_init - LPU_TXLINK_RETRY_FIFO_R_W_POINTER: 0x%llx\n",
* CSR_V LPU_TXLINK_RETRY_FIFO_CREDIT Expect HW 0x1580 "lpu_init - LPU_TXLINK_RETRY_FIFO_CREDIT: 0x%llx\n",
* CSR_V LPU_TXLINK_SEQUENCE_COUNTER Expect OBP 0xFFF0000 DBG(
DBG_LPU,
NULL,
"lpu_init - LPU_TXLINK_SEQUENCE_COUNTER: 0x%llx\n",
* CSR_V LPU_TXLINK_ACK_SENT_SEQUENCE_NUMBER Expect HW 0xFFF "lpu_init - LPU_TXLINK_ACK_SENT_SEQUENCE_NUMBER: 0x%llx\n",
* CSR_V LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR Expect OBP 0x157 * Test only register. Will not be programmed. "lpu_init - LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR: 0x%llx\n",
* CSR_V LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS Expect HW 0xFFF0000 * Test only register. Will not be programmed. "lpu_init - LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS: 0x%llx\n",
* CSR_V LPU_TXLINK_SEQUENCE_COUNT_R_W_POINTERS Expect HW 0x0 "lpu_init - LPU_TXLINK_SEQUENCE_COUNT_R_W_POINTERS: 0x%llx\n",
* CSR_V LPU_TXLINK_TEST_CONTROL Expect HW 0x0 * CSR_V LPU_TXLINK_MEMORY_ADDRESS_CONTROL Expect HW 0x0 * Test only register. Will not be programmed. "lpu_init - LPU_TXLINK_MEMORY_ADDRESS_CONTROL: 0x%llx\n",
* CSR_V LPU_TXLINK_MEMORY_DATA_LOAD0 Expect HW 0x0 "lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD0: 0x%llx\n",
* CSR_V LPU_TXLINK_MEMORY_DATA_LOAD1 Expect HW 0x0 "lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD1: 0x%llx\n",
* CSR_V LPU_TXLINK_MEMORY_DATA_LOAD2 Expect HW 0x0 "lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD2: 0x%llx\n",
* CSR_V LPU_TXLINK_MEMORY_DATA_LOAD3 Expect HW 0x0 "lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD3: 0x%llx\n",
* CSR_V LPU_TXLINK_MEMORY_DATA_LOAD4 Expect HW 0x0 "lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD4: 0x%llx\n",
* CSR_V LPU_TXLINK_RETRY_DATA_COUNT Expect HW 0x0 * Test only register. Will not be programmed. DBG(
DBG_LPU,
NULL,
"lpu_init - LPU_TXLINK_RETRY_DATA_COUNT: 0x%llx\n",
* CSR_V LPU_TXLINK_SEQUENCE_BUFFER_COUNT Expect HW 0x0 * Test only register. Will not be programmed. "lpu_init - LPU_TXLINK_SEQUENCE_BUFFER_COUNT: 0x%llx\n",
* CSR_V LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA Expect HW 0x0 "lpu_init - LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA: 0x%llx\n",
* CSR_V LPU_RXLINK_NEXT_RECEIVE_SEQUENCE_1_COUNTER Expect HW 0x0 "LPU_RXLINK_NEXT_RECEIVE_SEQUENCE_1_COUNTER: 0x%llx\n",
* CSR_V LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED Expect HW 0x0 "lpu_init - LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED: 0x%llx\n",
* CSR_V LPU_RXLINK_TEST_CONTROL Expect HW 0x0 * CSR_V LPU_PHYSICAL_LAYER_CONFIGURATION Expect HW 0x10 "lpu_init - LPU_PHYSICAL_LAYER_CONFIGURATION: 0x%llx\n",
* CSR_V LPU_PHY_LAYER_STATUS Expect HW 0x0 * CSR_V LPU_PHY_INTERRUPT_AND_STATUS_TEST Expect HW 0x0 "lpu_init - LPU_PHY_INTERRUPT_AND_STATUS_TEST: 0x%llx\n",
* CSR_V LPU PHY LAYER interrupt regs (mask, status) "lpu_init - LPU_PHY_LAYER_INTERRUPT_AND_STATUS: 0x%llx\n",
* CSR_V LPU_RECEIVE_PHY_CONFIG Expect HW 0x0 * This also needs some explanation. What is the best value * for the water mark? Test mode enables which test mode? * Programming model needed for the Receiver Reset Lane N * CSR_V LPU_RECEIVE_PHY_STATUS1 Expect HW 0x0 * CSR_V LPU_RECEIVE_PHY_STATUS2 Expect HW 0x0 * CSR_V LPU_RECEIVE_PHY_STATUS3 Expect HW 0x0 * CSR_V LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_TEST Expect HW 0x0 "lpu_init - LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_TEST: 0x%llx\n",
* CSR_V LPU RX LAYER interrupt regs (mask, status) "lpu_init - LPU_RECEIVE_PHY_INTERRUPT_MASK: 0x%llx\n",
"lpu_init - LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS: 0x%llx\n",
* CSR_V LPU_TRANSMIT_PHY_CONFIG Expect HW 0x0 * CSR_V LPU_TRANSMIT_PHY_STATUS Expect HW 0x0 * CSR_V LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_TEST Expect HW 0x0 "lpu_init - LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_TEST: 0x%llx\n",
* CSR_V LPU TX LAYER interrupt regs (mask, status) "lpu_init - LPU_TRANSMIT_PHY_INTERRUPT_MASK: 0x%llx\n",
"lpu_init - LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS: 0x%llx\n",
* CSR_V LPU_TRANSMIT_PHY_STATUS_2 Expect HW 0x0 * CSR_V LPU_LTSSM_CONFIG1 Expect OBP 0x205 * The new PRM has values for LTSSM 8 ns timeout value and * LTSSM 20 ns timeout value. But what do these values mean? * Most of the other bits are questions as well. * As such we will use the reset value. * CSR_V LPU_LTSSM_CONFIG2 Expect OBP 0x2DC6C0 * Again, what does '12 ms timeout value mean'? * CSR_V LPU_LTSSM_CONFIG3 Expect OBP 0x7A120 * CSR_V LPU_LTSSM_CONFIG4 Expect OBP 0x21300 * CSR_V LPU_LTSSM_CONFIG5 Expect OBP 0x0 * CSR_V LPU_LTSSM_STATUS1 Expect OBP 0x0 * LTSSM Status registers are test only. * CSR_V LPU_LTSSM_STATUS2 Expect OBP 0x0 * CSR_V LPU_LTSSM_INTERRUPT_AND_STATUS_TEST Expect HW 0x0 "lpu_init - LPU_LTSSM_INTERRUPT_AND_STATUS_TEST: 0x%llx\n",
* CSR_V LPU LTSSM LAYER interrupt regs (mask, status) "lpu_init - LPU_LTSSM_INTERRUPT_AND_STATUS: 0x%llx\n",
* CSR_V LPU_LTSSM_STATUS_WRITE_ENABLE Expect OBP 0x0 "lpu_init - LPU_LTSSM_STATUS_WRITE_ENABLE: 0x%llx\n",
* CSR_V LPU_GIGABLAZE_GLUE_CONFIG1 Expect OBP 0x88407 * CSR_V LPU_GIGABLAZE_GLUE_CONFIG2 Expect OBP 0x35 * CSR_V LPU_GIGABLAZE_GLUE_CONFIG3 Expect OBP 0x4400FA * CSR_V LPU_GIGABLAZE_GLUE_CONFIG4 Expect OBP 0x1E848 * CSR_V LPU_GIGABLAZE_GLUE_STATUS Expect OBP 0x0 * CSR_V LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_TEST Expect OBP 0x0 "LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_TEST: 0x%llx\n",
* CSR_V LPU GIGABLASE LAYER interrupt regs (mask, status) "lpu_init - LPU_GIGABLAZE_GLUE_INTERRUPT_MASK: 0x%llx\n",
"lpu_init - LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS: 0x%llx\n",
* CSR_V LPU_GIGABLAZE_GLUE_POWER_DOWN1 Expect HW 0x0 "lpu_init - LPU_GIGABLAZE_GLUE_POWER_DOWN1: 0x%llx\n",
* CSR_V LPU_GIGABLAZE_GLUE_POWER_DOWN2 Expect HW 0x0 "lpu_init - LPU_GIGABLAZE_GLUE_POWER_DOWN2: 0x%llx\n",
* CSR_V LPU_GIGABLAZE_GLUE_CONFIG5 Expect OBP 0x0 * CSR_V DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE Expect OBP 0x8000000000000003 "dmc_init - DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE: 0x%llx\n",
* CSR_V DMC_CORE_AND_BLOCK_ERROR_STATUS Expect HW 0x0 "dmc_init - DMC_CORE_AND_BLOCK_ERROR_STATUS: 0x%llx\n",
* CSR_V DMC_DEBUG_SELECT_FOR_PORT_A Expect HW 0x0 DBG(
DBG_DMC,
NULL,
"dmc_init - DMC_DEBUG_SELECT_FOR_PORT_A: 0x%llx\n",
* CSR_V DMC_DEBUG_SELECT_FOR_PORT_B Expect HW 0x0 DBG(
DBG_DMC,
NULL,
"dmc_init - DMC_DEBUG_SELECT_FOR_PORT_B: 0x%llx\n",
* CSR_V PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE Expect Kernel 0x800000000000000F "hvio_pec_init - PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE: 0x%llx\n",
* CSR_V PEC_CORE_AND_BLOCK_INTERRUPT_STATUS Expect HW 0x0 "hvio_pec_init - PEC_CORE_AND_BLOCK_INTERRUPT_STATUS: 0x%llx\n",
* Convert a TTE to physical address * Return MMU bypass noncache bit for chip "mmu_bypass_nocache - unknown chip type: 0x%x\n",
* Calculate number of TSB entries for the chip. * Initialize the module, but do not enable interrupts. * Invalidate the TLB through the diagnostic register. * Configure the Fire MMU TSB Control Register. Determine * the encoding for either 8KB pages (0) or 64KB pages (1). * Write the most significant 30 bits of the TSB physical address * and the encoded TSB table size. * Enable the MMU, set the "TSB Cache Snoop Enable", * the "Cache Mode", the "Bypass Enable" and * the "Translation Enable" bits. * Read the register here to ensure that the previous writes to * the Fire MMU registers have been flushed. (Technically, this * is not entirely necessary here as we will likely do later reads * during Fire initialization, but it is a small price to pay for * CSR_V TLU's UE interrupt regs (log, enable, status, clear) * Oberon will need to flush the corresponding TTEs in * Cache. We only need to flush every cache line. * Extra PIO's are expensive. * Oberon will need to flush the corresponding TTEs in * Cache. We only need to flush every cache line. * Extra PIO's are expensive. * Oberon will need to flush the corresponding TTEs in * Cache. We only need to flush every cache line. * Extra PIO's are expensive. "hvio_get_bypass_base - unknown chip type: 0x%x\n",
"hvio_get_bypass_end - unknown chip type: 0x%x\n",
* Generic IO Interrupt Servies * Converts a device specific interrupt number given by the * arguments devhandle and devino into a system specific ino. * Returns state in intr_valid_state if the interrupt defined by sysino * is valid (enabled) or not-valid (disabled). * Sets the 'valid' state of the interrupt defined by * the argument sysino to the state defined by the * argument intr_valid_state. * Returns the current state of the interrupt given by the sysino * Sets the current state of the interrupt given by the sysino * argument to the value given in the argument intr_state. * Note: Setting the state to INTR_IDLE clears any pending * Returns the cpuid that is the current target of the * interrupt given by the sysino argument. * The cpuid value returned is undefined if the target * has not been set via intr_settarget. * Set the target cpu for the interrupt defined by the argument * sysino to the target cpu value defined by the argument cpuid. * For now, we assign interrupt controller in a round * robin fashion. Later, we may need to come up with * a more efficient assignment algorithm. /* For EQ interrupts, set DATA MONDO bit */ "hvio_msiq_init: EVENT_QUEUE_BASE_ADDRESS 0x%llx\n",
"INTERRUPT_MONDO_DATA_0: 0x%llx\n",
/* PCI MEM 32 resources to perform 32 bit MSI transactions */ DBG(
DBG_IB,
NULL,
"hvio_msiq_init: MSI_32_BIT_ADDRESS: 0x%llx\n",
/* Reserve PCI MEM 64 resources to perform 64 bit MSI transactions */ DBG(
DBG_IB,
NULL,
"hvio_msiq_init: MSI_64_BIT_ADDRESS: 0x%llx\n",
* Registers saved have all been touched in the XXX_init functions. * uint64_t *pec_config_state; * uint64_t *mmu_config_state; * uint64_t *ib_config_state; * uint64_t *xcb_config_state; /* Save the PEC configuration states */ /* Save the MMU configuration states */ /* Save the interrupt mapping registers */ /* Save the IB configuration states */ /* Make sure that suspend actually did occur */ /* Restore IB configuration states */ * Restore the interrupt mapping registers * And make sure the intrs are idle. /* Restore MMU configuration states */ /* Restore PEC configuration states */ /* Make sure all reset bits are low until error is detected */ /* Enable PCI-E interrupt */ /* Save the configuration states */ * No reason to have any reset bits high until an error is * No reason to have any reset bits high until an error is /* Restore the configuration states */ /* Enable XBC interrupt */ /* Save MSI mapping registers */ /* Save all other MSIQ registers */ * Initialize EQ base address register and * Interrupt Mondo Data 0 register. /* Restore MSI mapping */ * Restore all other registers. MSI 32 bit address and * MSI 64 bit address are restored as part of this. * sends PME_Turn_Off message to put the link in L2/L3 ready state. * called by px_goto_l23ready. * returns DDI_SUCCESS or DDI_FAILURE /* If already pending, return failure */ "tlu_pme_turn_off_generate = %x\n",
reg);
/* write to PME_Turn_off reg to boradcast */ * Checks for link being in L1idle state. * DDI_SUCCESS - if the link is in L1idle * DDI_FAILURE - if the link is not in L1idle * Tranisition the link to L0, after it is down. /* Clear link down bit in TLU Other Event Clear Status Register. */ /* Clear Drain bit in TLU Status Register */ /* Clear Remain in Detect.Quiet bit in TLU Control Register */ /* Check Leaf Reset status */ /* Blink power LED, this is done from pciehpc already */ /* power fault detection */ /* wait to check power state */ /* Release PCI-E Reset */ * This should be done from pciehpc already /* wait for the link up */ * SPLS = 00b, SPLV = 11001b, i.e. 25W /* Wait for one second */ /* Blink power LED, this is done from pciehpc already */ /* Save the TLU registers */ /* Turn off slot power */ /* write 0 to bit 7 of ILU Error Log Enable Register */ /* Set back TLU registers */ /* Indicator LED blink */ /* Check Leaf Reset status */ "even after waiting %llx ticks",
end_time);
/* Wait for one second */ /* Get the power state */ "unsupported offset 0x%lx\n",
off);
* Depending on the current state, insertion or removal * will go through their respective sequences. "off because of power fault\n");
"unsupported offset 0x%lx\n",
off);
/* For empty or disconnected slot, disable LUP/LDN */ /* cookie is the csr_base */