px_hlib.c revision 055d7c804dc8f1263f0b3166ba459c65996b8697
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <sys/iommutsb.h>
#include <pcie_pwr.h>
#include <px_obj.h>
#include "px_regs.h"
#include "oberon_regs.h"
#include "px_csr.h"
#include "px_lib4u.h"
#include "px_err.h"
/*
*/
/*
* Registers in the PEC Module.
* LPU_RESET should be set to 0ull during resume
*
* This array is in reg,chip form. PX_CHIP_UNIDENTIFIED is for all chips
* or PX_CHIP_FIRE for Fire only, or PX_CHIP_OBERON for Oberon only.
*/
static struct px_pec_regs {
} pec_config_state_regs[] = {
};
#define PEC_KEYS \
((sizeof (pec_config_state_regs))/sizeof (struct px_pec_regs))
/*
* Registers for the MMU module.
* MMU_TTE_CACHE_INVALIDATE needs to be cleared. (-1ull)
*/
static uint64_t mmu_config_state_regs[] = {
};
#define MMU_SIZE (sizeof (mmu_config_state_regs))
/*
* Registers for the IB Module
*/
static uint64_t ib_config_state_regs[] = {
};
#define IB_SIZE (sizeof (ib_config_state_regs))
/*
* Registers for the JBC module.
* JBC_ERROR_STATUS_CLEAR needs to be cleared. (-1ull)
*/
static uint64_t jbc_config_state_regs[] = {
};
#define JBC_SIZE (sizeof (jbc_config_state_regs))
/*
* Registers for the UBC module.
* UBC_ERROR_STATUS_CLEAR needs to be cleared. (-1ull)
*/
static uint64_t ubc_config_state_regs[] = {
};
#define UBC_SIZE (sizeof (ubc_config_state_regs))
static uint64_t msiq_config_other_regs[] = {
};
#define MSIQ_OTHER_SIZE (sizeof (msiq_config_other_regs))
/* OPL tuning variables for link unstable issue */
/*
* Initialize the bus, but do not enable interrupts.
*/
/* ARGSUSED */
void
{
switch (PX_CHIP_TYPE(pxu_p)) {
case PX_CHIP_OBERON:
break;
case PX_CHIP_FIRE:
break;
default:
break;
}
}
/*
* Initialize the JBC module, but do not enable interrupts.
*/
/* ARGSUSED */
static void
{
/* Check if we need to enable inverted parity */
(1 << JBC_FATAL_RESET_ENABLE_CPE_P_INT_EN) |
(1 << JBC_FATAL_RESET_ENABLE_APE_P_INT_EN) |
/*
* Enable merge, jbc and dmc interrupts.
*/
"jbc_init, JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE: 0x%llx\n",
/*
* CSR_V JBC's interrupt regs (log, enable, status, clear)
*/
}
/*
* Initialize the UBC module, but do not enable interrupts.
*/
/* ARGSUSED */
static void
{
/*
* Enable Uranus bus error log bits.
*/
/*
* Clear Uranus bus errors.
*/
/*
* CSR_V UBC's interrupt regs (log, enable, status, clear)
*/
}
/*
* Initialize the module, but do not enable interrupts.
*/
/* ARGSUSED */
void
{
/*
* CSR_V IB's interrupt regs (log, enable, status, clear)
*/
}
/*
* Initialize the module, but do not enable interrupts.
*/
/* ARGSUSED */
static void
{
/*
* CSR_V ILU's interrupt regs (log, enable, status, clear)
*/
}
/*
* Initialize the module, but do not enable interrupts.
*/
/* ARGSUSED */
static void
{
/*
* CSR_V TLU_CONTROL Expect OBP ???
*/
/*
* L0s entry default timer value - 7.0 us
* Completion timeout select default value - 67.1 ms and
* OBP will set this value.
*
* Configuration - Bit 0 should always be 0 for upstream port.
* Bit 1 is clock - how is this related to the clock bit in TLU
* Link Control register? Both are hardware dependent and likely
* set by OBP.
*
* NOTE: Do not set the NPWR_EN bit. The desired value of this bit
* will be set by OBP.
*/
/*
* For Oberon, NPWR_EN is set to 0 to prevent PIO reads from blocking
* behind non-posted PIO writes. This blocking could cause a master or
* slave timeout on the host bus if multiple serialized PIOs were to
* suffer Completion Timeouts because the CTO delays for each PIO ahead
* of the read would accumulate. Since the Olympus processor can have
* only 1 PIO outstanding, there is no possibility of PIO accesses from
* a given CPU to a given device being re-ordered by the PCIe fabric;
* therefore turning off serialization should be safe from a PCIe
* ordering perspective.
*/
/*
* Set Detect.Quiet. This will disable automatic link
* re-training, if the link goes down e.g. power management
* turns off power to the downstream device. This will enable
* Fire to go to Drain state, after link down. The drain state
* forces a reset to the FC state machine, which is required for
* proper link re-training.
*/
/*
* CSR_V TLU_STATUS Expect HW 0x4
*/
/*
* Only bit [7:0] are currently defined. Bits [2:0]
* are the state, which should likely be in state active,
* 100b. Bit three is 'recovery', which is not understood.
* All other bits are reserved.
*/
/*
* CSR_V TLU_PME_TURN_OFF_GENERATE Expect HW 0x0
*/
/*
* CSR_V TLU_INGRESS_CREDITS_INITIAL Expect HW 0x10000200C0
*/
/*
* Ingress credits initial register. Bits [39:32] should be
* 0x10, bits [19:12] should be 0x20, and bits [11:0] should
* be 0xC0. These are the reset values, and should be set by
* HW.
*/
/*
* CSR_V TLU_DIAGNOSTIC Expect HW 0x0
*/
/*
* Diagnostic register - always zero unless we are debugging.
*/
/*
* CSR_V TLU_EGRESS_CREDITS_CONSUMED Expect HW 0x0
*/
/*
* CSR_V TLU_EGRESS_CREDIT_LIMIT Expect HW 0x0
*/
/*
* CSR_V TLU_EGRESS_RETRY_BUFFER Expect HW 0x0
*/
/*
* CSR_V TLU_INGRESS_CREDITS_ALLOCATED Expected HW 0x0
*/
"tlu_init - TLU_INGRESS_CREDITS_ALLOCATED: 0x%llx\n",
/*
* CSR_V TLU_INGRESS_CREDITS_RECEIVED Expected HW 0x0
*/
"tlu_init - TLU_INGRESS_CREDITS_RECEIVED: 0x%llx\n",
/*
* CSR_V TLU's interrupt regs (log, enable, status, clear)
*/
"tlu_init - TLU_OTHER_EVENT_LOG_ENABLE: 0x%llx\n",
"tlu_init - TLU_OTHER_EVENT_INTERRUPT_ENABLE: 0x%llx\n",
"tlu_init - TLU_OTHER_EVENT_INTERRUPT_STATUS: 0x%llx\n",
"tlu_init - TLU_OTHER_EVENT_STATUS_CLEAR: 0x%llx\n",
/*
* CSR_V TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG Expect HW 0x0
*/
"tlu_init - TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG: 0x%llx\n",
/*
* CSR_V TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG Expect HW 0x0
*/
"tlu_init - TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG: 0x%llx\n",
/*
* CSR_V TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG Expect HW 0x0
*/
"tlu_init - TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG: 0x%llx\n",
/*
* CSR_V TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG Expect HW 0x0
*/
"tlu_init - TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG: 0x%llx\n",
/*
* CSR_V TLU_PERFORMANCE_COUNTER_SELECT Expect HW 0x0
*/
"tlu_init - TLU_PERFORMANCE_COUNTER_SELECT: 0x%llx\n",
/*
* CSR_V TLU_PERFORMANCE_COUNTER_ZERO Expect HW 0x0
*/
"tlu_init - TLU_PERFORMANCE_COUNTER_ZERO: 0x%llx\n",
/*
* CSR_V TLU_PERFORMANCE_COUNTER_ONE Expect HW 0x0
*/
/*
* CSR_V TLU_PERFORMANCE_COUNTER_TWO Expect HW 0x0
*/
/*
* CSR_V TLU_DEBUG_SELECT_A Expect HW 0x0
*/
/*
* CSR_V TLU_DEBUG_SELECT_B Expect HW 0x0
*/
/*
* CSR_V TLU_DEVICE_CAPABILITIES Expect HW 0xFC2
*/
/*
* CSR_V TLU_DEVICE_CONTROL Expect HW 0x0
*/
/*
* Bits [14:12] are the Max Read Request Size, which is always 64
* bytes which is 000b. Bits [7:5] are Max Payload Size, which
* start at 128 bytes which is 000b. This may be revisited if
* init_child finds greater values.
*/
val = 0x0ull;
/*
* CSR_V TLU_DEVICE_STATUS Expect HW 0x0
*/
/*
* CSR_V TLU_LINK_CAPABILITIES Expect HW 0x15C81
*/
/*
* CSR_V TLU_LINK_CONTROL Expect OBP 0x40
*/
/*
* The CLOCK bit should be set by OBP if the hardware dictates,
* and if it is set then ASPM should be used since then L0s exit
* latency should be lower than L1 exit latency.
*
* Note that we will not enable power management during bringup
* since it has not been test and is creating some problems in
* simulation.
*/
/*
* CSR_V TLU_LINK_STATUS Expect OBP 0x1011
*/
/*
* Not sure if HW or OBP will be setting this read only
* register. Bit 12 is Clock, and it should always be 1
* signifying that the component uses the same physical
* clock as the platform. Bits [9:4] are for the width,
* with the expected value above signifying a x1 width.
* Bits [3:0] are the speed, with 1b signifying 2.5 Gb/s,
* the only speed as yet supported by the PCI-E spec.
*/
/*
* CSR_V TLU_SLOT_CAPABILITIES Expect OBP ???
*/
/*
* Power Limits for the slots. Will be platform
* dependent, and OBP will need to set after consulting
* with the HW guys.
*
* Bits [16:15] are power limit scale, which most likely
* will be 0b signifying 1x. Bits [14:7] are the Set
* Power Limit Value, which is a number which is multiplied
* by the power limit scale to get the actual power limit.
*/
/*
* CSR_V TLU_UNCORRECTABLE_ERROR_LOG_ENABLE Expect Kernel 0x17F011
*/
"tlu_init - TLU_UNCORRECTABLE_ERROR_LOG_ENABLE: 0x%llx\n",
/*
* CSR_V TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE Expect
* Kernel 0x17F0110017F011
*/
"tlu_init - TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE: 0x%llx\n",
/*
* CSR_V TLU_UNCORRECTABLE_ERROR_INTERRUPT_STATUS Expect HW 0x0
*/
"tlu_init - TLU_UNCORRECTABLE_ERROR_INTERRUPT_STATUS: 0x%llx\n",
/*
* CSR_V TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR Expect HW 0x0
*/
"tlu_init - TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR: 0x%llx\n",
/*
* CSR_V TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG HW 0x0
*/
"tlu_init - TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG: 0x%llx\n",
/*
* CSR_V TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG HW 0x0
*/
"tlu_init - TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG: 0x%llx\n",
/*
* CSR_V TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG HW 0x0
*/
"tlu_init - TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG: 0x%llx\n",
/*
* CSR_V TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG HW 0x0
*/
"tlu_init - TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG: 0x%llx\n",
/*
* CSR_V TLU's CE interrupt regs (log, enable, status, clear)
* Plus header logs
*/
/*
* CSR_V TLU_CORRECTABLE_ERROR_LOG_ENABLE Expect Kernel 0x11C1
*/
"tlu_init - TLU_CORRECTABLE_ERROR_LOG_ENABLE: 0x%llx\n",
/*
* CSR_V TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE Kernel 0x11C1000011C1
*/
"tlu_init - TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE: 0x%llx\n",
/*
* CSR_V TLU_CORRECTABLE_ERROR_INTERRUPT_STATUS Expect HW 0x0
*/
"tlu_init - TLU_CORRECTABLE_ERROR_INTERRUPT_STATUS: 0x%llx\n",
/*
* CSR_V TLU_CORRECTABLE_ERROR_STATUS_CLEAR Expect HW 0x0
*/
"tlu_init - TLU_CORRECTABLE_ERROR_STATUS_CLEAR: 0x%llx\n",
}
/* ARGSUSED */
static void
{
/* Variables used to set the ACKNAK Latency Timer and Replay Timer */
int link_width, max_payload;
/*
* ACKNAK Latency Threshold Table.
* See Fire PRM 2.0 section 1.2.12.2, table 1-17.
*/
{0xED, 0x49, 0x43, 0x30},
{0x1A0, 0x76, 0x6B, 0x48},
{0x22F, 0x9A, 0x56, 0x56},
{0x42F, 0x11A, 0x96, 0x96},
{0x82F, 0x21A, 0x116, 0x116},
{0x102F, 0x41A, 0x216, 0x216}
};
/*
* TxLink Replay Timer Latency Table
* See Fire PRM 2.0 sections 1.2.12.3, table 1-18.
*/
{0x379, 0x112, 0xFC, 0xB4},
{0x618, 0x1BA, 0x192, 0x10E},
{0x831, 0x242, 0x143, 0x143},
{0xFB1, 0x422, 0x233, 0x233},
{0x1EB0, 0x7E1, 0x412, 0x412},
{0x3CB0, 0xF61, 0x7D2, 0x7D2}
};
/*
* Get the Link Width. See table above LINK_WIDTH_ARR_SIZE #define
* Only Link Widths of x1, x4, and x8 are supported.
* If any width is reported other than x8, set default to x8.
*/
/*
* Convert link_width to match timer array configuration.
*/
switch (link_width) {
case 1:
link_width = 0;
break;
case 4:
link_width = 1;
break;
case 8:
link_width = 2;
break;
case 16:
link_width = 3;
break;
default:
link_width = 0;
}
/*
* Get the Max Payload Size.
* See table above LINK_MAX_PKT_ARR_SIZE #define
*/
(0x80 << max_payload));
/* Make sure the packet size is not greater than 4096 */
/*
* CSR_V LPU_ID Expect HW 0x0
*/
/*
* This register has link id, phy id and gigablaze id.
* Should be set by HW.
*/
/*
* CSR_V LPU_RESET Expect Kernel 0x0
*/
/*
* No reason to have any reset bits high until an error is
* detected on the link.
*/
/*
* CSR_V LPU_DEBUG_STATUS Expect HW 0x0
*/
/*
* Bits [15:8] are Debug B, and bit [7:0] are Debug A.
* They are read-only. What do the 8 bits mean, and
* how do they get set if they are read only?
*/
/*
* CSR_V LPU_DEBUG_CONFIG Expect Kernel 0x0
*/
/*
* CSR_V LPU_LTSSM_CONTROL Expect HW 0x0
*/
/*
* CSR_V LPU_LINK_STATUS Expect HW 0x101
*/
/*
* This register has bits [9:4] for link width, and the
* default 0x10, means a width of x16. The problem is
* this width is not supported according to the TLU
* link status register.
*/
/*
* CSR_V LPU_INTERRUPT_STATUS Expect HW 0x0
*/
/*
* CSR_V LPU_INTERRUPT_MASK Expect HW 0x0
*/
/*
* CSR_V LPU_LINK_PERFORMANCE_COUNTER_SELECT Expect HW 0x0
*/
"lpu_init - LPU_LINK_PERFORMANCE_COUNTER_SELECT: 0x%llx\n",
/*
* CSR_V LPU_LINK_PERFORMANCE_COUNTER_CONTROL Expect HW 0x0
*/
"lpu_init - LPU_LINK_PERFORMANCE_COUNTER_CONTROL: 0x%llx\n",
/*
* CSR_V LPU_LINK_PERFORMANCE_COUNTER1 Expect HW 0x0
*/
"lpu_init - LPU_LINK_PERFORMANCE_COUNTER1: 0x%llx\n",
/*
* CSR_V LPU_LINK_PERFORMANCE_COUNTER1_TEST Expect HW 0x0
*/
"lpu_init - LPU_LINK_PERFORMANCE_COUNTER1_TEST: 0x%llx\n",
/*
* CSR_V LPU_LINK_PERFORMANCE_COUNTER2 Expect HW 0x0
*/
"lpu_init - LPU_LINK_PERFORMANCE_COUNTER2: 0x%llx\n",
/*
* CSR_V LPU_LINK_PERFORMANCE_COUNTER2_TEST Expect HW 0x0
*/
"lpu_init - LPU_LINK_PERFORMANCE_COUNTER2_TEST: 0x%llx\n",
/*
* CSR_V LPU_LINK_LAYER_CONFIG Expect HW 0x100
*/
/*
* This is another place where Max Payload can be set,
* this time for the link layer. It will be set to
* 128B, which is the default, but this will need to
* be revisited.
*/
/*
* CSR_V LPU_LINK_LAYER_STATUS Expect OBP 0x5
*/
/*
* Another R/W status register. Bit 3, DL up Status, will
* be set high. The link state machine status bits [2:0]
* are set to 0x1, but the status bits are not defined in the
* PRM. What does 0x1 mean, what others values are possible
* and what are thier meanings?
*
* This register has been giving us problems in simulation.
* It has been mentioned that software should not program
* any registers with WE bits except during debug. So
* this register will no longer be programmed.
*/
/*
* CSR_V LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST Expect HW 0x0
*/
"lpu_init - LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST: 0x%llx\n",
/*
* CSR_V LPU Link Layer interrupt regs (mask, status)
*/
"lpu_init - LPU_LINK_LAYER_INTERRUPT_MASK: 0x%llx\n",
"lpu_init - LPU_LINK_LAYER_INTERRUPT_AND_STATUS: 0x%llx\n",
/*
* CSR_V LPU_FLOW_CONTROL_UPDATE_CONTROL Expect OBP 0x7
*/
/*
* The PRM says that only the first two bits will be set
* high by default, which will enable flow control for
* posted and non-posted updates, but NOT completetion
* updates.
*/
(1ull << LPU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_P_EN);
"lpu_init - LPU_FLOW_CONTROL_UPDATE_CONTROL: 0x%llx\n",
/*
* CSR_V LPU_LINK_LAYER_FLOW_CONTROL_UPDATE_TIMEOUT_VALUE
* Expect OBP 0x1D4C
*/
/*
* This should be set by OBP. We'll check to make sure.
*/
"LPU_LINK_LAYER_FLOW_CONTROL_UPDATE_TIMEOUT_VALUE: 0x%llx\n",
/*
* CSR_V LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER0 Expect OBP ???
*/
/*
* This register has Flow Control Update Timer values for
* non-posted and posted requests, bits [30:16] and bits
* [14:0], respectively. These are read-only to SW so
* either HW or OBP needs to set them.
*/
"LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER0: 0x%llx\n",
/*
* CSR_V LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER1 Expect OBP ???
*/
/*
* Same as timer0 register above, except for bits [14:0]
* have the timer values for completetions. Read-only to
* SW; OBP or HW need to set it.
*/
"LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER1: 0x%llx\n",
/*
* CSR_V LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD
*/
"LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD: 0x%llx\n",
/*
* CSR_V LPU_TXLINK_ACKNAK_LATENCY_TIMER Expect HW 0x0
*/
"lpu_init - LPU_TXLINK_ACKNAK_LATENCY_TIMER: 0x%llx\n",
/*
* CSR_V LPU_TXLINK_REPLAY_TIMER_THRESHOLD
*/
"lpu_init - LPU_TXLINK_REPLAY_TIMER_THRESHOLD: 0x%llx\n",
/*
* CSR_V LPU_TXLINK_REPLAY_TIMER Expect HW 0x0
*/
/*
* CSR_V LPU_TXLINK_REPLAY_NUMBER_STATUS Expect OBP 0x3
*/
"lpu_init - LPU_TXLINK_REPLAY_NUMBER_STATUS: 0x%llx\n",
/*
* CSR_V LPU_REPLAY_BUFFER_MAX_ADDRESS Expect OBP 0xB3F
*/
"lpu_init - LPU_REPLAY_BUFFER_MAX_ADDRESS: 0x%llx\n",
/*
* CSR_V LPU_TXLINK_RETRY_FIFO_POINTER Expect OBP 0xFFFF0000
*/
"lpu_init - LPU_TXLINK_RETRY_FIFO_POINTER: 0x%llx\n",
/*
* CSR_V LPU_TXLINK_RETRY_FIFO_R_W_POINTER Expect OBP 0x0
*/
"lpu_init - LPU_TXLINK_RETRY_FIFO_R_W_POINTER: 0x%llx\n",
/*
* CSR_V LPU_TXLINK_RETRY_FIFO_CREDIT Expect HW 0x1580
*/
"lpu_init - LPU_TXLINK_RETRY_FIFO_CREDIT: 0x%llx\n",
/*
* CSR_V LPU_TXLINK_SEQUENCE_COUNTER Expect OBP 0xFFF0000
*/
/*
* CSR_V LPU_TXLINK_ACK_SENT_SEQUENCE_NUMBER Expect HW 0xFFF
*/
"lpu_init - LPU_TXLINK_ACK_SENT_SEQUENCE_NUMBER: 0x%llx\n",
/*
* CSR_V LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR Expect OBP 0x157
*/
/*
* Test only register. Will not be programmed.
*/
"lpu_init - LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR: 0x%llx\n",
/*
* CSR_V LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS Expect HW 0xFFF0000
*/
/*
* Test only register. Will not be programmed.
*/
"lpu_init - LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS: 0x%llx\n",
/*
* CSR_V LPU_TXLINK_SEQUENCE_COUNT_R_W_POINTERS Expect HW 0x0
*/
"lpu_init - LPU_TXLINK_SEQUENCE_COUNT_R_W_POINTERS: 0x%llx\n",
/*
* CSR_V LPU_TXLINK_TEST_CONTROL Expect HW 0x0
*/
/*
* CSR_V LPU_TXLINK_MEMORY_ADDRESS_CONTROL Expect HW 0x0
*/
/*
* Test only register. Will not be programmed.
*/
"lpu_init - LPU_TXLINK_MEMORY_ADDRESS_CONTROL: 0x%llx\n",
/*
* CSR_V LPU_TXLINK_MEMORY_DATA_LOAD0 Expect HW 0x0
*/
"lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD0: 0x%llx\n",
/*
* CSR_V LPU_TXLINK_MEMORY_DATA_LOAD1 Expect HW 0x0
*/
"lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD1: 0x%llx\n",
/*
* CSR_V LPU_TXLINK_MEMORY_DATA_LOAD2 Expect HW 0x0
*/
"lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD2: 0x%llx\n",
/*
* CSR_V LPU_TXLINK_MEMORY_DATA_LOAD3 Expect HW 0x0
*/
"lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD3: 0x%llx\n",
/*
* CSR_V LPU_TXLINK_MEMORY_DATA_LOAD4 Expect HW 0x0
*/
"lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD4: 0x%llx\n",
/*
* CSR_V LPU_TXLINK_RETRY_DATA_COUNT Expect HW 0x0
*/
/*
* Test only register. Will not be programmed.
*/
/*
* CSR_V LPU_TXLINK_SEQUENCE_BUFFER_COUNT Expect HW 0x0
*/
/*
* Test only register. Will not be programmed.
*/
"lpu_init - LPU_TXLINK_SEQUENCE_BUFFER_COUNT: 0x%llx\n",
/*
* CSR_V LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA Expect HW 0x0
*/
/*
* Test only register.
*/
"lpu_init - LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA: 0x%llx\n",
/*
* CSR_V LPU_RXLINK_NEXT_RECEIVE_SEQUENCE_1_COUNTER Expect HW 0x0
*/
"LPU_RXLINK_NEXT_RECEIVE_SEQUENCE_1_COUNTER: 0x%llx\n",
/*
* CSR_V LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED Expect HW 0x0
*/
/*
* test only register.
*/
"lpu_init - LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED: 0x%llx\n",
/*
* CSR_V LPU_RXLINK_TEST_CONTROL Expect HW 0x0
*/
/*
* test only register.
*/
/*
* CSR_V LPU_PHYSICAL_LAYER_CONFIGURATION Expect HW 0x10
*/
"lpu_init - LPU_PHYSICAL_LAYER_CONFIGURATION: 0x%llx\n",
/*
* CSR_V LPU_PHY_LAYER_STATUS Expect HW 0x0
*/
/*
* CSR_V LPU_PHY_INTERRUPT_AND_STATUS_TEST Expect HW 0x0
*/
"lpu_init - LPU_PHY_INTERRUPT_AND_STATUS_TEST: 0x%llx\n",
/*
* CSR_V LPU PHY LAYER interrupt regs (mask, status)
*/
"lpu_init - LPU_PHY_LAYER_INTERRUPT_AND_STATUS: 0x%llx\n",
/*
* CSR_V LPU_RECEIVE_PHY_CONFIG Expect HW 0x0
*/
/*
* This also needs some explanation. What is the best value
* for the water mark? Test mode enables which test mode?
* Programming model needed for the Receiver Reset Lane N
* bits.
*/
/*
* CSR_V LPU_RECEIVE_PHY_STATUS1 Expect HW 0x0
*/
/*
* CSR_V LPU_RECEIVE_PHY_STATUS2 Expect HW 0x0
*/
/*
* CSR_V LPU_RECEIVE_PHY_STATUS3 Expect HW 0x0
*/
/*
* CSR_V LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_TEST Expect HW 0x0
*/
"lpu_init - LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_TEST: 0x%llx\n",
/*
* CSR_V LPU RX LAYER interrupt regs (mask, status)
*/
"lpu_init - LPU_RECEIVE_PHY_INTERRUPT_MASK: 0x%llx\n",
"lpu_init - LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS: 0x%llx\n",
/*
* CSR_V LPU_TRANSMIT_PHY_CONFIG Expect HW 0x0
*/
/*
* CSR_V LPU_TRANSMIT_PHY_STATUS Expect HW 0x0
*/
/*
* CSR_V LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_TEST Expect HW 0x0
*/
"lpu_init - LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_TEST: 0x%llx\n",
/*
* CSR_V LPU TX LAYER interrupt regs (mask, status)
*/
"lpu_init - LPU_TRANSMIT_PHY_INTERRUPT_MASK: 0x%llx\n",
"lpu_init - LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS: 0x%llx\n",
/*
* CSR_V LPU_TRANSMIT_PHY_STATUS_2 Expect HW 0x0
*/
/*
* CSR_V LPU_LTSSM_CONFIG1 Expect OBP 0x205
*/
/*
* The new PRM has values for LTSSM 8 ns timeout value and
* LTSSM 20 ns timeout value. But what do these values mean?
* Most of the other bits are questions as well.
*
* As such we will use the reset value.
*/
/*
* CSR_V LPU_LTSSM_CONFIG2 Expect OBP 0x2DC6C0
*/
/*
* Again, what does '12 ms timeout value mean'?
*/
/*
* CSR_V LPU_LTSSM_CONFIG3 Expect OBP 0x7A120
*/
/*
* CSR_V LPU_LTSSM_CONFIG4 Expect OBP 0x21300
*/
/*
* CSR_V LPU_LTSSM_CONFIG5 Expect OBP 0x0
*/
/*
* CSR_V LPU_LTSSM_STATUS1 Expect OBP 0x0
*/
/*
* LTSSM Status registers are test only.
*/
/*
* CSR_V LPU_LTSSM_STATUS2 Expect OBP 0x0
*/
/*
* CSR_V LPU_LTSSM_INTERRUPT_AND_STATUS_TEST Expect HW 0x0
*/
"lpu_init - LPU_LTSSM_INTERRUPT_AND_STATUS_TEST: 0x%llx\n",
/*
* CSR_V LPU LTSSM LAYER interrupt regs (mask, status)
*/
"lpu_init - LPU_LTSSM_INTERRUPT_AND_STATUS: 0x%llx\n",
/*
* CSR_V LPU_LTSSM_STATUS_WRITE_ENABLE Expect OBP 0x0
*/
"lpu_init - LPU_LTSSM_STATUS_WRITE_ENABLE: 0x%llx\n",
/*
* CSR_V LPU_GIGABLAZE_GLUE_CONFIG1 Expect OBP 0x88407
*/
/*
* CSR_V LPU_GIGABLAZE_GLUE_CONFIG2 Expect OBP 0x35
*/
/*
* CSR_V LPU_GIGABLAZE_GLUE_CONFIG3 Expect OBP 0x4400FA
*/
/*
* CSR_V LPU_GIGABLAZE_GLUE_CONFIG4 Expect OBP 0x1E848
*/
/*
* CSR_V LPU_GIGABLAZE_GLUE_STATUS Expect OBP 0x0
*/
/*
* CSR_V LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_TEST Expect OBP 0x0
*/
"LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_TEST: 0x%llx\n",
/*
* CSR_V LPU GIGABLASE LAYER interrupt regs (mask, status)
*/
"lpu_init - LPU_GIGABLAZE_GLUE_INTERRUPT_MASK: 0x%llx\n",
"lpu_init - LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS: 0x%llx\n",
/*
* CSR_V LPU_GIGABLAZE_GLUE_POWER_DOWN1 Expect HW 0x0
*/
"lpu_init - LPU_GIGABLAZE_GLUE_POWER_DOWN1: 0x%llx\n",
/*
* CSR_V LPU_GIGABLAZE_GLUE_POWER_DOWN2 Expect HW 0x0
*/
"lpu_init - LPU_GIGABLAZE_GLUE_POWER_DOWN2: 0x%llx\n",
/*
* CSR_V LPU_GIGABLAZE_GLUE_CONFIG5 Expect OBP 0x0
*/
}
/* ARGSUSED */
static void
{
(1ull << DLU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_P_EN);
}
/* ARGSUSED */
static void
{
/*
* CSR_V DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE Expect OBP 0x8000000000000003
*/
val = -1ull;
"dmc_init - DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE: 0x%llx\n",
/*
* CSR_V DMC_CORE_AND_BLOCK_ERROR_STATUS Expect HW 0x0
*/
"dmc_init - DMC_CORE_AND_BLOCK_ERROR_STATUS: 0x%llx\n",
/*
* CSR_V DMC_DEBUG_SELECT_FOR_PORT_A Expect HW 0x0
*/
val = 0x0ull;
/*
* CSR_V DMC_DEBUG_SELECT_FOR_PORT_B Expect HW 0x0
*/
val = 0x0ull;
}
void
{
switch (PX_CHIP_TYPE(pxu_p)) {
case PX_CHIP_OBERON:
break;
case PX_CHIP_FIRE:
break;
default:
break;
}
/*
* CSR_V PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE Expect Kernel 0x800000000000000F
*/
val = -1ull;
"hvio_pec_init - PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE: 0x%llx\n",
/*
* CSR_V PEC_CORE_AND_BLOCK_INTERRUPT_STATUS Expect HW 0x0
*/
"hvio_pec_init - PEC_CORE_AND_BLOCK_INTERRUPT_STATUS: 0x%llx\n",
}
/*
* Convert a TTE to physical address
*/
static r_addr_t
{
switch (PX_CHIP_TYPE(pxu_p)) {
case PX_CHIP_OBERON:
break;
case PX_CHIP_FIRE:
break;
default:
pa_mask = 0;
break;
}
}
/*
* Return MMU bypass noncache bit for chip
*/
static r_addr_t
{
switch (PX_CHIP_TYPE(pxu_p)) {
case PX_CHIP_OBERON:
break;
case PX_CHIP_FIRE:
break;
default:
"mmu_bypass_nocache - unknown chip type: 0x%x\n",
bypass_noncache_bit = 0;
break;
}
return (bypass_noncache_bit);
}
/*
* Calculate number of TSB entries for the chip.
*/
/* ARGSUSED */
static uint_t
{
return (obp_tsb_entries);
}
/*
* Initialize the module, but do not enable interrupts.
*/
void
{
/*
* Preserve OBP's TSB
*/
for (i = 0; i < obp_tsb_entries; i++) {
if (!MMU_TTE_VALID(tte))
continue;
base_tte_addr[i] = tte;
}
/*
* Invalidate the TLB through the diagnostic register.
*/
/*
* Configure the Fire MMU TSB Control Register. Determine
* the encoding for either 8KB pages (0) or 64KB pages (1).
*
* Write the most significant 30 bits of the TSB physical address
* and the encoded TSB table size.
*/
/*
* Enable the MMU, set the "TSB Cache Snoop Enable",
* the "Cache Mode", the "Bypass Enable" and
* the "Translation Enable" bits.
*/
| (1ull << MMU_CONTROL_AND_STATUS_BE)
| (1ull << MMU_CONTROL_AND_STATUS_TE));
/*
* Read the register here to ensure that the previous writes to
* the Fire MMU registers have been flushed. (Technically, this
* is not entirely necessary here as we will likely do later reads
* during Fire initialization, but it is a small price to pay for
* more modular code.)
*/
/*
* CSR_V TLU's UE interrupt regs (log, enable, status, clear)
* Plus header logs
*/
}
/*
* Generic IOMMU Servies
*/
/* ARGSUSED */
{
int i;
if (io_attr & PCI_MAP_ATTR_WRITE)
(io_attr & PCI_MAP_ATTR_RO))
attr |= MMU_TTE_RO;
if (attr & MMU_TTE_RO) {
}
if (flags & MMU_MAP_PFN) {
/*
* Oberon will need to flush the corresponding TTEs in
* Cache. We only need to flush every cache line.
* Extra PIO's are expensive.
*/
(tsb_index*MMU_TTE_SIZE)));
}
}
}
} else {
/*
* Oberon will need to flush the corresponding TTEs in
* Cache. We only need to flush every cache line.
* Extra PIO's are expensive.
*/
(tsb_index*MMU_TTE_SIZE)));
}
}
}
}
return (H_EOK);
}
/* ARGSUSED */
{
int i;
/*
* Oberon will need to flush the corresponding TTEs in
* Cache. We only need to flush every cache line.
* Extra PIO's are expensive.
*/
(tsb_index*MMU_TTE_SIZE)));
}
}
}
return (H_EOK);
}
/* ARGSUSED */
{
} else {
*r_addr_p = 0;
*attr_p = 0;
}
return (ret);
}
/* ARGSUSED */
{
switch (PX_CHIP_TYPE(pxu_p)) {
case PX_CHIP_OBERON:
break;
case PX_CHIP_FIRE:
break;
default:
"hvio_get_bypass_base - unknown chip type: 0x%x\n",
base = 0;
break;
}
return (base);
}
/* ARGSUSED */
{
switch (PX_CHIP_TYPE(pxu_p)) {
case PX_CHIP_OBERON:
break;
case PX_CHIP_FIRE:
break;
default:
"hvio_get_bypass_end - unknown chip type: 0x%x\n",
end = 0;
break;
}
return (end);
}
/* ARGSUSED */
{
return (H_EOK);
}
/*
* Generic IO Interrupt Servies
*/
/*
* Converts a device specific interrupt number given by the
* arguments devhandle and devino into a system specific ino.
*/
/* ARGSUSED */
{
if (devino > INTERRUPT_MAPPING_ENTRIES) {
return (H_ENOINTR);
}
return (H_EOK);
}
/*
* Returns state in intr_valid_state if the interrupt defined by sysino
* is valid (enabled) or not-valid (disabled).
*/
{
} else {
}
return (H_EOK);
}
/*
* Sets the 'valid' state of the interrupt defined by
* the argument sysino to the state defined by the
* argument intr_valid_state.
*/
{
switch (intr_valid_state) {
case INTR_VALID:
break;
case INTR_NOTVALID:
break;
default:
return (EINVAL);
}
return (H_EOK);
}
/*
* Returns the current state of the interrupt given by the sysino
* argument.
*/
{
switch (state) {
case INTERRUPT_IDLE_STATE:
break;
case INTERRUPT_RECEIVED_STATE:
break;
case INTERRUPT_PENDING_STATE:
break;
default:
return (EINVAL);
}
return (H_EOK);
}
/*
* Sets the current state of the interrupt given by the sysino
* argument to the value given in the argument intr_state.
*
* Note: Setting the state to INTR_IDLE clears any pending
* interrupt for sysino.
*/
{
switch (intr_state) {
case INTR_IDLE_STATE:
break;
case INTR_DELIVERED_STATE:
break;
default:
return (EINVAL);
}
return (H_EOK);
}
/*
* Returns the cpuid that is the current target of the
* interrupt given by the sysino argument.
*
* The cpuid value returned is undefined if the target
* has not been set via intr_settarget.
*/
{
switch (PX_CHIP_TYPE(pxu_p)) {
case PX_CHIP_OBERON:
break;
case PX_CHIP_FIRE:
break;
default:
return (EINVAL);
}
return (H_EOK);
}
/*
* Set the target cpu for the interrupt defined by the argument
* sysino to the target cpu value defined by the argument cpuid.
*/
{
/*
* For now, we assign interrupt controller in a round
* robin fashion. Later, we may need to come up with
* a more efficient assignment algorithm.
*/
switch (PX_CHIP_TYPE(pxu_p)) {
case PX_CHIP_OBERON:
((intr_controller &
break;
case PX_CHIP_FIRE:
((intr_controller &
break;
default:
return (EINVAL);
}
/* For EQ interrupts, set DATA MONDO bit */
if ((ino >= PX_DEFAULT_MSIQ_1ST_DEVINO) &&
return (H_EOK);
}
/*
* MSIQ Functions:
*/
{
"hvio_msiq_init: EVENT_QUEUE_BASE_ADDRESS 0x%llx\n",
"INTERRUPT_MONDO_DATA_0: 0x%llx\n",
return (H_EOK);
}
{
switch (eq_state) {
case EQ_IDLE_STATE:
break;
case EQ_ACTIVE_STATE:
case EQ_ERROR_STATE:
break;
default:
break;
}
return (ret);
}
{
switch (msiq_valid_state) {
case PCI_MSIQ_INVALID:
break;
case PCI_MSIQ_VALID:
break;
default:
break;
}
return (ret);
}
{
switch (eq_state) {
case EQ_IDLE_STATE:
case EQ_ACTIVE_STATE:
break;
case EQ_ERROR_STATE:
break;
default:
}
return (ret);
}
{
switch (eq_state) {
case EQ_IDLE_STATE:
if (msiq_state == PCI_MSIQ_STATE_ERROR)
break;
case EQ_ACTIVE_STATE:
if (msiq_state == PCI_MSIQ_STATE_ERROR)
else
break;
case EQ_ERROR_STATE:
if (msiq_state == PCI_MSIQ_STATE_IDLE)
else
break;
default:
}
return (ret);
}
{
return (H_EOK);
}
{
return (H_EOK);
}
{
return (H_EOK);
}
/*
* MSI Functions:
*/
{
/* PCI MEM 32 resources to perform 32 bit MSI transactions */
/* Reserve PCI MEM 64 resources to perform 64 bit MSI transactions */
return (H_EOK);
}
{
return (H_EOK);
}
{
return (H_EOK);
}
{
return (H_EOK);
}
{
switch (msi_valid_state) {
case PCI_MSI_VALID:
break;
case PCI_MSI_INVALID:
break;
default:
}
return (ret);
}
{
return (H_EOK);
}
{
switch (msi_state) {
case PCI_MSI_STATE_IDLE:
break;
case PCI_MSI_STATE_DELIVERED:
default:
break;
}
return (ret);
}
/*
* MSG Functions:
*/
{
switch (msg_type) {
case PCIE_PME_MSG:
break;
case PCIE_PME_ACK_MSG:
EQNUM);
break;
case PCIE_CORR_MSG:
break;
case PCIE_NONFATAL_MSG:
EQNUM);
break;
case PCIE_FATAL_MSG:
break;
default:
break;
}
return (ret);
}
{
switch (msg_type) {
case PCIE_PME_MSG:
break;
case PCIE_PME_ACK_MSG:
break;
case PCIE_CORR_MSG:
break;
case PCIE_NONFATAL_MSG:
break;
case PCIE_FATAL_MSG:
break;
default:
break;
}
return (ret);
}
{
switch (msg_type) {
case PCIE_PME_MSG:
break;
case PCIE_PME_ACK_MSG:
PME_TO_ACK_MAPPING, V);
break;
case PCIE_CORR_MSG:
break;
case PCIE_NONFATAL_MSG:
ERR_NONFATAL_MAPPING, V);
break;
case PCIE_FATAL_MSG:
V);
break;
default:
break;
}
return (ret);
}
{
switch (msg_valid_state) {
case PCIE_MSG_VALID:
switch (msg_type) {
case PCIE_PME_MSG:
break;
case PCIE_PME_ACK_MSG:
break;
case PCIE_CORR_MSG:
break;
case PCIE_NONFATAL_MSG:
break;
case PCIE_FATAL_MSG:
break;
default:
break;
}
break;
case PCIE_MSG_INVALID:
switch (msg_type) {
case PCIE_PME_MSG:
break;
case PCIE_PME_ACK_MSG:
break;
case PCIE_CORR_MSG:
break;
case PCIE_NONFATAL_MSG:
break;
case PCIE_FATAL_MSG:
break;
default:
break;
}
break;
default:
}
return (ret);
}
/*
* (pec, mmu, ib)
* cb
* Registers saved have all been touched in the XXX_init functions.
*/
{
int total_size;
int i;
return (H_EIO);
if (config_state == NULL) {
return (H_EIO);
}
/*
* uint64_t *pec_config_state;
* uint64_t *mmu_config_state;
* uint64_t *ib_intr_map;
* uint64_t *ib_config_state;
* uint64_t *xcb_config_state;
*/
/* Save the PEC configuration states */
for (i = 0; i < PEC_KEYS; i++) {
pxu_p->pec_config_state[i] =
pec_config_state_regs[i].reg);
}
}
/* Save the MMU configuration states */
for (i = 0; i < MMU_KEYS; i++) {
pxu_p->mmu_config_state[i] =
}
/* Save the interrupt mapping registers */
for (i = 0; i < INTERRUPT_MAPPING_ENTRIES; i++) {
pxu_p->ib_intr_map[i] =
}
/* Save the IB configuration states */
for (i = 0; i < IB_KEYS; i++) {
pxu_p->ib_config_state[i] =
}
return (H_EOK);
}
void
{
int total_size;
int i;
/* Make sure that suspend actually did occur */
if (!pxu_p->pec_config_state) {
return;
}
/* Restore IB configuration states */
for (i = 0; i < IB_KEYS; i++) {
pxu_p->ib_config_state[i]);
}
/*
* Restore the interrupt mapping registers
* And make sure the intrs are idle.
*/
for (i = 0; i < INTERRUPT_MAPPING_ENTRIES; i++) {
pxu_p->ib_intr_map[i]);
}
/* Restore MMU configuration states */
/* Clear the cache. */
for (i = 0; i < MMU_KEYS; i++) {
pxu_p->mmu_config_state[i]);
}
/* Restore PEC configuration states */
/* Make sure all reset bits are low until error is detected */
for (i = 0; i < PEC_KEYS; i++) {
pxu_p->pec_config_state[i]);
}
}
/* Enable PCI-E interrupt */
}
{
switch (PX_CHIP_TYPE(pxu_p)) {
case PX_CHIP_OBERON:
break;
case PX_CHIP_FIRE:
break;
default:
break;
}
if (config_state == NULL) {
return (H_EIO);
}
/* Save the configuration states */
for (i = 0; i < cb_keys; i++) {
pxu_p->xcb_config_state[i] =
}
return (H_EOK);
}
void
{
switch (PX_CHIP_TYPE(pxu_p)) {
case PX_CHIP_OBERON:
/*
* No reason to have any reset bits high until an error is
* detected on the link.
*/
break;
case PX_CHIP_FIRE:
/*
* No reason to have any reset bits high until an error is
* detected on the link.
*/
break;
default:
break;
}
/* Restore the configuration states */
for (i = 0; i < cb_keys; i++) {
pxu_p->xcb_config_state[i]);
}
/* Enable XBC interrupt */
}
static uint64_t
{
int i;
NULL)
return (H_EIO);
/* Save each EQ state */
for (i = 0; i < EVENT_QUEUE_STATE_ENTRIES; i++, cur_p++)
/* Save MSI mapping registers */
for (i = 0; i < MSI_MAPPING_ENTRIES; i++, cur_p++)
/* Save all other MSIQ registers */
for (i = 0; i < MSIQ_OTHER_KEYS; i++, cur_p++)
return (H_EOK);
}
static void
{
int i;
/*
* Initialize EQ base address register and
* Interrupt Mondo Data 0 register.
*/
/* Restore EQ states */
for (i = 0; i < EVENT_QUEUE_STATE_ENTRIES; i++, cur_p++) {
i, ENTRIES_EN);
}
/* Restore MSI mapping */
for (i = 0; i < MSI_MAPPING_ENTRIES; i++, cur_p++)
/*
* Restore all other registers. MSI 32 bit address and
* MSI 64 bit address are restored as part of this.
*/
for (i = 0; i < MSIQ_OTHER_KEYS; i++, cur_p++)
}
/*
* called by px_goto_l23ready.
* returns DDI_SUCCESS or DDI_FAILURE
*/
int
{
/* If already pending, return failure */
"tlu_pme_turn_off_generate = %x\n", reg);
return (DDI_FAILURE);
}
/* write to PME_Turn_off reg to boradcast */
return (DDI_SUCCESS);
}
/*
* Checks for link being in L1idle state.
* Returns
* DDI_SUCCESS - if the link is in L1idle
* DDI_FAILURE - if the link is not in L1idle
*/
int
{
int ntries = px_max_l1_tries;
while (ntries > 0) {
break;
delay(1);
}
}
/*
* Tranisition the link to L0, after it is down.
*/
int
{
return (DDI_FAILURE);
}
/* Clear link down bit in TLU Other Event Clear Status Register. */
/* Clear Drain bit in TLU Status Register */
/* Clear Remain in Detect.Quiet bit in TLU Control Register */
return (DDI_SUCCESS);
}
void
{
}
static uint_t
{
int loop, i;
/* Check Leaf Reset status */
goto fail;
}
/* Check Slot status */
reg);
goto fail;
}
/* Blink power LED, this is done from pciehpc already */
/* Turn on slot power */
/* power fault detection */
/* wait to check power state */
goto fail1;
}
/* power is good */
/* Turn on slot clock */
loop++) {
if (link_retry == B_TRUE) {
"%d\n", loop);
}
/* Release PCI-E Reset */
/*
* Open events' mask
* This should be done from pciehpc already
*/
/* Enable PCIE port */
/* wait for the link up */
if ((((reg >> DLU_LINK_LAYER_STATUS_INIT_FC_SM_STS) &
==
} else
link_retry = B_TRUE;
}
}
"PCI-E port\n");
goto fail2;
}
/* link is up */
/*
* Initialize Leaf
* SPLS = 00b, SPLV = 11001b, i.e. 25W
*/
reg &= ~(TLU_SLOT_CAPABILITIES_SPLS_MASK <<
reg &= ~(TLU_SLOT_CAPABILITIES_SPLV_MASK <<
/* Turn on Power LED */
/* Notify to SCF */
else
return (DDI_SUCCESS);
/* Link up is failed */
fail:
return ((uint_t)DDI_FAILURE);
}
static uint_t
{
/* Blink power LED, this is done from pciehpc already */
/* Clear Slot Event */
/* DRN_TR_DIS on */
(1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_P) |
(1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_S) |
(1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_S));
/* Save the TLU registers */
/* All clear */
/* Disable port */
/* PCIE reset */
/* PCIE clock stop */
/* Turn off slot power */
/* write 0 to bit 7 of ILU Error Log Enable Register */
/* Set back TLU registers */
/* Power LED off */
/* Indicator LED blink */
/* Notify to SCF */
else
/* Indicator LED off */
return (DDI_SUCCESS);
}
static uint_t
{
switch (off) {
case PCIE_SLOTCAP:
break;
case PCIE_SLOTCTL:
/* Get the power state */
(1ull << HOTPLUG_CONTROL_PWREN)) ?
break;
case PCIE_SLOTSTS:
break;
case PCIE_LINKCAP:
break;
case PCIE_LINKSTS:
break;
default:
"unsupported offset 0x%lx\n", off);
break;
}
}
static uint_t
{
switch (off) {
case PCIE_SLOTCTL:
/*
* Depending on the current state, insertion or removal
* will go through their respective sequences.
*/
if (!pwr_off && !pwr_state_on)
else if (pwr_off && pwr_state_on) {
(1ull << TLU_SLOT_STATUS_PWFD);
if (pwr_fault) {
"off because of power fault\n");
}
else
} else
break;
case PCIE_SLOTSTS:
break;
default:
"unsupported offset 0x%lx\n", off);
break;
}
return (ret);
}
int
{
TLU_SLOT_CAPABILITIES, HP)) {
return (DDI_FAILURE);
}
TLU_SLOT_STATUS, PSD) ||
HOTPLUG_CONTROL, PWREN)) {
(1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_P) |
(1ull << TLU_OTHER_EVENT_STATUS_SET_LDN_S) |
(1ull << TLU_OTHER_EVENT_STATUS_SET_LUP_S));
}
/* cookie is the csr_base */
return (DDI_SUCCESS);
}
return (DDI_ENOTSUP);
}
int
{
return (DDI_SUCCESS);
return (DDI_FAILURE);
}