pci_pci.c revision c85864d8472aaccb47ceb468ebd9b3a85b66d161
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Sun4u PCI to PCI bus bridge nexus driver
*/
#include <sys/autoconf.h>
#include <sys/ddi_impldefs.h>
#include <sys/ddi_subrdefs.h>
#include <sys/pcie_impl.h>
#define NUM_LOGICAL_SLOTS 32
#define PPB_RANGE_LEN 2
#define PPB_32BIT_IO 1
#define PPB_32bit_MEM 1
#define PPB_MEMGRAIN 0x100000
#define PPB_IOGRAIN 0x1000
typedef struct slot_table {
} slot_table_t;
/*
* The variable controls the default setting of the command register
* for pci devices. See ppb_initchild() for details.
*/
void *, void *);
/*
* fm_init busop to initialize our children
*/
struct bus_ops ppb_bus_ops = {
0,
0,
0,
ndi_busop_get_eventcookie, /* (*bus_get_eventcookie)(); */
ndi_busop_add_eventcall, /* (*bus_add_eventcall)(); */
ndi_busop_remove_eventcall, /* (*bus_remove_eventcall)(); */
ndi_post_event, /* (*bus_post_event)(); */
0, /* (*bus_intr_ctl)(); */
0, /* (*bus_config)(); */
0, /* (*bus_unconfig)(); */
ppb_fm_init_child, /* (*bus_fm_init)(); */
NULL, /* (*bus_fm_fini)(); */
ppb_bus_enter, /* (*bus_enter)() */
ppb_bus_exit, /* (*bus_exit)() */
ppb_bus_power, /* (*bus_power)() */
ppb_intr_ops /* (*bus_intr_op)(); */
};
static struct cb_ops ppb_cb_ops = {
ppb_open, /* open */
ppb_close, /* close */
nulldev, /* strategy */
nulldev, /* print */
nulldev, /* dump */
nulldev, /* read */
nulldev, /* write */
ppb_ioctl, /* ioctl */
nodev, /* devmap */
nodev, /* mmap */
nodev, /* segmap */
nochpoll, /* poll */
ppb_prop_op, /* cb_prop_op */
NULL, /* streamtab */
CB_REV, /* rev */
nodev, /* int (*cb_aread)() */
nodev /* int (*cb_awrite)() */
};
static int ppb_probe(dev_info_t *);
DEVO_REV, /* devo_rev */
0, /* refcnt */
ppb_info, /* info */
nulldev, /* identify */
ppb_probe, /* probe */
ppb_attach, /* attach */
ppb_detach, /* detach */
nulldev, /* reset */
&ppb_cb_ops, /* driver operations */
&ppb_bus_ops, /* bus operations */
ppb_pwr, /* power */
ddi_quiesce_not_needed, /* quiesce */
};
/*
* Module linkage information for the kernel.
*/
&mod_driverops, /* Type of module */
"Standard PCI to PCI bridge nexus driver",
&ppb_ops, /* driver ops */
};
static struct modlinkage modlinkage = {
(void *)&modldrv,
};
/*
* soft state pointer and structure template:
*/
static void *ppb_state;
struct ppb_cfg_state {
};
typedef struct {
/*
* configuration register state for the bus:
*/
/*
* PM support
*/
/*
* HP support
*/
#define PPB_SOFT_STATE_CLOSED 0x00
#define PPB_SOFT_STATE_OPEN 0x01
#define PPB_SOFT_STATE_OPEN_EXCL 0x02
int fm_cap;
/*
* The following variable enables a workaround for the following obp bug:
*
* 1234181 - obp should set latency timer registers in pci
* configuration header
*
* Until this bug gets fixed in the obp, the following workaround should
* be enabled.
*/
/*
* The following variable enables a workaround for an obp bug to be
* submitted. A bug requesting a workaround fof this problem has
* been filed:
*
* 1235094 - need workarounds on positron nexus drivers to set cache
* line size registers
*
* Until this bug gets fixed in the obp, the following workaround should
* be enabled.
*/
/*
* forward function declarations:
*/
/*
* FMA error callback
* Register error handling callback with our parent. We will just call
* our children's error callbacks and return their status.
*/
const void *impl_data);
/*
* register/unregister our callback.
*/
static void ppb_removechild(dev_info_t *);
uint64_t pci_debug_flags = 0;
int
_init(void)
{
int e;
return (e);
}
int
_fini(void)
{
int e;
if ((e = mod_remove(&modlinkage)) == 0)
return (e);
}
int
{
}
/*ARGSUSED*/
static int
{
instance);
switch (infocmd) {
default:
return (DDI_FAILURE);
case DDI_INFO_DEVT2INSTANCE:
return (DDI_SUCCESS);
case DDI_INFO_DEVT2DEVINFO:
return (DDI_FAILURE);
return (DDI_SUCCESS);
}
}
/*ARGSUSED*/
static int
{
return (DDI_PROBE_SUCCESS);
}
/*ARGSUSED*/
static int
{
int instance;
switch (cmd) {
case DDI_ATTACH:
/*
* Make sure the "device_type" property exists.
*/
"device_type", "pci");
/*
* Allocate and get soft state structure.
*/
return (DDI_FAILURE);
return (DDI_FAILURE);
}
/*
* Before reading config registers, make sure power is
* on, and remains on.
*/
}
/*
* Check whether the "ranges" property is present.
* Otherwise create the ranges property by reading
* the configuration registers
*/
"ranges") == 0) {
}
}
/*
* Initialize hotplug support on this bus. At minimum
* (for non hotplug bus) this would create ":devctl" minor
* node to support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls
* to this bus. This all takes place if this nexus has hot-plug
* slots and successfully initializes Hot Plug Framework.
*/
/*
* create minor node for devctl interfaces
*/
DDI_NT_NEXUS, 0) != DDI_SUCCESS) {
}
return (DDI_FAILURE);
}
}
"ppb_attach(): this nexus %s hotplug slots\n",
return (DDI_SUCCESS);
case DDI_RESUME:
/*
* Get the soft state structure for the bridge.
*/
ppb = (ppb_devstate_t *)
return (DDI_SUCCESS);
}
return (DDI_FAILURE);
}
/*ARGSUSED*/
static int
{
switch (cmd) {
case DDI_DETACH:
/*
* And finally free the per-pci soft state after
* uninitializing hotplug support for this bus.
*/
ppb = (ppb_devstate_t *)
return (DDI_FAILURE);
else
}
return (DDI_SUCCESS);
case DDI_SUSPEND:
ppb = (ppb_devstate_t *)
return (DDI_SUCCESS);
}
return (DDI_FAILURE);
}
/*ARGSUSED*/
static int
{
register dev_info_t *pdip;
}
/*ARGSUSED*/
static int
{
int reglen;
int rn;
struct attachspec *as;
struct detachspec *ds;
int totreg;
switch (ctlop) {
case DDI_CTLOPS_REPORTDEV:
if (rdip == (dev_info_t *)0)
return (DDI_FAILURE);
return (DDI_SUCCESS);
case DDI_CTLOPS_INITCHILD:
case DDI_CTLOPS_UNINITCHILD:
return (DDI_SUCCESS);
case DDI_CTLOPS_ATTACH:
return (DDI_SUCCESS);
return (DDI_SUCCESS);
case DDI_CTLOPS_DETACH:
return (DDI_SUCCESS);
return (DDI_SUCCESS);
case DDI_CTLOPS_SIDDEV:
return (DDI_SUCCESS);
case DDI_CTLOPS_REGSIZE:
case DDI_CTLOPS_NREGS:
if (rdip == (dev_info_t *)0)
return (DDI_FAILURE);
break;
default:
}
*(int *)result = 0;
return (DDI_FAILURE);
if (ctlop == DDI_CTLOPS_NREGS)
else if (ctlop == DDI_CTLOPS_REGSIZE) {
return (DDI_FAILURE);
}
}
return (DDI_SUCCESS);
}
static dev_info_t *
{
;
return (cdip);
}
static int
{
if ((intr_op == DDI_INTROP_SUPPORTED_TYPES) ||
goto done;
/*
* If the interrupt-map property is defined at this
* node, it will have performed the interrupt
* translation as part of the property, so no
* rotation needs to be done.
*/
goto done;
/*
* Use the devices reg property to determine its
* PCI bus number and device number.
*/
return (DDI_FAILURE);
/* Spin the interrupt */
else
done:
/* Pass up the request to our parent. */
}
static int
{
}
/*
* name_child
*
* This function is called from init_child to name a node. It is
* also passed as a callback for node merging functions.
*
* return value: DDI_SUCCESS, DDI_FAILURE
*/
static int
{
char **unit_addr;
uint_t n;
/*
* Pseudo nodes indicate a prototype node with per-instance
* properties to be merged into the real h/w device node.
* The interpretation of the unit-address is DD[,F]
* where DD is the device id and F is the function.
*/
if (ndi_dev_is_persistent_node(child) == 0) {
return (DDI_FAILURE);
}
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
/*
* Get the address portion of the node name based on
* the function and device number.
*/
return (DDI_FAILURE);
}
if (func != 0)
else
return (DDI_SUCCESS);
}
static int
{
char name[MAXNAMELEN];
uint_t n;
/*
* Name the child
*/
return (DDI_FAILURE);
/*
* Pseudo nodes indicate a prototype node with per-instance
* properties to be merged into the real h/w device node.
* The interpretation of the unit-address is DD[,F]
* where DD is the device id and F is the function.
*/
if (ndi_dev_is_persistent_node(child) == 0) {
extern int pci_allow_pseudo_children;
/*
* Try to merge the properties from this prototype
* node into real h/w nodes.
*/
/*
* Merged ok - return failure to remove the node.
*/
return (DDI_FAILURE);
}
/* workaround for ddivs to run under PCI */
return (DDI_SUCCESS);
/*
* The child was not merged into a h/w node,
* but there's not much we can do with it other
* than return failure to cause the node to be removed.
*/
return (DDI_NOT_WELL_FORMED);
}
/*
* If hardware is PM capable, set up the power info structure.
* This also ensures the the bus will not be off (0MHz) otherwise
* system panics during a bus access.
*/
/*
* Create a pwr_info struct for child. Bus will be
* at full speed after creating info.
*/
#ifdef DEBUG
#endif
}
/*
* If configuration registers were previously saved by
* child (before it entered D3), then let the child do the
* restore to set up the config regs as it'll first need to
* power the device out of D3.
*/
"config-regs-saved-by-child") == 1) {
"INITCHILD: config regs to be restored by child"
return (DDI_SUCCESS);
}
"INITCHILD: config regs setup for %s@%s\n",
}
return (DDI_FAILURE);
}
/*
* Determine the configuration header type.
*/
/*
* Support for the "command-preserve" property.
*/
DDI_PROP_DONTPASS, "command-preserve", 0);
/*
* If the device has a bus control register then program it
* based on the settings in the command register.
*/
}
/*
* Initialize cache-line-size configuration register if needed.
*/
"cache-line-size", 0) == 0) {
if (n != 0) {
"cache-line-size", n);
}
}
/*
* Initialize latency timer configuration registers if needed.
*/
"latency-timer", 0) == 0) {
} else {
}
if (n != 0) {
"latency-timer", n);
}
}
/*
* SPARC PCIe FMA specific
*
* Note: parent_data for parent is created only if this is sparc PCI-E
* platform, for which, SG take a different route to handle device
* errors.
*/
return (DDI_FAILURE);
}
}
/*
*/
"pcix-update-cmd-reg", -1);
if (n != -1) {
"Workaround: value = %x\n", n);
pcix_set_cmd_reg(child, n);
}
return (DDI_SUCCESS);
}
static void
{
/*
* SG OPL FMA specific
*/
}
static void
{
"UNINITCHILD: removing pwr_info for %s@%s\n",
}
/*
* Strip the node to properly convert it back to prototype form
*/
}
/*
* If bridge is PM capable, set up PM state for nexus.
*/
static void
{
char *comp_array[5];
int i;
/*
* Determine if bridge is PM capable. If not, leave ppb_pwr_p NULL
* and return.
*/
return;
}
/*
* Locate and store the power management cap_ptr for future references.
*/
== DDI_FAILURE) {
" PM data structure not found in config header\n");
return;
}
/*
* Allocate PM state structure for ppb.
*/
return;
}
if (pmcap & PCI_PMCAP_D1) {
} else {
}
if (pmcap & PCI_PMCAP_D2) {
} else {
}
if (pmcsr_bse & PCI_PMCSR_BSE_BPCC_EN) {
} else {
return;
}
/*
* PCI states D0 and D3 always are supported for normal PCI
* devices. D1 and D2 are optional which are checked for above.
* Bridge function states D0-D3 correspond to secondary bus states
* B0-B3, EXCEPT if PCI_PMCSR_BSE_B2_B3 is set. In this case, setting
* the bridge function to D3 will set the bridge bus to state B2 instead
* of B3. D2 will not correspond to B2 (and in fact, probably
* won't be D2 capable). Implicitly, this means that if
* PCI_PMCSR_BSE_B2_B3 is set, the bus will not be B3 capable.
*/
if (pmcsr_bse & PCI_PMCSR_BSE_B2_B3) {
} else {
}
i = 0;
comp_array[i++] = "NAME=PCI bridge PM";
comp_array[i++] = "0=Clock/Power Off (B3)";
}
comp_array[i++] = "1=Clock Off (B2)";
}
comp_array[i++] = "2=Bus Inactive (B1)";
}
comp_array[i++] = "3=Full Power (B0)";
/*
* Create pm-components property. It does not already exist.
*/
"%s%d pm-components prop update failed",
return;
}
"%s%d fail to create pm-want-child-notification? prop",
return;
}
}
/*
* Remove PM state for nexus.
*/
static void
{
int low_lvl;
/*
* Determine the lowest power level supported.
*/
} else {
}
}
}
"pm-want-child-notification?") != DDI_PROP_SUCCESS) {
"%s%d unable to remove prop pm-want_child_notification?",
}
}
/*
* Examine the pmcsr register and return the software defined
* state (the difference being whether D3 means B2 or B3).
*/
int
{
/*
* Find out current power level
*/
return (DDI_FAILURE);
switch (pmcsr & PCI_PMCSR_STATE_MASK) {
case PCI_PMCSR_D0:
return (PM_LEVEL_B0);
case PCI_PMCSR_D1:
return (PM_LEVEL_B1);
case PCI_PMCSR_D2:
return (PM_LEVEL_B2);
case PCI_PMCSR_D3HOT:
return (PM_LEVEL_B2);
} else {
return (PM_LEVEL_B3);
}
}
/*NOTREACHED*/
return (PM_LEVEL_B3);
}
/*
* Power entry point. Called by the PM framework to change the
* current power state of the bus. This function must first verify that
* the requested power change is still valid.
*/
/*ARGSUSED*/
static int
{
char *str;
int lowest_lvl;
int old_lvl;
int new_lvl;
return (DDI_FAILURE);
}
/*
* Find out if the power setting is possible. If it is not,
* set component busy and return failure. If it is possible,
* and it is the lowest pwr setting possible, set component
* busy so that the framework does not try to lower any further.
*/
if (lowest_lvl > lvl) {
"lowest allowed is %d requested is %d\n",
lowest_lvl, lvl);
return (DDI_FAILURE);
} else if (lowest_lvl == lvl) {
} else {
}
return (DDI_FAILURE);
/*
* Save the current power level. This is the actual function level,
* not the translated bridge level stored in pwr_p->current_lvl
*/
switch (lvl) {
case PM_LEVEL_B0:
str = "PM_LEVEL_B0 (full speed)";
pmcsr |= PCI_PMCSR_D0;
break;
case PM_LEVEL_B1:
str = "PM_LEVEL_B1 (light sleep. No bus traffic allowed)";
return (DDI_FAILURE);
}
pmcsr |= PCI_PMCSR_D1;
break;
case PM_LEVEL_B2:
str = "PM_LEVEL_B2 (clock off)";
return (DDI_FAILURE);
}
/*
* If B3 isn't supported, use D3 for B2 to avoid the
* possible case that D2 for B2 isn't supported.
* Saves and extra check and state flag..
*/
pmcsr |= PCI_PMCSR_D3HOT;
} else {
pmcsr |= PCI_PMCSR_D2;
}
break;
case PM_LEVEL_B3:
str = "PM_LEVEL_B30 (clock and power off)";
return (DDI_FAILURE);
}
pmcsr |= PCI_PMCSR_D3HOT;
break;
default:
return (DDI_FAILURE);
}
/*
* Save config regs if going into HW state D3 (B2 or B3)
*/
return (DDI_FAILURE);
}
}
pmcsr);
/*
* No bus transactions should occur without waiting for
* settle time specified in PCI PM spec rev 2.1 sec 5.6.1
* To make things simple, just use the max time specified for
* all state transitions.
*/
/*
* Restore configuration registers if coming out of HW state D3
*/
panic("%s%d restore config regs failed",
}
/*NOTREACHED*/
}
return (DDI_SUCCESS);
}
/*
* Initialize hotplug framework if we are hotpluggable.
* Sets flag in the soft state if Hot Plug is supported and initialized
* properly.
*/
/*ARGSUSED*/
static void
{
"hotplug-capable")) {
"%s #%d: Failed setting hotplug framework",
} else
}
}
static void
{
int i = 0, rangelen = sizeof (ppb_ranges_t)/sizeof (int);
/*
* Create ranges for IO space
*/
ranges[i].parent_high = 0;
(PCI_REG_REL_M | PCI_ADDR_IO);
}
}
}
/*
* Create ranges for 32bit memory space
*/
ranges[i].parent_high = 0;
i++;
}
if (i) {
}
}
/* ARGSUSED */
static int
{
/*
* Make sure the open is for the right file type.
*/
return (EINVAL);
/*
* Get the soft state structure for the device.
*/
instance);
return (ENXIO);
/*
* Handle the open by tracking the device state.
*/
return (EBUSY);
}
} else {
return (EBUSY);
}
}
return (0);
}
/* ARGSUSED */
static int
{
return (EINVAL);
instance);
return (ENXIO);
return (0);
}
/*
* ppb_ioctl: devctl hotplug controls
*/
/* ARGSUSED */
static int
int *rvalp)
{
struct devctl_iocdata *dcp;
int rv = 0;
instance);
return (ENXIO);
/*
* We can use the generic implementation for these ioctls
*/
switch (cmd) {
case DEVCTL_DEVICE_GETSTATE:
case DEVCTL_DEVICE_ONLINE:
case DEVCTL_DEVICE_OFFLINE:
case DEVCTL_BUS_GETSTATE:
}
/*
* read devctl ioctl data
*/
return (EFAULT);
switch (cmd) {
case DEVCTL_DEVICE_RESET:
break;
case DEVCTL_BUS_QUIESCE:
if (bus_state == BUS_QUIESCED)
break;
break;
case DEVCTL_BUS_UNQUIESCE:
if (bus_state == BUS_ACTIVE)
break;
break;
case DEVCTL_BUS_RESET:
break;
case DEVCTL_BUS_RESETALL:
break;
default:
}
return (rv);
}
{
instance);
return (ENXIO);
}
/*
* Initialize our FMA resources
*/
static void
{
char *bus;
/*
* Request our capability level and get our parents capability
* and ibc.
*/
/*
* Register error callback with our parent.
*/
break;
}
}
/*
* Breakdown our FMA resources
*/
static void
{
/*
* Clean up allocated fm structures
*/
}
/*
* Initialize FMA resources for children devices. Called when
* child calls ddi_fm_init().
*/
/*ARGSUSED*/
static int
{
}
/*
* FMA registered error callback
*/
static int
{
/*
* errors handled by SPARC PCI-E framework for PCIe platforms
*/
return (DDI_FM_OK);
/*
* do the following for SPARC PCI platforms
*/
return (derr->fme_status);
}
static void
{
}
/* ARGSUSED */
static void
{
}