pci_pci.c revision 0c5eba8c5970fdedca3397ca86830ae5db5d98eb
1612N/A * The contents of this file are subject to the terms of the 1612N/A * Common Development and Distribution License (the "License"). 1612N/A * You may not use this file except in compliance with the License. 1612N/A * See the License for the specific language governing permissions 1612N/A * and limitations under the License. 1612N/A * When distributing Covered Code, include this CDDL HEADER in each 1612N/A * If applicable, add the following below this CDDL HEADER, with the 1612N/A * fields enclosed by brackets "[]" replaced with your own identifying 1612N/A * information: Portions Copyright [yyyy] [name of copyright owner] 1612N/A * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 1612N/A * Use is subject to license terms. 1879N/A#
pragma ident "%Z%%M% %I% %E% SMI" 1879N/A * Sun4u PCI to PCI bus bridge nexus driver 1612N/A * The variable controls the default setting of the command register 1612N/A * for pci devices. See ppb_initchild() for details. 1879N/A * fm_init busop to initialize our children 0,
/* (*bus_intr_ctl)(); */ 0,
/* (*bus_config)(); */ 0,
/* (*bus_unconfig)(); */ NULL,
/* (*bus_fm_fini)(); */ nodev,
/* int (*cb_aread)() */ nodev /* int (*cb_awrite)() */ * Module linkage information for the kernel. "Standard PCI to PCI bridge nexus driver %I%",
* soft state pointer and structure template: * configuration register state for the bus: * The following variable enables a workaround for the following obp bug: * 1234181 - obp should set latency timer registers in pci * Until this bug gets fixed in the obp, the following workaround should * The following variable enables a workaround for an obp bug to be * submitted. A bug requesting a workaround fof this problem has * 1235094 - need workarounds on positron nexus drivers to set cache * Until this bug gets fixed in the obp, the following workaround should * forward function declarations: * Register error handling callback with our parent. We will just call * our children's error callbacks and return their status. * Make sure the "device_type" property exists. * Allocate and get soft state structure. * Before reading config registers, make sure power is * Check whether the "ranges" property is present. * Otherwise create the ranges property by reading * the configuration registers * Initialize hotplug support on this bus. At minimum * (for non hotplug bus) this would create ":devctl" minor * node to support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls * to this bus. This all takes place if this nexus has hot-plug * slots and successfully initializes Hot Plug Framework. * create minor node for devctl interfaces "ppb_attach(): this nexus %s hotplug slots\n",
* Get the soft state structure for the bridge. * And finally free the per-pci soft state after * uninitializing hotplug support for this bus. * If the interrupt-map property is defined at this * node, it will have performed the interrupt * translation as part of the property, so no * rotation needs to be done. * Use the devices reg property to determine its * PCI bus number and device number. /* Pass up the request to our parent. */ * This function is called from init_child to name a node. It is * also passed as a callback for node merging functions. * return value: DDI_SUCCESS, DDI_FAILURE * Pseudo nodes indicate a prototype node with per-instance * properties to be merged into the real h/w device node. * The interpretation of the unit-address is DD[,F] * where DD is the device id and F is the function. * Get the address portion of the node name based on * the function and device number. * Pseudo nodes indicate a prototype node with per-instance * properties to be merged into the real h/w device node. * The interpretation of the unit-address is DD[,F] * where DD is the device id and F is the function. * Try to merge the properties from this prototype * node into real h/w nodes. * Merged ok - return failure to remove the node. /* workaround for ddivs to run under PCI */ * The child was not merged into a h/w node, * but there's not much we can do with it other * than return failure to cause the node to be removed. * If hardware is PM capable, set up the power info structure. * This also ensures the the bus will not be off (0MHz) otherwise * system panics during a bus access. * Create a pwr_info struct for child. Bus will be * at full speed after creating info. * If configuration registers were previously saved by * child (before it entered D3), then let the child do the * restore to set up the config regs as it'll first need to * power the device out of D3. "config-regs-saved-by-child") ==
1) {
"INITCHILD: config regs to be restored by child" "INITCHILD: config regs setup for %s@%s\n",
* Determine the configuration header type. * Support for the "command-preserve" property. * If the device has a bus control register then program it * based on the settings in the command register. * Initialize cache-line-size configuration register if needed. "cache-line-size", 0) == 0) {
* Initialize latency timer configuration registers if needed. "latency-timer", 0) == 0) {
* SPARC PCIe FMA specific * Note: parent_data for parent is created only if this is sparc PCI-E * platform, for which, SG take a different route to handle device * Check to see if the XMITS/PCI-X workaround applies. "pcix-update-cmd-reg", -
1);
"Workaround: value = %x\n", n);
"UNINITCHILD: removing pwr_info for %s@%s\n",
* Strip the node to properly convert it back to prototype form * If bridge is PM capable, set up PM state for nexus. * Determine if bridge is PM capable. If not, leave ppb_pwr_p NULL * Locate and store the power management cap_ptr for future references. " PM data structure not found in config header\n");
* Allocate PM state structure for ppb. * PCI states D0 and D3 always are supported for normal PCI * devices. D1 and D2 are optional which are checked for above. * Bridge function states D0-D3 correspond to secondary bus states * B0-B3, EXCEPT if PCI_PMCSR_BSE_B2_B3 is set. In this case, setting * the bridge function to D3 will set the bridge bus to state B2 instead * of B3. D2 will not correspond to B2 (and in fact, probably * won't be D2 capable). Implicitly, this means that if * PCI_PMCSR_BSE_B2_B3 is set, the bus will not be B3 capable. * Create pm-components property. It does not already exist. "%s%d pm-components prop update failed",
"%s%d fail to create pm-want-child-notification? prop",
* Remove PM state for nexus. * Determine the lowest power level supported. "%s%d unable to remove prop pm-want_child_notification?",
* Examine the pmcsr register and return the software defined * state (the difference being whether D3 means B2 or B3). * Find out current power level * Power entry point. Called by the PM framework to change the * current power state of the bus. This function must first verify that * the requested power change is still valid. * Find out if the power setting is possible. If it is not, * set component busy and return failure. If it is possible, * and it is the lowest pwr setting possible, set component * busy so that the framework does not try to lower any further. "lowest allowed is %d requested is %d\n",
* Save the current power level. This is the actual function level, * not the translated bridge level stored in pwr_p->current_lvl str =
"PM_LEVEL_B0 (full speed)";
str =
"PM_LEVEL_B1 (light sleep. No bus traffic allowed)";
str =
"PM_LEVEL_B2 (clock off)";
* If B3 isn't supported, use D3 for B2 to avoid the * possible case that D2 for B2 isn't supported. * Saves and extra check and state flag.. str =
"PM_LEVEL_B30 (clock and power off)";
* Save config regs if going into HW state D3 (B2 or B3) * No bus transactions should occur without waiting for * settle time specified in PCI PM spec rev 2.1 sec 5.6.1 * To make things simple, just use the max time specified for * Restore configuration registers if coming out of HW state D3 panic(
"%s%d restore config regs failed",
* Initialize hotplug framework if we are hotpluggable. * Sets flag in the soft state if Hot Plug is supported and initialized "%s #%d: Failed setting hotplug framework",
* Create ranges for IO space * Create ranges for 32bit memory space * Make sure the open is for the right file type. * Get the soft state structure for the device. * Handle the open by tracking the device state. * ppb_ioctl: devctl hotplug controls * We can use the generic implementation for these ioctls * Initialize our FMA resources * Request our capability level and get our parents capability * Register error callback with our parent. * Breakdown our FMA resources * Clean up allocated fm structures * Initialize FMA resources for children devices. Called when * child calls ddi_fm_init(). * FMA registered error callback * errors handled by SPARC PCI-E framework for PCIe platforms * do the following for SPARC PCI platforms